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Razvalyaev
2025-05-09 21:34:37 +03:00
parent a043335d9b
commit c6269ca448
312 changed files with 173574 additions and 174744 deletions
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49
Code/Core/Inc/gpio.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.h
* @brief This file contains all the function prototypes for
* the gpio.c file
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ GPIO_H__ */

69
Code/Core/Inc/main.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

495
Code/Core/Inc/stm32f4xx_hal_conf.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_hal_conf_template.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_FMPSMBUS_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "stm32f4xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
#include "stm32f4xx_hal_eth_legacy.h"
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32f4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32f4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f4xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_FMPI2C_MODULE_ENABLED
#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
#ifdef HAL_FMPSMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_fmpsmbus.h"
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32f4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32f4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */

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Code/Core/Inc/stm32f4xx_it.h
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@@ -1,66 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */

90
Code/Core/Inc/trace.h
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// TRACE SETTINGS
#define TRACE_MB_UART_ENABLE 14
//#define TRACE_MB_TIM_ENABLE 15
#define TRACE_TIM_PWM_ENABLE 15
//#define TRACE_PWM_REINIT_ENABLE 15
//#define TRACE_TIM_DEAD_TIME_ENABLE 14
//#define TRACE_TIM_CTRL_ENABLE 15
#define TRACE_GPIO_ENTER(_gpio_,_pin_) (_gpio_)->BSRR = (1<<(_pin_))
#define TRACE_GPIO_EXIT(_gpio_,_pin_) (_gpio_)->BSRR = (1<<((_pin_)+16))
#ifdef TRACE_MB_UART_ENABLE
#define Trace_MB_UART_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_MB_UART_ENABLE)
#define Trace_MB_UART_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_MB_UART_ENABLE)
#endif
#ifdef TRACE_MB_TIM_ENABLE
#define Trace_MB_TIM_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_MB_TIM_ENABLE)
#define Trace_MB_TIM_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_MB_TIM_ENABLE)
#endif
#ifdef TRACE_TIM_PWM_ENABLE
#define Trace_PWM_TIM_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_TIM_PWM_ENABLE)
#define Trace_PWM_TIM_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_TIM_PWM_ENABLE)
#endif
#ifdef TRACE_PWM_REINIT_ENABLE
#define Trace_PWM_reInit_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_PWM_REINIT_ENABLE)
#define Trace_PWM_reInit_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_PWM_REINIT_ENABLE)
#endif
#ifdef TRACE_TIM_DEAD_TIME_ENABLE
#define Trace_PWM_DeadTime_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_TIM_DEAD_TIME_ENABLE)
#define Trace_PWM_DeadTime_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_TIM_DEAD_TIME_ENABLE)
#endif
#ifdef TRACE_TIM_CTRL_ENABLE
#define Trace_CTRL_TIM_Enter() TRACE_GPIO_ENTER(GPIOD, TRACE_TIM_CTRL_ENABLE)
#define Trace_CTRL_TIM_Exit() TRACE_GPIO_EXIT(GPIOD, TRACE_TIM_CTRL_ENABLE)
#endif
#ifndef Trace_MB_UART_Enter
#define Trace_MB_UART_Enter()
#endif
#ifndef Trace_MB_UART_Exit
#define Trace_MB_UART_Exit()
#endif
#ifndef Trace_MB_TIM_Enter
#define Trace_MB_TIM_Enter()
#endif
#ifndef Trace_MB_TIM_Exit
#define Trace_MB_TIM_Exit()
#endif
#ifndef Trace_PWM_TIM_Enter
#define Trace_PWM_TIM_Enter()
#endif
#ifndef Trace_PWM_TIM_Exit
#define Trace_PWM_TIM_Exit()
#endif
#ifndef Trace_CTRL_TIM_Enter
#define Trace_CTRL_TIM_Enter()
#endif
#ifndef Trace_CTRL_TIM_Exit
#define Trace_CTRL_TIM_Exit()
#endif
#ifndef Trace_PWM_reInit_Enter
#define Trace_PWM_reInit_Enter()
#endif
#ifndef Trace_PWM_reInit_Exit
#define Trace_PWM_reInit_Exit()
#endif
#ifndef Trace_PWM_DeadTime_Enter
#define Trace_PWM_DeadTime_Enter()
#endif
#ifndef Trace_PWM_DeadTime_Exit
#define Trace_PWM_DeadTime_Exit()
#endif

61
Code/Core/Src/gpio.c
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@@ -1,61 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.c
* @brief This file provides code for the configuration
* of all used GPIO pins.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "gpio.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure GPIO */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/*Configure GPIO pin : PC13 */
GPIO_InitStruct.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13 | GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

256
Code/Core/Src/main.c
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@@ -1,256 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "gpio.h"
#include "math.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "pwm.h"
#include "rs_message.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
UART_SettingsTypeDef modbus1_suart;
TIM_SettingsTypeDef modbus1_stim;
RS_HandleTypeDef hmodbus1;
RS_MsgTypeDef MODBUS_MSG;
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */
//MODBUS_HandleTypeDef hmodbus1;
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/**
* @brief reInitialize Peripheral.
* @note Данная функция необходима, если запрос на реинициализацию приходит от другой периферии.
* И чтобы не реинициализировать периферию в прерывании, она реинится в main while(1).
*/
void Periph_reInit(void)
{
// wait for reinit modbus coil (requested by modbus interrupt)
if(MB_Read_Coil_Global(COIL_UART_CTRL_GLOBAL, NULL) && hmodbus1.fTX_Done)
{
MB_Write_Coil_Global(COIL_UART_CTRL_GLOBAL, RESET_COIL);
modbus1_suart.huart.Init.BaudRate = uart_ctrl[R_UART_CTRL_SPEED];
RS_ReInit_UART(&hmodbus1 ,&modbus1_suart);
}
// fait for reinit log timer (requested by modbus interrupt)
if((TIM_CTRL.sTimFreqHz != log_ctrl[R_LOG_CTRL_LOG_HZ]) && (log_ctrl[R_LOG_CTRL_LOG_HZ] != 0))
{
TIM_CTRL.sTimFreqHz = log_ctrl[R_LOG_CTRL_LOG_HZ];
// clear logs params
Set_Log_Params();
TIM_Base_MspDeInit(&TIM_CTRL.htim);
Control_Timer_ReInit(&TIM_CTRL);
}
// READ TIM_PWM_HZ
if(hpwm1.stim.sTimFreqHz != pwm_ctrl[R_PWM_CTRL_PWM_HZ])
{
hpwm1.stim.sTimFreqHz = pwm_ctrl[R_PWM_CTRL_PWM_HZ];
pwm_ctrl[R_PWM_CTRL_PWM_HZ] = hpwm1.stim.sTimFreqHz;
// update logs params
Set_Log_Params();
// reinit tim
PWM_Sine_ReInit(&hpwm1);
PWM_SlavePhase_reInit(&hpwm2);
PWM_SlavePhase_reInit(&hpwm3);
}
}
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
__HAL_DBGMCU_FREEZE_TIM1();
__HAL_DBGMCU_FREEZE_TIM3();
__HAL_DBGMCU_FREEZE_TIM4();
__HAL_DBGMCU_FREEZE_TIM12();
// 0xE0042008
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
//SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
// init params for pwm and log
pwm_ctrl[R_PWM_CTRL_PWM_VALUE] = 2560;
pwm_ctrl[R_PWM_CTRL_PWM_HZ] = HZ_TIMER_PWM;
pwm_ctrl[R_PWM_CTRL_MIN_PULSE_DUR] = 30;
pwm_ctrl[R_PWM_CTRL_DEAD_TIME] = 1;
pwm_ctrl[R_PWM_CTRL_SIN_TABLE_SIZE] = SIN_TABLE_SIZE_MAX;
//MB_Write_Coil_Global(COIL_PWM_DC_MODE_GLOBAL, SET_COIL);
MB_Write_Coil_Global(COIL_PWM_CH_MODE_GLOBAL, SET_COIL);
MB_Write_Coil_Global(COIL_PWM_PHASE_MODE_GLOBAL, SET_COIL);
log_ctrl[R_LOG_CTRL_LOG_HZ] = HZ_TIMER_CTRL;
log_ctrl[R_LOG_CTRL_LOG_SIZE] = 50;
log_ctrl[R_LOG_CTRL_LOG_PWM_NUMB] = 3;
WriteSettingsToMem();
MODBUS_FirstInit();
Control_Timer_FirstInit();
PWM_Sine_FirstInit();
//---------------TEST MODBUS------------------
// MODBUS_Transmit_IT(&hmodbus1, &MODBUS_MSG);
//RS_Receive_IT(&hmodbus1, &MODBUS_MSG);
while (1)
{
/* USER CODE END WHILE */
Periph_reInit();
/* USER CODE BEGIN 3 */
// HAL_Delay(200);
// MB_Toogle_Coil_Local(&GPIOD->ODR, COIL_GPIOD_LED3);
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 72;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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Code/Core/Src/stm32f4xx_hal_msp.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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Code/Core/Src/stm32f4xx_it.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
return;
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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Code/Core/Src/system_stm32f4xx.c
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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
(void)(tmp);
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
clock */
RCC->AHB1ENR |= 0x0000007D;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOA->MODER |= 0x00008000;
/* Configure PDx pins speed to 50 MHz */
GPIOA->OSPEEDR |= 0x00008000;
/* Configure PDx pins Output type to push-pull */
GPIOA->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOA->PUPDR |= 0x00000000;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOC->MODER |= 0x00000A00;
/* Configure PDx pins speed to 50 MHz */
GPIOC->OSPEEDR |= 0x00000A00;
/* Configure PDx pins Output type to push-pull */
GPIOC->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOC->PUPDR |= 0x00000000;
#endif /* STM32F446xx */
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp);
}
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

31
Code/GENERAL/gpio_general.c
View File

@@ -1,31 +0,0 @@
/**********************************TIM**************************************
Данный файл содержит базовые функции для инициализации портов.
***************************************************************************/
#include "gpio_general.h"
//-------------------------------------------------------------------
//------------------------GPIO INIT FUNCTIONS------------------------
HAL_StatusTypeDef GPIO_Clock_Enable(GPIO_TypeDef *GPIOx)
{
HAL_StatusTypeDef status = HAL_OK;
// choose port for enable clock
if (GPIOx==GPIOA)
__HAL_RCC_GPIOA_CLK_ENABLE();
else if (GPIOx==GPIOB)
__HAL_RCC_GPIOB_CLK_ENABLE();
else if (GPIOx==GPIOC)
__HAL_RCC_GPIOC_CLK_ENABLE();
else if (GPIOx==GPIOD)
__HAL_RCC_GPIOD_CLK_ENABLE();
else if (GPIOx==GPIOE)
__HAL_RCC_GPIOE_CLK_ENABLE();
else
status = HAL_ERROR;
return status;
}
//------------------------GPIO INIT FUNCTIONS------------------------
//-------------------------------------------------------------------

17
Code/GENERAL/gpio_general.h
View File

@@ -1,17 +0,0 @@
/**********************************TIM**************************************
Данный файл содержит объявления базовых функции и дефайны для инициализации
портов.
***************************************************************************/
#ifndef __GPIO_GENERAL_H_
#define __GPIO_GENERAL_H_
#include "periph_general.h"
/////////////////////////////////////////////////////////////////////
///////////////////////////---FUNCTIONS---///////////////////////////
HAL_StatusTypeDef GPIO_Clock_Enable(GPIO_TypeDef *GPIOx);
///////////////////////////---FUNCTIONS---///////////////////////////
#endif // __GPIO_GENERAL_H_

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/**********************************TIM**************************************
Данный файл содержит инклюды и дефайны для всех библиотек базовой перефирии.
***************************************************************************/
#ifndef __PERIPH_GENERAL_H_
#define __PERIPH_GENERAL_H_
// user includes
#include "modbus.h"
#include "trace.h"
extern void Error_Handler(void);
#define ERROR_HANDLER_NAME(_params_) Error_Handler(_params_)
/* If error handler not defined - set void */
#ifndef ERROR_HANDLER_NAME
#define ((void)0U)
#endif // ERROR_HANDLER_NAME
#include "stm32f4xx_hal.h"
#include "gpio_general.h"
#include "uart_general.h"
#include "tim_general.h"
#endif // __PERIPH_GENERAL_H_

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/**********************************TIM**************************************
Данный файл содержит базовые функции для инициализации таймеров.
//-------------------Функции-------------------//
@func tim initialize
- TIM_Base_Init Инициализация TIM
- TIM_Output_PWM_Init Инициализация PWM с выводом на GPIO
- TIM_Base_MspInit Аналог HAL_MspInit для таймера
***************************************************************************/
#include "tim_general.h"
//-------------------------------------------------------------------
//-------------------------TIM INIT FUNCTIONS------------------------
/**
* @brief Initialize TIM with TIM_SettingsTypeDef structure.
* @param stim - указатель на структуру с настройками таймера.
* @return HAL status.
* @note Данная структура содержит хендл таймера и структуры для его настройки.
*/
HAL_StatusTypeDef TIM_Base_Init(TIM_SettingsTypeDef *stim)
{ // function takes structure for init
// check that htim is defined
if (stim->htim.Instance == NULL)
return HAL_ERROR;
if(stim->sTickBaseMHz) // if tickbase isnt disable
{
if((stim->sTimAHBFreqMHz == 0))
return HAL_ERROR;
stim->htim.Init.Prescaler = (stim->sTimAHBFreqMHz*stim->sTickBaseMHz) - 1;
if ((stim->sTimFreqHz != NULL))
stim->htim.Init.Period = ((1000000/stim->sTickBaseMHz) / stim->sTimFreqHz) - 1;
}
// if freq is too high (period too small for choosen base) OR base is too high (period too small for choosen base)
if((stim->htim.Init.Period == NULL) || (stim->htim.Init.Prescaler == NULL))
{
return HAL_ERROR;
}
// fix overflow of presc and period if need
for(int i = 0; (stim->htim.Init.Prescaler > 0xFFFF) || (stim->htim.Init.Period > 0xFFFF); i++)
{
if (i>10) // if it isnt fixed after 10 itteration - return HAL_ERRPOR
{
return HAL_ERROR;
}
// if timbase is too big (prescaller too big for choosen base from MHZ)
if(stim->htim.Init.Prescaler > 0xFFFF)
{
// переносим часть пресскалера в период
stim->htim.Init.Prescaler = ((stim->htim.Init.Prescaler + 1)/2) - 1;
stim->htim.Init.Period = ((stim->htim.Init.Period + 1)*2) - 1;
// обновляем TickBase
stim->sTickBaseMHz /= 2;
}
// if freq is too low (period too big for choosen base)
if(stim->htim.Init.Period > 0xFFFF)
{
// переносим часть периода в прескалер
stim->htim.Init.Period = ((stim->htim.Init.Period + 1)/2) - 1;
stim->htim.Init.Prescaler = ((stim->htim.Init.Prescaler + 1)*2) - 1;
// обновляем TickBase
stim->sTickBaseMHz *= 2;
}
}
//-------------TIM BASE INIT----------------
// tim base init
TIM_Base_MspInit(&stim->htim, stim->sTimMode);
if (HAL_TIM_Base_Init(&stim->htim) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
//-------------CLOCK SRC INIT---------------
// fill sClockSourceConfig if its NULL
if (stim->sClockSourceConfig.ClockSource == NULL)
stim->sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
// clock source init
if (HAL_TIM_ConfigClockSource(&stim->htim, &stim->sClockSourceConfig) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
//--------------SLAVE INIT------------------
// if slave mode enables - config it
if (stim->sSlaveConfig.SlaveMode)
{
// slave mode init
if (HAL_TIM_SlaveConfigSynchro(&stim->htim, &stim->sSlaveConfig) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
}
//--------------MASTER INIT-----------------
// master mode init
if (HAL_TIMEx_MasterConfigSynchronization(&stim->htim, &stim->sMasterConfig) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
//--------------BDTR INIT-----------------
if (HAL_TIMEx_ConfigBreakDeadTime(&stim->htim, &stim->sBreakDeadTimeConfig) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
//----------------IT CLEAR-------------------
__HAL_TIM_CLEAR_IT(&stim->htim, TIM_IT_UPDATE);
stim->htim.Instance->CNT = 0;
return HAL_OK;
}
/**
* @brief Initialize PWM Channel and GPIO for output.
* @param htim - указатель на хендл таймера.
* @param sConfigOC - указатель на настрйоки канала таймера.
* @param TIM_CHANNEL - канал таймера для настройки.
* @param GPIOx - порт для вывода ШИМ.
* @param GPIO_PIN - пин для вывода ШИМ.
* @return HAL status.
*/
HAL_StatusTypeDef TIM_Output_PWM_Init(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfigOC, uint32_t TIM_CHANNEL, GPIO_TypeDef *GPIOx, uint32_t GPIO_PIN)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
HAL_StatusTypeDef RES = HAL_ERROR;
// setup channel for pwm
if (HAL_TIM_PWM_ConfigChannel(htim, sConfigOC, TIM_CHANNEL) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
// choose port for enable clock
if(GPIO_Clock_Enable(GPIOx) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
GPIO_InitStruct.Pin = GPIO_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = TIM_Alternate_Mapping(htim->Instance);
if(GPIO_InitStruct.Alternate)
HAL_GPIO_Init(GPIOx, &GPIO_InitStruct);
return HAL_OK;
}
/**
* @brief Initialize TIMs clock and interrupt.
* @param htim - указатель на хендл таймера.
* @note Чтобы не генерировать функцию с иницилизацией неиспользуемых таймеров,
дефайнами в tim_general.h определяются используемые таймеры.
*/
void TIM_Base_MspInit(TIM_HandleTypeDef* htim, TIM_ITModeTypeDef it_mode)
{
it_mode = it_mode&TIM_IT_CONF;
#ifdef USE_TIM1
if(htim->Instance==TIM1)
{
/* TIM2 clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
/* TIM2 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
}
}
#endif
#ifdef USE_TIM2
if(htim->Instance==TIM2)
{
/* TIM2 clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
/* TIM2 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM2_IRQn);
}
}
#endif
#ifdef USE_TIM3
if(htim->Instance==TIM3)
{
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
/* TIM3 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM3_IRQn);
}
}
#endif
#ifdef USE_TIM4
if(htim->Instance==TIM4)
{
/* TIM4 clock enable */
__HAL_RCC_TIM4_CLK_ENABLE();
/* TIM4 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM4_IRQn);
}
}
#endif
#ifdef USE_TIM5
if(htim->Instance==TIM5)
{
/* TIM5 clock enable */
__HAL_RCC_TIM5_CLK_ENABLE();
/* TIM5 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM5_IRQn);
}
}
#endif
#ifdef USE_TIM6
if(htim->Instance==TIM6)
{
/* TIM6 clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
/* TIM6 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
}
}
#endif
#ifdef USE_TIM7
if(htim->Instance==TIM7)
{
/* TIM7 clock enable */
__HAL_RCC_TIM7_CLK_ENABLE();
/* TIM7 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM7_IRQn);
}
}
#endif
#ifdef USE_TIM8
if(htim->Instance==TIM8)
{
/* TIM8 clock enable */
__HAL_RCC_TIM8_CLK_ENABLE();
/* TIM8 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
}
}
#endif
#ifdef USE_TIM9
if(htim->Instance==TIM9)
{
/* TIM9 clock enable */
__HAL_RCC_TIM9_CLK_ENABLE();
/* TIM9 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM1_BRK_TIM9_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn);
}
}
#endif
#ifdef USE_TIM10
if(htim->Instance==TIM10)
{
/* TIM10 clock enable */
__HAL_RCC_TIM10_CLK_ENABLE();
/* TIM10 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
}
}
#endif
#ifdef USE_TIM11
if(htim->Instance==TIM11)
{
/* TIM11 clock enable */
__HAL_RCC_TIM11_CLK_ENABLE();
/* TIM11 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn);
}
}
#endif
#ifdef USE_TIM12
if(htim->Instance==TIM12)
{
/* TIM12 clock enable */
__HAL_RCC_TIM12_CLK_ENABLE();
/* TIM12 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM8_BRK_TIM12_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn);
}
}
#endif
#ifdef USE_TIM13
if(htim->Instance==TIM13)
{
/* TIM13 clock enable */
__HAL_RCC_TIM13_CLK_ENABLE();
/* TIM13 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
}
}
#endif
#ifdef USE_TIM14
if(htim->Instance==TIM14)
{
/* TIM14 clock enable */
__HAL_RCC_TIM14_CLK_ENABLE();
/* TIM14 interrupt Init */
if(it_mode)
{
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
}
}
#endif
}
/**
* @brief DeInitialize TIMs clock and interrupt.
* @param htim - указатель на хендл таймера.
* @note Чтобы не генерировать функцию с деиницилизацией неиспользуемых таймеров,
дефайнами в tim_general.h определяются используемые таймеры.
*/
void TIM_Base_MspDeInit(TIM_HandleTypeDef* htim)
{
#ifdef USE_TIM1
if(htim->Instance==TIM1)
{
__HAL_RCC_TIM1_FORCE_RESET();
__HAL_RCC_TIM1_RELEASE_RESET();
}
#endif
#ifdef USE_TIM2
if(htim->Instance==TIM2)
{
__HAL_RCC_TIM2_FORCE_RESET();
__HAL_RCC_TIM2_RELEASE_RESET();
}
#endif
#ifdef USE_TIM3
if(htim->Instance==TIM3)
{
__HAL_RCC_TIM3_FORCE_RESET();
__HAL_RCC_TIM3_RELEASE_RESET();
}
#endif
#ifdef USE_TIM4
if(htim->Instance==TIM4)
{
__HAL_RCC_TIM4_FORCE_RESET();
__HAL_RCC_TIM4_RELEASE_RESET();
}
#endif
#ifdef USE_TIM5
if(htim->Instance==TIM5)
{
__HAL_RCC_TIM5_FORCE_RESET();
__HAL_RCC_TIM5_RELEASE_RESET();
}
#endif
#ifdef USE_TIM6
if(htim->Instance==TIM6)
{
__HAL_RCC_TIM6_FORCE_RESET();
__HAL_RCC_TIM6_RELEASE_RESET();
}
#endif
#ifdef USE_TIM7
if(htim->Instance==TIM7)
{
__HAL_RCC_TIM7_FORCE_RESET();
__HAL_RCC_TIM7_RELEASE_RESET();
}
#endif
#ifdef USE_TIM8
if(htim->Instance==TIM8)
{
__HAL_RCC_TIM8_FORCE_RESET();
__HAL_RCC_TIM8_RELEASE_RESET();
}
#endif
#ifdef USE_TIM9
if(htim->Instance==TIM9)
{
__HAL_RCC_TIM9_FORCE_RESET();
__HAL_RCC_TIM9_RELEASE_RESET();
}
#endif
#ifdef USE_TIM10
if(htim->Instance==TIM10)
{
__HAL_RCC_TIM10_FORCE_RESET();
__HAL_RCC_TIM10_RELEASE_RESET();
}
#endif
#ifdef USE_TIM11
if(htim->Instance==TIM11)
{
__HAL_RCC_TIM11_FORCE_RESET();
__HAL_RCC_TIM11_RELEASE_RESET();
}
#endif
#ifdef USE_TIM12
if(htim->Instance==TIM12)
{
__HAL_RCC_TIM12_FORCE_RESET();
__HAL_RCC_TIM12_RELEASE_RESET();
}
#endif
#ifdef USE_TIM13
if(htim->Instance==TIM13)
{
__HAL_RCC_TIM13_FORCE_RESET();
__HAL_RCC_TIM13_RELEASE_RESET();
}
#endif
#ifdef USE_TIM14
if(htim->Instance==TIM14)
{
__HAL_RCC_TIM14_FORCE_RESET();
__HAL_RCC_TIM14_RELEASE_RESET();
}
#endif
}
//-------------------------TIM INIT FUNCTIONS------------------------
//-------------------------------------------------------------------

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/**********************************TIM**************************************
Данный файл содержит объявления базовых функции и дефайны для инициализации
таймеров.
***************************************************************************/
#ifndef __TIM_GENERAL_H_
#define __TIM_GENERAL_H_
/////////////////////////////////////////////////////////////////////
/////////////////////////---USER SETTINGS---/////////////////////////
#define HAL_TIM_MODULE_ENABLED // need to uncomment this define in stm32f4xx_hal_conf.h
#define USE_TIM1
#define USE_TIM2
#define USE_TIM3
#define USE_TIM4
#define USE_TIM5
#define USE_TIM6
#define USE_TIM7
#define USE_TIM8
#define USE_TIM9
#define USE_TIM10
#define USE_TIM11
#define USE_TIM12
#define USE_TIM13
#define USE_TIM14
/* note: used uart defines in modbus.h */
/////////////////////////---USER SETTINGS---/////////////////////////
#include "periph_general.h"
/////////////////////////////////////////////////////////////////////
////////////////////////////---DEFINES---////////////////////////////
#define TIM_IT_CONF_Pos 0
//#define TIM_PWM_CONF_Pos 1
//#define TIM_CLCK_SRC_CONF_Pos 2
//#define TIM_SLAVE_CONF_Pos 3
//#define TIM_MASTER_CONF_Pos 4
//#define TIM_BDTR_CONF_Pos 5
#define TIM_IT_CONF (1<<(TIM_IT_CONF_Pos))
//#define TIM_PWM_CONF (1<<(TIM_PWM_Pos))
#define TIM_Alternate_Mapping(INSTANCE) ((((INSTANCE) == TIM1) || ((INSTANCE) == TIM2))? GPIO_AF1_TIM1: \
(((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5))? GPIO_AF2_TIM3: \
(((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM10) || ((INSTANCE) == TIM11))? GPIO_AF3_TIM8: \
(((INSTANCE) == TIM12) || ((INSTANCE) == TIM13) || ((INSTANCE) == TIM14))? GPIO_AF9_TIM12: \
(0))
////////////////////////////---DEFINES---////////////////////////////]
/////////////////////////////////////////////////////////////////////
///////////////////////---STRUCTURES & ENUMS---//////////////////////
typedef enum
{
TIM_DEFAULT = 0,
TIM_IT_MODE = TIM_IT_CONF,
// TIM_PWM_MODE = TIM_PWM_ENABLE,
// TIM_PWM_IT_MODE = TIM_PWM_ENABLE | TIM_IT_CONF,
}TIM_ITModeTypeDef;
typedef enum
{
TIM_Base_Disable = 0,
TIM_TickBase_1US = 1,
TIM_TickBase_10US = 10,
TIM_TickBase_100US = 100,
TIM_TickBase_1MS = 1000,
TIM_TickBase_10MS = 10000,
TIM_TickBase_100MS = 100000,
}TIM_MHzTickBaseTypeDef;
typedef struct // struct with settings for custom function
{
TIM_HandleTypeDef htim;
TIM_ClockConfigTypeDef sClockSourceConfig;
TIM_SlaveConfigTypeDef sSlaveConfig;
TIM_MasterConfigTypeDef sMasterConfig;
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig;
TIM_ITModeTypeDef sTimMode;
TIM_MHzTickBaseTypeDef sTickBaseMHz;
float sTimAHBFreqMHz;
uint32_t sTimFreqHz;
}TIM_SettingsTypeDef;
///////////////////////---STRUCTURES & ENUMS---//////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////////---FUNCTIONS---///////////////////////////
/**
* @brief Initialize TIM with TIM_SettingsTypeDef structure.
* @param stim - указатель на структуру с настройками таймера.
* @return HAL status.
* @note Данная структура содержит хендл таймера и структуры для его настройки.
*/
HAL_StatusTypeDef TIM_Base_Init(TIM_SettingsTypeDef* stim);
/**
* @brief Initialize PWM Channel and GPIO for output.
* @param htim - указатель на хендл таймера.
* @param sConfigOC - указатель на настрйоки канала таймера.
* @param TIM_CHANNEL - канал таймера для настройки.
* @param GPIOx - порт для вывода ШИМ.
* @param GPIO_PIN - пин для вывода ШИМ.
* @return HAL status.
*/
HAL_StatusTypeDef TIM_Output_PWM_Init(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfigOC, uint32_t TIM_CHANNEL, GPIO_TypeDef *GPIOx, uint32_t PWM_PIN);
/**
* @brief Initialize TIMs clock and interrupt.
* @param htim - указатель на хендл таймера.
* @note Чтобы не генерировать функцию с иницилизацией неиспользуемых таймеров,
дефайнами в tim_general.h определяются используемые таймеры.
*/
void TIM_Base_MspInit(TIM_HandleTypeDef* htim, TIM_ITModeTypeDef it_mode);
/**
* @brief DeInitialize TIMs clock and interrupt.
* @param htim - указатель на хендл таймера.
* @note Чтобы не генерировать функцию с деиницилизацией неиспользуемых таймеров,
дефайнами в tim_general.h определяются используемые таймеры.
*/
void TIM_Base_MspDeInit(TIM_HandleTypeDef* htim);
///////////////////////////---FUNCTIONS---///////////////////////////
#endif // __TIM_GENERAL_H_

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/*********************************UART**************************************
Данный файл содержит базовые функции для инициализации UART.
//-------------------Функции-------------------//
@func users
- UART_Base_Init Инициализация UART
@func uart initialize
- UART_GPIO_Init Инициализация GPIO для UART
- UART_DMA_Init Инициализация DMA для UART
- UART_MspInit Аналог HAL_MspInit для UART
- UART_MspDeInit Аналог HAL_MspDeInit для UART
***************************************************************************/
#include "uart_general.h"
//-------------------------------------------------------------------
//------------------------UART INIT FUNCTIONS------------------------
/**
* @brief Initialize UART with UART_SettingsTypeDef structure.
* @param suart - указатель на структуру с настройками UART.
* @return HAL status.
* @note Данная структура содержит хендл ЮАРТ и настройки перефирии (GPIO)
*/
HAL_StatusTypeDef UART_Base_Init(UART_SettingsTypeDef *suart)
{ // function takes setting structure for init
// check is settings are valid
if(Check_UART_Init_Struct(suart) != HAL_OK)
return HAL_ERROR;
suart->huart.Init.Mode = UART_MODE_TX_RX;
UART_MspInit(&suart->huart);
if (HAL_UART_Init(&suart->huart) != HAL_OK)
{
ERROR_HANDLER_NAME();
return HAL_ERROR;
}
// init gpio from UARTSettings structure
UART_GPIO_Init(suart->GPIOx, suart->GPIO_PIN_RX, suart->GPIO_PIN_TX);
// init dma from UARTSettings structure if need
if (suart->DMAChannel != 0)
UART_DMA_Init(&suart->huart, suart->huart.hdmarx, suart->DMAChannel, suart->DMA_CHANNEL_X);
return HAL_OK;
}
/**
* @brief Initialize GPIO for UART.
* @param GPIOx - порт для настройки.
* @param GPIO_PIN_RX - пин для настройки на прием.
* @param GPIO_PIN_TX - пин для настройки на передачу.
*/
void UART_GPIO_Init(GPIO_TypeDef *GPIOx, uint16_t GPIO_PIN_RX, uint16_t GPIO_PIN_TX)
{ // function takes port and pins (for rx and tx)
GPIO_InitTypeDef GPIO_InitStruct = {0};
// choose port for enable clock
GPIO_Clock_Enable(GPIOx);
//USART3 GPIO Configuration
//GPIO_PIN_TX ------> USART_TX
//GPIO_PIN_RX ------> USART_RX
#if defined(STM32F407xx) // gpio init for 407
GPIO_InitStruct.Pin = GPIO_PIN_TX|GPIO_PIN_RX;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
HAL_GPIO_Init(GPIOx, &GPIO_InitStruct);
#elif defined(STM32F103xG) // gpio init for atm403/stm103
//GPIO_PIN_TX ------> USART_TX
GPIO_InitStruct.Pin = GPIO_PIN_TX;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOx, &GPIO_InitStruct);
// GPIO_PIN_RX ------> USART_RX
GPIO_InitStruct.Pin = GPIO_PIN_RX;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOx, &GPIO_InitStruct);
#endif
}
/**
* @brief Initialize DMA for UART.
* @param huart - указатель на хендл UART для настройки DMA.
* @param hdma_rx - указатель на хендл DMA для линии приема UART.
* @param DMAChannel - указатель на канал DMA/поток DMA в STM32F407.
* @param DMA_CHANNEL_X - канал DMA.
*/
void UART_DMA_Init(UART_HandleTypeDef *huart, DMA_HandleTypeDef *hdma_rx, DMA_Stream_TypeDef *DMAChannel, uint32_t DMA_CHANNEL_X)
{ // function takes uart and dma handlers and dmachannel for uart
// for now only dma rx is supported, tx maybe later if needed
// calc defines on boot_project_setup.h
/* USART3 DMA Init */
/* USART3_RX Init */
hdma_rx->Instance = DMAChannel;
#if defined(STM32F407xx) // dma channel choose for 407
hdma_rx->Init.Channel = DMA_CHANNEL_X;
#endif
hdma_rx->Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_rx->Init.PeriphInc = DMA_PINC_DISABLE;
hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_rx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_rx->Init.Mode = DMA_CIRCULAR;
hdma_rx->Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(hdma_rx) != HAL_OK)
{
ERROR_HANDLER_NAME();
}
__USER_LINKDMA(huart,hdmarx,hdma_rx);
// __USER_LINKDMA is need because __HAL_LINKDMA is written for global defined hdma_rx
// so you get error because hal uses . insted of ->
}
/**
* @brief Initialize UART & DMA clock and interrupt.
* @param huart - указатель на хендл UART для инициализации.
* @note Чтобы не генерировать функцию с иницилизацией неиспользуемых UART,
дефайнами в rs_message.h определяются используемые UART.
*/
void UART_MspInit(UART_HandleTypeDef *huart) // analog for hal function
{
// __RCC_DMA_UART_CLK_ENABLE();
// /* DMA interrupt init */
// /* DMA1_Stream1_IRQn interrupt configuration */
// HAL_NVIC_SetPriority(DMA_UART_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA_UART_IRQn);
// rcc, dma and interrupt init for USARTs
// GPIO init was moved to own functions UART_GPIO_Init
if(0);
#ifdef USE_USART1
else if(huart->Instance==USART1)
{
/* DMA2 clock enable */
__HAL_RCC_DMA2_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
}
#endif // USE_USART1
#ifdef USE_USART2
else if(huart->Instance==USART2)
{
/* DMA1 clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
}
#endif // USE_USART2
#ifdef USE_USART3
else if(huart->Instance==USART3)
{
/* DMA1 clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
/* USART3 clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
/* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn);
}
#endif // USE_USART3
#ifdef USE_UART4
else if(huart->Instance==UART4)
{
/* DMA1 clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
/* UART4 clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
/* UART4 interrupt Init */
HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(UART4_IRQn);
}
#endif // USE_UART4
#ifdef USE_UART5
else if(huart->Instance==UART5)
{
/* DMA1 clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
/* UART5 clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* UART5 interrupt Init */
HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(UART5_IRQn);
}
#endif // USE_UART5
#ifdef USE_USART6
else if(huart->Instance==USART6)
{
/* DMA2 clock enable */
__HAL_RCC_DMA2_CLK_ENABLE();
/* DMA interrupt init */
HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
/* USART6 clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
/* USART6 interrupt Init */
HAL_NVIC_SetPriority(USART6_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART6_IRQn);
}
#endif // USE_USART6
}
/**
* @brief Deinitialize UART & DMA clock and interrupt.
* @param huart - указатель на хендл UART для деинициализации.
* @note Чтобы не генерировать функцию с деиницилизацией неиспользуемых UART,
дефайнами определяются используемые UART.
*/
void UART_MspDeInit(UART_HandleTypeDef *huart) // analog for hal function
{
// rcc, dma and interrupt init for USARTs
// GPIO init was moved to own functions UART_GPIO_Init
if(0);
#ifdef USE_USART1
else if(huart->Instance==USART1)
{
// /* DMA2 clock enable */
// __HAL_RCC_DMA2_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
/* USART1 clock reset */
__HAL_RCC_USART1_FORCE_RESET();
__HAL_RCC_USART1_RELEASE_RESET();
}
#endif // USE_USART1
#ifdef USE_USART2
else if(huart->Instance==USART2)
{
// /* DMA1 clock enable */
// __HAL_RCC_DMA1_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
/* USART2 clock reset */
__HAL_RCC_USART2_FORCE_RESET();
__HAL_RCC_USART2_RELEASE_RESET();
}
#endif // USE_USART2
#ifdef USE_USART3
else if(huart->Instance==USART3)
{
// /* DMA1 clock enable */
// __HAL_RCC_DMA1_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
/* USART3 clock reset */
__HAL_RCC_USART3_FORCE_RESET();
__HAL_RCC_USART3_RELEASE_RESET();
}
#endif // USE_USART3
#ifdef USE_UART4
else if(huart->Instance==UART4)
{
// /* DMA1 clock enable */
// __HAL_RCC_DMA1_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
/* UART4 clock reset */
__HAL_RCC_UART4_FORCE_RESET();
__HAL_RCC_UART4_RELEASE_RESET();
}
#endif // USE_UART4
#ifdef USE_UART5
else if(huart->Instance==UART5)
{
// /* DMA1 clock enable */
// __HAL_RCC_DMA1_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
/* UART5 clock reset */
__HAL_RCC_UART5_FORCE_RESET();
__HAL_RCC_UART5_RELEASE_RESET();
}
#endif // USE_UART5
#ifdef USE_USART6
else if(huart->Instance==USART6)
{
// /* DMA2 clock enable */
// __HAL_RCC_DMA2_CLK_ENABLE();
// /* DMA interrupt init */
// HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0, 0);
// HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
/* USART6 clock reset */
__HAL_RCC_USART6_FORCE_RESET();
__HAL_RCC_USART6_RELEASE_RESET();
}
#endif // USE_USART6
}
/**
* @brief Check that uart init structure have correct values.
* @param suart - указатель на структуру с настройками UART.
* @return HAL status.
*/
HAL_StatusTypeDef Check_UART_Init_Struct(UART_SettingsTypeDef *suart)
{
// check is settings are valid
if (!IS_UART_INSTANCE(suart->huart.Instance))
return HAL_ERROR;
if (!IS_UART_BAUDRATE(suart->huart.Init.BaudRate) || (suart->huart.Init.BaudRate == NULL))
return HAL_ERROR;
if (!IS_GPIO_ALL_INSTANCE(suart->GPIOx))
return HAL_ERROR;
if (!IS_GPIO_PIN(suart->GPIO_PIN_RX) && !IS_GPIO_PIN(suart->GPIO_PIN_TX)) // if both pins arent set up
return HAL_ERROR;
return HAL_OK;
}
//------------------------UART INIT FUNCTIONS------------------------
//-------------------------------------------------------------------

106
Code/GENERAL/uart_general.h
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@@ -1,106 +0,0 @@
/*********************************UART**************************************
Данный файл содержит объявления базовых функции и дефайны для инициализации
UART.
***************************************************************************/
#ifndef __UART_GENERAL_H_
#define __UART_GENERAL_H_
//////////////////////////////////////////////////////////////////////
/////////////////////////---USER SETTINGS---/////////////////////////
#define HAL_UART_MODULE_ENABLED // need to uncomment these defines in stm32f4xx_hal_conf.h
#define HAL_USART_MODULE_ENABLED // also need to add hal_uart.c (source code)
//#define USE_USART1
//#define USE_USART2
//#define USE_USART3
//#define USE_UART4
//#define USE_UART5
//#define USE_USART6
/* note: used uart defines in modbus.h */
/////////////////////////---USER SETTINGS---/////////////////////////
#include "periph_general.h"
/////////////////////////////////////////////////////////////////////
////////////////////////////---DEFINES---////////////////////////////
/**
* @brief Analog for HAL define. Remade with pointer to structure.
* @note @ref __HAL_LINKDMA.
*/
#define __USER_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = (__DMA_HANDLE__); \
(__DMA_HANDLE__)->Parent = (__HANDLE__);} while(0U)
////////////////////////////---DEFINES---////////////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////---STRUCTURES & ENUMS---//////////////////////
typedef struct // struct with settings for custom function
{
UART_HandleTypeDef huart;
GPIO_TypeDef *GPIOx;
uint16_t GPIO_PIN_RX;
uint16_t GPIO_PIN_TX;
DMA_Stream_TypeDef *DMAChannel; // DMAChannel = 0 if doesnt need
uint32_t DMA_CHANNEL_X; // DMAChannel = 0 if doesnt need
}UART_SettingsTypeDef;
///////////////////////---STRUCTURES & ENUMS---//////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////////---FUNCTIONS---///////////////////////////
/**
* @brief Initialize UART with UART_SettingsTypeDef structure.
* @param suart - указатель на структуру с настройками UART.
* @return HAL status.
* @note Данная структура содержит хендл ЮАРТ и настройки перефирии (GPIO)
*/
HAL_StatusTypeDef UART_Base_Init(UART_SettingsTypeDef *suart);
/**
* @brief Initialize GPIO for UART.
* @param GPIOx - порт для настройки.
* @param GPIO_PIN_RX - пин для настройки на прием.
* @param GPIO_PIN_TX - пин для настройки на передачу.
*/
void UART_GPIO_Init(GPIO_TypeDef *GPIOx, uint16_t GPIO_PIN_RX, uint16_t GPIO_PIN_TX);
/**
* @brief Initialize DMA for UART.
* @param huart - указатель на хендл UART для настройки DMA.
* @param hdma_rx - указатель на хендл DMA для линии приема UART.
* @param DMAChannel - указатель на канал DMA/поток DMA в STM32F407.
* @param DMA_CHANNEL_X - канал DMA.
*/
void UART_DMA_Init(UART_HandleTypeDef *huart, DMA_HandleTypeDef *hdma_rx, DMA_Stream_TypeDef *DMAChannel, uint32_t DMA_CHANNEL_X);
/**
* @brief Initialize UART & DMA clock and interrupt.
* @param huart - указатель на хендл UART для инициализации.
* @note Чтобы не генерировать функцию с иницилизацией неиспользуемых UART,
дефайнами определяются используемые UART.
*/
void UART_MspInit(UART_HandleTypeDef *huart);
/**
* @brief Deinitialize UART & DMA clock and interrupt.
* @param huart - указатель на хендл UART для деинициализации.
* @note Чтобы не генерировать функцию с деиницилизацией неиспользуемых UART,
дефайнами в rs_message.h определяются используемые UART.
*/
void UART_MspDeInit(UART_HandleTypeDef *huart);
/**
* @brief Check that uart init structure have correct values.
* @param suart - указатель на структуру с настройками UART.
* @return HAL status.
*/
HAL_StatusTypeDef Check_UART_Init_Struct(UART_SettingsTypeDef *suart);
///////////////////////////---FUNCTIONS---///////////////////////////
#endif // __UART_GENERAL_H_

116
Code/Modbus/crc_algs.c
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@@ -1,116 +0,0 @@
#include "crc_algs.h"
uint32_t CRC_calc;
uint32_t CRC_ref;
//uint16_t CRC_calc;
//uint16_t CRC_ref;
// left this global for debug
uint8_t uchCRCHi = 0xFF;
uint8_t uchCRCLo = 0xFF;
unsigned uIndex;
uint32_t crc32(uint8_t *data, uint32_t data_size)
{
static const unsigned int crc32_table[] =
{
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
};
unsigned int crc = 0xFFFFFFFF;
while (data_size--)
{
crc = (crc >> 8) ^ crc32_table[(crc ^ *data) & 255];
data++;
}
return crc^0xFFFFFFFF;
}
uint16_t crc16(uint8_t *data, uint32_t data_size)
{
/*Table of CRC values for high order byte*/
static unsigned char auchCRCHi[]=
{
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,
0x00,0xC1,0x81,0x40,0x01,0xC0,0x80,0x41,0x01,0xC0,0x80,0x41,0x00,0xC1,0x81,0x40,
};
/*Table of CRC values for low order byte*/
static char auchCRCLo[] =
{
0x00,0xC0,0xC1,0x01,0xC3,0x03,0x02,0xC2,0xC6,0x06,0x07,0xC7,0x05,0xC5,0xC4,0x04,
0xCC,0x0C,0x0D,0xCD,0x0F,0xCF,0xCE,0x0E,0x0A,0xCA,0xCB,0x0B,0xC9,0x09,0x08,0xC8,
0xD8,0x18,0x19,0xD9,0x1B,0xDB,0xDA,0x1A,0x1E,0xDE,0xDF,0x1F,0xDD,0x1D,0x1C,0xDC,
0x14,0xD4,0xD5,0x15,0xD7,0x17,0x16,0xD6,0xD2,0x12,0x13,0xD3,0x11,0xD1,0xD0,0x10,
0xF0,0x30,0x31,0xF1,0x33,0xF3,0xF2,0x32,0x36,0xF6,0xF7,0x37,0xF5,0x35,0x34,0xF4,
0x3C,0xFC,0xFD,0x3D,0xFF,0x3F,0x3E,0xFE,0xFA,0x3A,0x3B,0xFB,0x39,0xF9,0xF8,0x38,
0x28,0xE8,0xE9,0x29,0xEB,0x2B,0x2A,0xEA,0xEE,0x2E,0x2F,0xEF,0x2D,0xED,0xEC,0x2C,
0xE4,0x24,0x25,0xE5,0x27,0xE7,0xE6,0x26,0x22,0xE2,0xE3,0x23,0xE1,0x21,0x20,0xE0,
0xA0,0x60,0x61,0xA1,0x63,0xA3,0xA2,0x62,0x66,0xA6,0xA7,0x67,0xA5,0x65,0x64,0xA4,
0x6C,0xAC,0xAD,0x6D,0xAF,0x6F,0x6E,0xAE,0xAA,0x6A,0x6B,0xAB,0x69,0xA9,0xA8,0x68,
0x78,0xB8,0xB9,0x79,0xBB,0x7B,0x7A,0xBA,0xBE,0x7E,0x7F,0xBF,0x7D,0xBD,0xBC,0x7C,
0xB4,0x74,0x75,0xB5,0x77,0xB7,0xB6,0x76,0x72,0xB2,0xB3,0x73,0xB1,0x71,0x70,0xB0,
0x50,0x90,0x91,0x51,0x93,0x53,0x52,0x92,0x96,0x56,0x57,0x97,0x55,0x95,0x94,0x54,
0x9C,0x5C,0x5D,0x9D,0x5F,0x9F,0x9E,0x5E,0x5A,0x9A,0x9B,0x5B,0x99,0x59,0x58,0x98,
0x88,0x48,0x49,0x89,0x4B,0x8B,0x8A,0x4A,0x4E,0x8E,0x8F,0x4F,0x8D,0x4D,0x4C,0x8C,
0x44,0x84,0x85,0x45,0x87,0x47,0x46,0x86,0x82,0x42,0x43,0x83,0x41,0x81,0x80,0x40,
};
uchCRCHi = 0xFF;
uchCRCLo = 0xFF;
/* CRC Generation Function */
while( data_size--) /* pass through message buffer */
{
uIndex = uchCRCHi ^ *data++; /* calculate the CRC */
uchCRCHi = uchCRCLo ^ auchCRCHi[uIndex];
uchCRCLo = auchCRCLo[uIndex];
}
return uchCRCHi | uchCRCLo<<8;
}

9
Code/Modbus/crc_algs.h
View File

@@ -1,9 +0,0 @@
#include "main.h"
// extern here to use in bootloader.c
extern uint32_t CRC_calc;
extern uint32_t CRC_ref;
uint16_t crc16(uint8_t *data, uint32_t data_size);
uint32_t crc32(uint8_t *data, uint32_t data_size);

864
Code/Modbus/modbus.c
View File

@@ -1,864 +0,0 @@
/********************************MODBUS*************************************
Данный файл содержит базовые функции для реализации MODBUS.
//-------------------Функции-------------------//
@func user
- MB_SetCoil
- MB_ResetCoil
@func process message
- MB_DefineRegistersAddress Определение "начального" адреса регистров
- MB_DefineCoilsAddress Определение "начального" адреса коилов
- MB_Check_Address_For_Arr принадлежит ли адресс Addr конкретному массиву
- Modbus_Command_x Обработка команды x
@func RS functions
- Parse_Message/Collect_Message Заполнение структуры сообщения и буфера
- RS_Response Ответ на комманду
- RS_Define_Size_of_RX_Message Определение размера принимаемых данных
- RS_Init Инициализация периферии и modbus handler
@func initialization
- MB_Init Инициализация modbus
//--------------Данные для модбас--------------//
@registers Holding/Input Registers
Регистры представляют собой 16-битные числа (слова). В обработке комманд
находится адресс "начального" регистра и записывается в указатель. Доступ к
остальным регистрам осуществляется через указатель. Таким образом, сами
регистры могут представлять собой как массив так и структуру.
- sine_log - массив регистров на 500 элементов
- sine_log - массив регистров на 500 элементов
@coils Coils
Коилы представляют собой биты, упакованные в 16-битные регистры. В обработке
комманд находится адресс "начального" регистра запрашиваемого коила. Доступ к
остальным коилам осуществляется через маску и указатель. Таким образом, сами
коилы могут представлять собой как массив так и структуру.
@example SLAVE RECEIVE
//--------------Настройка модбас--------------//
// create handles and settings
Create_MODBUS_Handles(modbus1);
// set up UART for modbus
modbus1_suart.huart = &modbus1_huart;
modbus1_suart.huart->Instance = USED_MODBUS_UART;
modbus1_suart.huart->Init.BaudRate = 38400;
modbus1_suart.GPIOx = MODBUS_GPIOX;
modbus1_suart.GPIO_PIN_RX = MODBUS_GPIO_PIN_RX;
modbus1_suart.GPIO_PIN_TX = MODBUS_GPIO_PIN_TX;
// set up timeout TIM for modbus
modbus1_stim.htim = &modbus1_htim;
modbus1_stim.htim.Instance = USED_MODBUS_TIM;
modbus1_stim.htim.Init.Prescaler = 36000; // set this to 0.5 ms
modbus1_stim.TIM_MODE = TIM_IT_CONF;
// set up modbus: MB_RX_Size_NotConst and Timeout enable
hmodbus1.ID = 1;
hmodbus1.sRS_RX_Size_Mode = RS_RX_Size_NotConst;
hmodbus1.sRS_Timeout = 100;
hmodbus1.sRS_Mode = SLAVE_ALWAYS_WAIT;
hmodbus1.RS_STATUS = RS_Init(&hmodbus1, &modbus1_suart, &modbus1_stim, 0);
//----------------Прием модбас----------------//
RS_MsgTypeDef MODBUS_MSG;
RS_Receive_IT(&hmodbus1, &MODBUS_MSG);
***************************************************************************/
#include "rs_message.h"
uint32_t dbg_temp, dbg_temp2, dbg_temp3; // for debug
uint32_t err_cnt = 0;
/* EXTERN MODBUS HANDLES */
extern UART_SettingsTypeDef modbus1_suart;
extern TIM_SettingsTypeDef modbus1_stim;
extern RS_HandleTypeDef hmodbus1;
/* DEFINE REGISTERS/COILS */
uint16_t sine_log[R_SINE_LOG_QNT]; // start from 0x0000
uint16_t pwm_log[R_PWM_LOG_QNT]; // start from 500 (0x1F4)
uint16_t cnt_log[R_CNT_LOG_QNT]; // start from 100 (0x3E8)
uint16_t time_log[R_TIME_LOG_QNT]; // start from 1500 (0x5DC)
uint16_t pwm_ctrl[R_PWM_CTRL_QNT]; // start from 2000 (0x7D0)
uint16_t log_ctrl[R_PWM_CTRL_QNT]; // start from 2008 (0x7D0)
uint16_t uart_ctrl[R_UART_CTRL_QNT];
uint16_t coils_regs[C_CTRL_COILS_QNT];
//-------------------------------------------------------------------
//-----------------------------FOR USER------------------------------
/**
* @brief First set up of MODBUS.
* @note Первый инит модбас. Заполняет структуры и инициализирует таймер и юарт для общения по модбас.
* Скважность ШИМ меняется по закону синусоиды, каждый канал генерирует свой полупериод синуса (от -1 до 0 И от 0 до 1)
* ШИМ генерируется на одном канале.
* @note This called from main
*/
void MODBUS_FirstInit(void)
{
//-----------SETUP MODBUS-------------
// set up UART for modbus
modbus1_suart.huart.Instance = USED_MODBUS_UART;
modbus1_suart.huart.Init.BaudRate = PROJSET.MB_SPEED;
modbus1_suart.GPIOx = (GPIO_TypeDef *)PROJSET.MB_GPIOX;
modbus1_suart.GPIO_PIN_RX = PROJSET.MB_GPIO_PIN_RX;
modbus1_suart.GPIO_PIN_TX = PROJSET.MB_GPIO_PIN_TX;
// set up timeout TIM for modbus
modbus1_stim.htim.Instance = USED_MODBUS_TIM;
modbus1_stim.sTimAHBFreqMHz = PROJSET.MB_TIM_AHB_FREQ;
modbus1_stim.sTimMode = TIM_IT_CONF;
// set up modbus: MB_RX_Size_NotConst and Timeout enable
hmodbus1.ID = PROJSET.MB_DEVICE_ID;
hmodbus1.sRS_Timeout = PROJSET.MB_MAX_TIMEOUT;
hmodbus1.sRS_Mode = SLAVE_ALWAYS_WAIT;
hmodbus1.sRS_RX_Size_Mode = RS_RX_Size_NotConst;
// INIT
hmodbus1.RS_STATUS = RS_Init(&hmodbus1, &modbus1_suart, &modbus1_stim, 0);
}
/**
* @brief Set or Reset Coil at its global address.
* @param Addr - адрес коила.
* @param WriteVal - Что записать в коил: 0 или 1.
* @return ExceptionCode - Код исключения если коила по адресу не существует, и NO_ERRORS если все ок.
*
* @note Позволяет обратиться к любому коилу по его глобальному адрессу.
Вне зависимости от того как коилы размещены в памяти.
*/
MB_ExceptionTypeDef MB_Write_Coil_Global(uint16_t Addr, MB_CoilsOpTypeDef WriteVal)
{
//---------CHECK FOR ERRORS----------
MB_ExceptionTypeDef Exception = NO_ERRORS;
uint16_t *coils;
uint16_t start_shift = 0; // shift in coils register
//------------WRITE COIL-------------
Exception = MB_DefineCoilsAddress(&coils, Addr, 1, &start_shift, 1);
if(Exception == NO_ERRORS)
{
switch(WriteVal)
{
case SET_COIL:
*coils |= (1<<start_shift);
break;
case RESET_COIL:
*coils &= ~(1<<start_shift);
break;
case TOOGLE_COIL:
*coils ^= (1<<start_shift);
break;
}
}
return Exception;
}
/**
* @brief Read Coil at its global address.
* @param Addr - адрес коила.
* @param Exception - Указатель на переменную для кода исключения, в случа неудачи при чтении.
* @return uint16_t - Возвращает весь регистр с маской на запрошенном коиле.
*
* @note Позволяет обратиться к любому коилу по его глобальному адрессу.
Вне зависимости от того как коилы размещены в памяти.
*/
uint16_t MB_Read_Coil_Global(uint16_t Addr, MB_ExceptionTypeDef *Exception)
{
//---------CHECK FOR ERRORS----------
MB_ExceptionTypeDef Exception_tmp;
if(Exception == NULL) // if exception is not given to func fill it
Exception = &Exception_tmp;
uint16_t *coils;
uint16_t start_shift = 0; // shift in coils register
//------------READ COIL--------------
*Exception = MB_DefineCoilsAddress(&coils, Addr, 1, &start_shift, 0);
if(*Exception == NO_ERRORS)
{
return ((*coils)&(1<<start_shift));
}
else
{
return 0;
}
}
//-------------------------------------------------------------------
//----------------FUNCTIONS FOR PROCESSING MESSAGE-------------------
/**
* @brief Define Address Origin for Input/Holding Registers
* @param pRegs - указатель на указатель регистров.
* @param Addr - адрес начального регистра.
* @param Qnt - количество запрашиваемых регистров.
* @param WriteFlag - флаг регистр нужны для чтения или записи.
* @return ExceptionCode - Код исключения если есть, и NO_ERRORS если нет.
*
* @note Определение адреса начального регистра.
* @note WriteFlag пока не используется.
*/
MB_ExceptionTypeDef MB_DefineRegistersAddress(uint16_t **pRegs, uint16_t Addr, uint16_t Qnt, uint8_t WriteFlag)
{
/* check quantity error */
if (Qnt > 125)
{
return ILLEGAL_DATA_VALUE; // return exception code
}
// sensors array
if(MB_Check_Address_For_Arr(Addr, Qnt, R_SINE_LOG_ADDR, R_SINE_LOG_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&sine_log, Addr); // начало регистров хранения/входных
}
// PWM array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_PWM_LOG_ADDR, R_PWM_LOG_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&pwm_log, Addr - R_PWM_LOG_ADDR); // начало регистров хранения/входных
}
// counter array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_CNT_LOG_ADDR, R_CNT_LOG_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&cnt_log, Addr - R_CNT_LOG_ADDR); // начало регистров хранения/входных
}
// time array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_TIME_LOG_ADDR, R_TIME_LOG_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&time_log, Addr - R_TIME_LOG_ADDR); // начало регистров хранения/входных
}
// PWM array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_PWM_CTRL_ADDR, R_PWM_CTRL_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&pwm_ctrl, Addr - R_PWM_CTRL_ADDR); // начало регистров хранения/входных
}
// log array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_LOG_CTRL_ADDR, R_LOG_CTRL_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&log_ctrl, Addr - R_LOG_CTRL_ADDR); // начало регистров хранения/входных
}
// uart settings array
else if(MB_Check_Address_For_Arr(Addr, Qnt, R_UART_CTRL_ADDR, R_UART_CTRL_QNT) == NO_ERRORS)
{
*pRegs = MB_Set_Register_Ptr(&uart_ctrl, Addr - R_UART_CTRL_ADDR); // начало регистров хранения/входных
}
// if address doesnt match any array - return illegal data address response
else
{
return ILLEGAL_DATA_ADDRESS;
}
// if found requeried array return no err
return NO_ERRORS; // return no errors
}
/**
* @brief Define Address Origin for coils
* @param pCoils - указатель на указатель коилов.
* @param Addr - адресс начального коила.
* @param Qnt - количество запрашиваемых коилов.
* @param start_shift - указатель на переменную содержащую сдвиг внутри регистра для начального коила.
* @param WriteFlag - флаг коилы нужны для чтения или записи.
* @return ExceptionCode - Код исключения если есть, и NO_ERRORS если нет.
*
* @note Определение адреса начального регистра запрашиваемых коилов.
* @note WriteFlag используется для определния регистров GPIO: ODR или IDR.
*/
MB_ExceptionTypeDef MB_DefineCoilsAddress(uint16_t **pCoils, uint16_t Addr, uint16_t Qnt, uint16_t *start_shift, uint8_t WriteFlag)
{
/* check quantity error */
if (Qnt > 2000)
{
return ILLEGAL_DATA_VALUE; // return exception code
}
// gpiod coils
if(MB_Check_Address_For_Arr(Addr, Qnt, C_GPIOD_ADDR, C_GPIOD_QNT) == NO_ERRORS)
{
if(WriteFlag) // if write set odr
*pCoils = MB_Set_Coil_Reg_Ptr(&GPIOD->ODR, Addr);
else // if read set idr
*pCoils = MB_Set_Coil_Reg_Ptr(&GPIOD->IDR, Addr);
}
// peripheral control coils
else if(MB_Check_Address_For_Arr(Addr, Qnt, C_CTRL_COILS_ADDR, C_CTRL_COILS_QNT) == NO_ERRORS)
{
*pCoils = MB_Set_Coil_Reg_Ptr(&coils_regs, Addr-C_CTRL_COILS_ADDR);
}
// if address doesnt match any array - return illegal data address response
else
{
return ILLEGAL_DATA_ADDRESS;
}
*start_shift = Addr % 16; // set shift to requested coil
// if found requeried array return no err
return NO_ERRORS; // return no errors
}
/**
* @brief Check is address valid for certain array.
* @param Addr - начальный адресс.
* @param Qnt - количество запрашиваемых элементов.
* @param R_ARR_ADDR - начальный адресс массива R_ARR.
* @param R_ARR_NUMB - количество элементов в массиве R_ARR.
* @return ExceptionCode - ILLEGAL DATA ADRESS если адресс недействителен, и NO_ERRORS если все ок.
*
* @note Позволяет определить, принадлежит ли адресс Addr массиву R_ARR:
* Если адресс Addr находится в диапазоне адрессов массива R_ARR, то возвращаем NO_ERROR.
* Если адресс Addr находится за пределами адрессов массива R_ARR - ILLEGAL_DATA_ADDRESSю.
*/
MB_ExceptionTypeDef MB_Check_Address_For_Arr(uint16_t Addr, uint16_t Qnt, uint16_t R_ARR_ADDR, uint16_t R_ARR_NUMB)
{
// if address from this array
if(Addr >= R_ARR_ADDR)
{
// if quantity too big return error
if ((Addr - R_ARR_ADDR) + Qnt > R_ARR_NUMB)
{
return ILLEGAL_DATA_ADDRESS; // return exception code
}
// if all ok - return no errors
return NO_ERRORS;
}
// if address isnt from this array return error
else
return ILLEGAL_DATA_ADDRESS; // return exception code
}
/**
* @brief Proccess command Read Coils (01 - 0x01).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Read Coils.
*/
uint8_t MB_Read_Coils(RS_MsgTypeDef *modbus_msg)
{
//---------CHECK FOR ERRORS----------
uint16_t *coils;
uint16_t start_shift = 0; // shift in coils register
modbus_msg->Except_Code = MB_DefineCoilsAddress(&coils, modbus_msg->Addr, modbus_msg->Qnt, &start_shift, 0);
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//-----------READING COIL------------
// setup output message data size
modbus_msg->ByteCnt = Divide_Up(modbus_msg->Qnt, 8);
// create mask for coils
uint16_t mask_for_coils = 0; // mask for coils that've been chosen
uint16_t setted_coils = 0; // value of setted coils
uint16_t temp_reg = 0; // temp register for saving coils that hasnt been chosen
uint16_t coil_cnt = 0; // counter for processed coils
// cycle until all registers with requered coils would be processed
int shift = start_shift; // set shift to first coil in first register
int ind = 0; // index for coils registers and data
for(; ind <= Divide_Up(start_shift + modbus_msg->Qnt, 16); ind++)
{
//----SET MASK FOR COILS REGISTER----
mask_for_coils = 0;
for(; shift < 0x10; shift++)
{
mask_for_coils |= 1<<(shift); // choose certain coil
if(++coil_cnt >= modbus_msg->Qnt)
break;
}
shift = 0; // set shift to zero for the next step
//-----------READ COILS--------------
modbus_msg->DATA[ind] = (*(coils+ind)&mask_for_coils) >> start_shift;
if(ind > 0)
modbus_msg->DATA[ind-1] |= ((*(coils+ind)&mask_for_coils) << 16) >> start_shift;
}
// т.к. DATA 16-битная, для 8-битной передачи, надо поменять местами верхний и нижний байты
for(; ind >= 0; --ind)
modbus_msg->DATA[ind] = ByteSwap16(modbus_msg->DATA[ind]);
return 1;
}
/**
* @brief Proccess command Read Holding Registers (03 - 0x03).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Read Holding Registers.
*/
uint8_t MB_Read_Hold_Regs(RS_MsgTypeDef *modbus_msg)
{
//---------CHECK FOR ERRORS----------
// get origin address for data
uint16_t *pHoldRegs;
modbus_msg->Except_Code = MB_DefineRegistersAddress(&pHoldRegs, modbus_msg->Addr, modbus_msg->Qnt, NULL); // определение адреса регистров
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//-----------READING REGS------------
// setup output message data size
modbus_msg->ByteCnt = modbus_msg->Qnt*2; // *2 because we transmit 8 bits, not 16 bits
// read data
int i;
for (i = 0; i<modbus_msg->Qnt; i++)
{
modbus_msg->DATA[i] = *(pHoldRegs++);
}
return 1;
}
/**
* @brief Proccess command Write Single Coils (05 - 0x05).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Single Coils.
*/
uint8_t MB_Write_Single_Coil(RS_MsgTypeDef *modbus_msg)
{
//---------CHECK FOR ERRORS----------
if ((modbus_msg->Qnt != 0x0000) && (modbus_msg->Qnt != 0xFF00))
{
modbus_msg->Except_Code = ILLEGAL_DATA_VALUE;
return 0;
}
// define position of coil
uint16_t *coils;
uint16_t start_shift = 0; // shift in coils register
modbus_msg->Except_Code = MB_DefineCoilsAddress(&coils, modbus_msg->Addr, 0, &start_shift, 1);
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//----------WRITTING COIL------------
if(modbus_msg->Qnt == 0xFF00)
*(coils) |= 1<<start_shift; // write flags corresponding to received data
else
*(coils) &= ~(1<<start_shift); // write flags corresponding to received data
return 1;
}
/**
* @brief Proccess command Write Single Register (06 - 0x06).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Single Register.
*/
uint8_t MB_Write_Single_Reg(RS_MsgTypeDef *modbus_msg)
{
// get origin address for data
uint16_t *pInputRegs;
modbus_msg->Except_Code = MB_DefineRegistersAddress(&pInputRegs, modbus_msg->Addr, 1, NULL); // определение адреса регистров
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//-----------WRITTING REG------------
*(pInputRegs) = modbus_msg->Qnt;
return 1;
}
/**
* @brief Proccess command Write Multiple Coils (15 - 0x0F).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Multiple Coils.
*/
uint8_t MB_Write_Miltuple_Coils(RS_MsgTypeDef *modbus_msg)
{
//---------CHECK FOR ERRORS----------
if (modbus_msg->ByteCnt != Divide_Up(modbus_msg->Qnt, 8))
{ // if quantity too large OR if quantity and bytes count arent match
modbus_msg->Except_Code = ILLEGAL_DATA_VALUE;
return 0;
}
// define position of coil
uint16_t *coils; // pointer to coils
uint16_t start_shift = 0; // shift in coils register
modbus_msg->Except_Code = MB_DefineCoilsAddress(&coils, modbus_msg->Addr, modbus_msg->Qnt, &start_shift, 1);
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//----------WRITTING COILS-----------
// create mask for coils
uint16_t mask_for_coils = 0; // mask for coils that've been chosen
uint32_t setted_coils = 0; // value of setted coils
uint16_t temp_reg = 0; // temp register for saving coils that hasnt been chosen
uint16_t coil_cnt = 0; // counter for processed coils
// cycle until all registers with requered coils would be processed
int shift = start_shift; // set shift to first coil in first register
for(int ind = 0; ind <= Divide_Up(start_shift + modbus_msg->Qnt, 16); ind++)
{
//----SET MASK FOR COILS REGISTER----
mask_for_coils = 0;
for(; shift < 0x10; shift++)
{
mask_for_coils |= 1<<(shift); // choose certain coil
if(++coil_cnt >= modbus_msg->Qnt)
break;
}
shift = 0; // set shift to zero for the next step
//-----------WRITE COILS-------------
// get current coils
temp_reg = *(coils+ind);
// set coils
setted_coils = ByteSwap16(modbus_msg->DATA[ind]) << start_shift;
if(ind > 0)
{
setted_coils |= ((ByteSwap16(modbus_msg->DATA[ind-1]) << start_shift) >> 16);
}
// write coils
*(coils+ind) = setted_coils & mask_for_coils;
// restore untouched coils
*(coils+ind) |= temp_reg&(~mask_for_coils);
if(coil_cnt >= modbus_msg->Qnt) // if all coils written - break cycle
break; // *kind of unnecessary
}
return 1;
}
/**
* @brief Proccess command Write Multiple Registers (16 - 0x10).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Multiple Registers.
*/
uint8_t MB_Write_Miltuple_Regs(RS_MsgTypeDef *modbus_msg)
{
//---------CHECK FOR ERRORS----------
if (modbus_msg->Qnt*2 != modbus_msg->ByteCnt)
{ // if quantity and bytes count arent match
modbus_msg->Except_Code = 3;
return 0;
}
// get origin address for data
uint16_t *pInputRegs;
modbus_msg->Except_Code = MB_DefineRegistersAddress(&pInputRegs, modbus_msg->Addr, modbus_msg->Qnt, NULL); // определение адреса регистров
if(modbus_msg->Except_Code != NO_ERRORS)
return 0;
//-----------WRITTING REGS-----------
for (int i = 0; i<modbus_msg->Qnt; i++)
{
*(pInputRegs++) = modbus_msg->DATA[i];
}
return 1;
}
/**
* @brief Respond accord to received message.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о результате ответа на комманду.
* @note Обработка принятой комманды и ответ на неё.
*/
RS_StatusTypeDef RS_Response(RS_HandleTypeDef *hmodbus, RS_MsgTypeDef *modbus_msg)
{
RS_StatusTypeDef MB_RES = 0;
hmodbus->fMessageHandled = 0;
hmodbus->fEchoResponse = 0;
RS_Reset_TX_Flags(hmodbus); // reset flag for correct transmit
if(modbus_msg->Func_Code < ERR_VALUES_START)// if no errors after parsing
{
switch (modbus_msg->Func_Code)
{
// Read Coils
case MB_R_COILS:
hmodbus->fMessageHandled = MB_Read_Coils(hmodbus->pMessagePtr);
break;
// case MB_R_DISC_IN: break;
// Read Hodling Registers
case MB_R_HOLD_REGS:
case MB_R_IN_REGS:
hmodbus->fMessageHandled = MB_Read_Hold_Regs(hmodbus->pMessagePtr);
break;
// Write Single Coils
case MB_W_COIL:
hmodbus->fMessageHandled = MB_Write_Single_Coil(hmodbus->pMessagePtr);
if(hmodbus->fMessageHandled) hmodbus->fEchoResponse = 1; // echo response if write ok
break;
case MB_W_IN_REG:
hmodbus->fMessageHandled = MB_Write_Single_Reg(hmodbus->pMessagePtr);
if(hmodbus->fMessageHandled) hmodbus->fEchoResponse = 1; // echo response if write ok
break;
// Write Multiple Coils
case MB_W_COILS:
hmodbus->fMessageHandled = MB_Write_Miltuple_Coils(hmodbus->pMessagePtr);
if(hmodbus->fMessageHandled) hmodbus->fEchoResponse = 1; hmodbus->RS_Message_Size = 6; // echo response if write ok (withous data bytes)
break;
// Write Multiple Registers
case MB_W_IN_REGS:
hmodbus->fMessageHandled = MB_Write_Miltuple_Regs(hmodbus->pMessagePtr);
if(hmodbus->fMessageHandled) hmodbus->fEchoResponse = 1; hmodbus->RS_Message_Size = 6; // echo response if write ok (withous data bytes)
break;
/* unknown func code */
default: modbus_msg->Except_Code = 0x01; /* set exception code: illegal function */
}
if(hmodbus->fMessageHandled == 0)
modbus_msg->Func_Code += ERR_VALUES_START;
}
// if we need response - check that transmit isnt busy
if( RS_Is_TX_Busy(hmodbus) )
RS_Abort(hmodbus, ABORT_TX); // if tx busy - set it free
// Transmit right there, or sets (fDeferredResponse) to transmit response in main code
MB_RES = RS_Handle_Transmit_Start(hmodbus, modbus_msg);
hmodbus->RS_STATUS = MB_RES;
return MB_RES;
}
/**
* @brief Collect message in buffer to transmit it.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @param msg_uart_buff - указатель на буффер UART.
* @return RS_RES - статус о результате заполнения буфера.
* @note Заполнение буффера UART из структуры сообщения.
*/
RS_StatusTypeDef Collect_Message(RS_HandleTypeDef *hmodbus, RS_MsgTypeDef *modbus_msg, uint8_t *modbus_uart_buff)
{
int ind = 0; // ind for modbus-uart buffer
if(hmodbus->fEchoResponse && hmodbus->fMessageHandled) // if echo response need
ind = hmodbus->RS_Message_Size;
else
{
//------INFO ABOUT DATA/MESSAGE------
//-----------[first bytes]-----------
// set ID of message/user
modbus_uart_buff[ind++] = modbus_msg->MbAddr;
// set dat or err response
modbus_uart_buff[ind++] = modbus_msg->Func_Code;
if (modbus_msg->Func_Code < ERR_VALUES_START) // if no error occur
{
// set size of received data
if (modbus_msg->ByteCnt <= DATA_SIZE*2) // if ByteCnt less than DATA_SIZE
modbus_uart_buff[ind++] = modbus_msg->ByteCnt;
else // otherwise return data_size err
return RS_COLLECT_MSG_ERR;
//---------------DATA----------------
//-----------[data bytes]------------
uint16_t *tmp_data_addr = (uint16_t *)modbus_msg->DATA;
for(int i = 0; i < modbus_msg->ByteCnt; i++) // filling buffer with data
{ // set data
if (i%2 == 0) // HI byte
modbus_uart_buff[ind++] = (*tmp_data_addr)>>8;
else // LO byte
{
modbus_uart_buff[ind++] = *tmp_data_addr;
tmp_data_addr++;
}
}
}
else // if some error occur
{ // send expection code
modbus_uart_buff[ind++] = modbus_msg->Except_Code;
}
}
//---------------CRC----------------
//---------[last 16 bytes]----------
// calc crc of received data
uint16_t CRC_VALUE = crc16(modbus_uart_buff, ind);
// write crc to message structure and modbus-uart buffer
modbus_msg->MB_CRC = CRC_VALUE;
modbus_uart_buff[ind++] = CRC_VALUE;
modbus_uart_buff[ind++] = CRC_VALUE >> 8;
hmodbus->RS_Message_Size = ind;
return RS_OK; // returns ok
}
/**
* @brief Parse message from buffer to process it.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @param msg_uart_buff - указатель на буффер UART.
* @return RS_RES - статус о результате заполнения структуры.
* @note Заполнение структуры сообщения из буффера UART.
*/
RS_StatusTypeDef Parse_Message(RS_HandleTypeDef *hmodbus, RS_MsgTypeDef *modbus_msg, uint8_t *modbus_uart_buff)
{
uint32_t check_empty_buff;
int ind = 0; // ind for modbus-uart buffer
//-----INFO ABOUT DATA/MESSAGE-------
//-----------[first bits]------------
// get ID of message/user
modbus_msg->MbAddr = modbus_uart_buff[ind++];
if(modbus_msg->MbAddr != hmodbus->ID)
return RS_SKIP;
// get dat or err response
modbus_msg->Func_Code = modbus_uart_buff[ind++];
// get address from CMD
modbus_msg->Addr = modbus_uart_buff[ind++] << 8;
modbus_msg->Addr |= modbus_uart_buff[ind++];
// get address from CMD
modbus_msg->Qnt = modbus_uart_buff[ind++] << 8;
modbus_msg->Qnt |= modbus_uart_buff[ind++];
if(hmodbus->fRX_Half == 0) // if all message received
{
//---------------DATA----------------
// (optional)
if (modbus_msg->ByteCnt != 0)
{
ind++; // increment ind for data_size byte
//check that data size is correct
if (modbus_msg->ByteCnt > DATA_SIZE)
{
// hmodbus->MB_RESPONSE = MB_DATA_SIZE_ERR; // set func code - error data size more than maximumif yes, set func code - error about empty message
modbus_msg->Func_Code += ERR_VALUES_START;
return RS_PARSE_MSG_ERR;
}
uint16_t *tmp_data_addr = (uint16_t *)modbus_msg->DATA;
for(int i = 0; i < modbus_msg->ByteCnt; i++) // /2 because we transmit 8 bits, not 16 bits
{ // set data
if (i%2 == 0)
*tmp_data_addr = ((uint16_t)modbus_uart_buff[ind++] << 8);
else
{
*tmp_data_addr |= modbus_uart_buff[ind++];
tmp_data_addr++;
}
}
}
//---------------CRC----------------
//----------[last 16 bits]----------
// calc crc of received data
uint16_t CRC_VALUE = crc16(modbus_uart_buff, ind);
// get crc of received data
modbus_msg->MB_CRC = modbus_uart_buff[ind++];
modbus_msg->MB_CRC |= modbus_uart_buff[ind++] << 8;
// compare crc
if (modbus_msg->MB_CRC != CRC_VALUE)
modbus_msg->Func_Code += ERR_VALUES_START;
// hmodbus->MB_RESPONSE = MB_CRC_ERR; // set func code - error about wrong crc
// check is buffer empty
check_empty_buff = 0;
for(int i=0; i<ind;i++)
check_empty_buff += modbus_uart_buff[i];
// if(check_empty_buff == 0)
// hmodbus->MB_RESPONSE = MB_EMPTY_MSG; //
}
return RS_OK;
}
/**
* @brief Define size of RX Message that need to be received.
* @param hRS - указатель на хендлер RS.
* @param rx_data_size - указатель на переменную для записи кол-ва байт для принятия.
* @return RS_RES - статус о корректности рассчета кол-ва байт для принятия.
* @note Определение сколько байтов надо принять по протоколу.
*/
RS_StatusTypeDef RS_Define_Size_of_RX_Message(RS_HandleTypeDef *hmodbus, uint32_t *rx_data_size)
{
RS_StatusTypeDef MB_RES = 0;
MB_RES = Parse_Message(hmodbus, hmodbus->pMessagePtr, hmodbus->pBufferPtr);
if(MB_RES == RS_SKIP) // if message not for us
return MB_RES; // return
if ((hmodbus->pMessagePtr->Func_Code & ~ERR_VALUES_START) < 0x0F)
{
hmodbus->pMessagePtr->ByteCnt = 0;
*rx_data_size = 1;
}
else
{
hmodbus->pMessagePtr->ByteCnt = hmodbus->pBufferPtr[RX_FIRST_PART_SIZE-1]; // get numb of data in command
// +1 because that defines is size, not ind.
*rx_data_size = hmodbus->pMessagePtr->ByteCnt + 2;
}
hmodbus->RS_Message_Size = RX_FIRST_PART_SIZE + *rx_data_size; // size of whole message
return RS_OK;
}
//-----------------------------FOR USER------------------------------
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//-------------------------HANDLERS FUNCTION-------------------------
#if (MODBUS_UART_NUMB == 1) // choose handler for UART
void USART1_IRQHandler(void)
#elif (MODBUS_UART_NUMB == 2)
void USART2_IRQHandler(void)
#elif (MODBUS_UART_NUMB == 3)
void USART3_IRQHandler(void)
#elif (MODBUS_UART_NUMB == 4)
void USART4_IRQHandler(void)
#elif (MODBUS_UART_NUMB == 5)
void USART5_IRQHandler(void)
#elif (MODBUS_UART_NUMB == 6)
void USART6_IRQHandler(void)
#endif
{
Trace_MB_UART_Enter();
RS_UART_Handler(&hmodbus1);
Trace_MB_UART_Exit();
}
#if (MODBUS_TIM_NUMB == 1) || (MODBUS_TIM_NUMB == 10) // choose handler for TIM
void TIM1_UP_TIM10_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 2)
void TIM2_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 3)
void TIM3_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 4)
void TIM4_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 5)
void TIM5_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 6)
void TIM6_DAC_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 7)
void TIM7_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 8) || (MODBUS_TIM_NUMB == 13)
void TIM8_UP_TIM13_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 1) || (MODBUS_TIM_NUMB == 9)
void TIM1_BRK_TIM9_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 1) || (MODBUS_TIM_NUMB == 11)
void TIM1_TRG_COM_TIM11_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 8) || (MODBUS_TIM_NUMB == 12)
void TIM8_BRK_TIM12_IRQHandler(void)
#elif (MODBUS_TIM_NUMB == 8) || (MODBUS_TIM_NUMB == 14)
void TIM8_TRG_COM_TIM14_IRQHandler(void)
#endif
{
Trace_MB_TIM_Enter();
RS_TIM_Handler(&hmodbus1);
Trace_MB_TIM_Exit();
}
//-------------------------HANDLERS FUNCTION-------------------------
//-------------------------------------------------------------------

418
Code/Modbus/modbus.h
View File

@@ -1,418 +0,0 @@
/********************************MODBUS*************************************
Данный файл содержит объявления базовых функции и дефайны для реализации
MODBUS.
Данный файл необходимо подключить в rs_message.h. После подключать rs_message.h
к основному проекту.
***************************************************************************/
#ifndef __MODBUS_H_
#define __MODBUS_H_
#include "stm32f4xx_hal.h"
#include "modbus_data.h"
#include "settings.h" // for modbus settings
/////////////////////////////////////////////////////////////////////
//////////////////////////---SETTINGS---/////////////////////////////
////----------DEFINES FOR MODBUS SETTING--------------
//#define MODBUS_UART_NUMB 3 // number of used uart
//#define MODBUS_SPEED 115200
//#define MODBUS_GPIOX GPIOB
//#define MODBUS_GPIO_PIN_RX GPIO_PIN_11
//#define MODBUS_GPIO_PIN_TX GPIO_PIN_10
///* accord to this define sets define USED_MB_UART = USARTx */
//#define MODBUS_TIM_NUMB 7 // number of used uart
//#define MODBUS_TIM_AHB_FREQ 72
///* accord to this define sets define USED_MB_TIM = TIMx */
///* defines for modbus behaviour */
//#define MODBUS_DEVICE_ID 1 // number of used uart
//#define MODBUS_MAX_TIMEOUT 5000 // is ms
//// custom define for size of receive message
////--------------------------------------------------
//---------------MODBUS DEVICE DATA-----------------
/* EXTERN REGISTERS/COILS */
extern uint16_t sine_log[R_SINE_LOG_QNT]; // start from 0x0000
extern uint16_t pwm_log[R_PWM_LOG_QNT]; // start from 500 (0x1F4)
extern uint16_t cnt_log[R_CNT_LOG_QNT]; // start from 100 (0x3E8)
extern uint16_t time_log[R_TIME_LOG_QNT]; // start from 1500 (0x5DC)
extern uint16_t pwm_ctrl[R_PWM_CTRL_QNT]; // start from 2000 (0x7D0)
extern uint16_t log_ctrl[R_LOG_CTRL_QNT]; // start from 2008 (0x7D0)
extern uint16_t uart_ctrl[R_UART_CTRL_QNT];
extern uint16_t coils_regs[C_CTRL_COILS_QNT]; // start from 0x0001 (16th bit)
//--------------------------------------------------
//////////////////////////---SETTINGS---/////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////---USER MESSAGE DEFINES---//////////////////////
//-------------DEFINES FOR STRUCTURE----------------
/* defines for structure of modbus message */
#define MbAddr_SIZE 1 // size of (MbAddr)
#define Func_Code_SIZE 1 // size of (Func_Code)
#define Addr_SIZE 2 // size of (Addr)
#define Qnt_SIZE 2 // size of (Qnt)
#define ByteCnt_SIZE 1 // size of (ByteCnt)
#define DATA_SIZE 125 // maximum number of data: DWORD (NOT MESSAGE SIZE)
#define CRC_SIZE 2 // size of (MB_CRC) in bytes
/* size of info */
#define INFO_SIZE_MAX (MbAddr_SIZE+Func_Code_SIZE+Addr_SIZE+Qnt_SIZE+ByteCnt_SIZE)
/* size of first part of message that will be received
first receive info part of message, than defines size of rest message*/
#define RX_FIRST_PART_SIZE INFO_SIZE_MAX
/* size of buffer: max size of whole message */
#define MSG_SIZE_MAX (INFO_SIZE_MAX + DATA_SIZE*2 + CRC_SIZE) // max possible size of message
/* Structure for modbus exception codes */
typedef enum //MB_ExceptionTypeDef
{
// reading
NO_ERRORS = 0x00, // no errors
ILLEGAL_FUNCTION = 0x01, // function cannot be processed
ILLEGAL_DATA_ADDRESS = 0x02, // data at this address is not available
ILLEGAL_DATA_VALUE = 0x03, // uncorrect data value (quantity too big and cannot be returned or value for coil is incorrect)
SLAVE_DEVICE_FAILURE = 0x04, // idk
ACKNOWLEDGE = 0x05, // idk
SLAVE_DEVICE_BUSY = 0x06, // idk
MEMORY_PARITY_ERROR = 0x08, // idk
}MB_ExceptionTypeDef;
/* Structure for modbus func codes */
typedef enum //MB_FunctonTypeDef
{
// reading
MB_R_COILS = 0x01,
MB_R_DISC_IN = 0x02,
MB_R_IN_REGS = 0x03,
MB_R_HOLD_REGS = 0x04,
// writting
MB_W_COIL = 0x05,
MB_W_IN_REG = 0x06,
MB_W_COILS = 0x0F,
MB_W_IN_REGS = 0x10,
}MB_FunctonTypeDef;
#define ERR_VALUES_START 0x80U // from this value starts error func codes
/* Structure for modbus messsage */
typedef struct // RS_MsgTypeDef
{
uint8_t MbAddr;
MB_FunctonTypeDef Func_Code;
uint16_t Addr;
uint16_t Qnt;
uint8_t ByteCnt;
uint16_t DATA[DATA_SIZE];
MB_ExceptionTypeDef Except_Code;
uint16_t MB_CRC;
}RS_MsgTypeDef;
//--------------------------------------------------
/////////////////////---USER MESSAGE DEFINES---//////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////---GENERAL MODBUS STUFF---//////////////////////
/* Structure for coils operation */
typedef enum
{
// READ_COIL,
SET_COIL,
RESET_COIL,
TOOGLE_COIL,
}MB_CoilsOpTypeDef;
//------------DEFINES FOR PROCESS DATA--------------
/**
* @brief Calc dividing including remainder
* @param _val_ - делимое.
* @param _div_ - делитель.
* @note Если результат деления без остатка: он возвращается как есть
Если с остатком - округляется вверх
*/
//#define Divide_Up(_val_, _div_) (((_val_)%(_div_))? (_val_)/(_div_)+1 : (_val_)/_div_) /* через тернарный оператор */
#define Divide_Up(_val_, _div_) ((_val_ - 1) / _div_) + 1 /* через мат выражение */
/**
* @brief Swap between Little Endian and Big Endian
* @param v - Переменная для свапа.
* @return v (new) - Свапнутая переменная.
* @note Переключения между двумя типами хранения слова: HI-LO байты и LO-HI байты.
*/
#define ByteSwap16(v) (((v&0xFF00) >> (8)) | ((v&0x00FF) << (8)))
//--------------------------------------------------
//-----------DEFINES FOR ACCESS TO DATA-------------
/**
* @brief Macros to set pointer to 16-bit array
* @param _arr_ - массив слов (16-бит).
*/
#define MB_Set_Arr16_Ptr(_arr_) ((uint16_t*)(&(_arr_)))
/**
* @brief Macros to set pointer to register
* @param _parr_ - массив регистров.
* @param _addr_ - Номер регистра (его индекс) от начала массива _arr_.
*/
#define MB_Set_Register_Ptr(_parr_, _addr_) ((uint16_t *)(_parr_)+(_addr_))
/**
* @brief Macros to set pointer to a certain register that contains certain coil
* @param _parr_ - массив коилов.
* @param _coil_ - Номер коила от начала массива _arr_.
* @note Пояснение выражений
* (_coil_/16) - get index (address shift) of register that contain certain coil
* (16*(_coil_/16) - how many coils we need to skip. e.g. (16*30/16) - skip 16 coils from first register
* _coil_-(16*(_coil_/16)) - shift to certain coil in certain register
* e.g. Coil(30) gets in register[1] (30/16 = 1) coil №14 (30 - (16*30/16) = 30 - 16 = 14)
*
* Visual explanation:
* xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxCx
* |register[0]----| |register[1]----|
* |skip this------| |get this-------|
* |shift to 14 bit|
*/
#define MB_Set_Coil_Reg_Ptr(_parr_, _coil_) ((uint16_t *)(_parr_)+((_coil_)/16))
#define MB_Set_Coil_Mask(_coil_) (1 << ( _coil_ - (16*((_coil_)/16)) ))
/**
* @brief Read Coil at its local address.
* @param _parr_ - массив коилов.
* @param _coil_ - Номер коила от начала массива _arr_.
* @return uint16_t - Возвращает весь регистр с маской на запрошенном коиле.
*
* @note Позволяет обратиться к коилу по адресу относительно _arr_.
*/
#define MB_Read_Coil_Local(_parr_, _coil_) (( *MB_Set_Coil_Reg_Ptr(_parr_, _coil_) & MB_Set_Coil_Mask(_coil_) ) >> _coil_)
/**
* @brief Set Coil at its local address.
* @param _parr_ - указатель на массив коилов.
* @param _coil_ - Номер коила от начала массива _arr_.
*
* @note Позволяет обратиться к коилу по адресу относительно _arr_.
*/
#define MB_Set_Coil_Local(_parr_, _coil_) *MB_Set_Coil_Reg_Ptr(_parr_, _coil_) |= MB_Set_Coil_Mask(_coil_)
/**
* @brief Reset Coil at its local address.
* @param _parr_ - указатель на массив коилов.
* @param _coil_ - Номер коила от начала массива _arr_.
*
* @note Позволяет обратиться к коилу по адресу относительно _arr_.
*/
#define MB_Reset_Coil_Local(_parr_, _coil_) *MB_Set_Coil_Reg_Ptr(_parr_, _coil_) &= ~(MB_Set_Coil_Mask(_coil_))
/**
* @brief Set Coil at its local address.
* @param _parr_ - указатель на массив коилов.
* @param _coil_ - Номер коила от начала массива _arr_.
*
* @note Позволяет обратиться к коилу по адресу относительно _arr_.
*/
#define MB_Toogle_Coil_Local(_parr_, _coil_) *MB_Set_Coil_Reg_Ptr(_parr_, _coil_) ^= MB_Set_Coil_Mask(_coil_)
//--------------------------------------------------
//------------------OTHER DEFINES-------------------
// create hadnles and settings for uart, tim, rs with _modbus_ name
#define CONCAT(a,b) a##b
#define Create_MODBUS_Handles(_modbus_) \
UART_SettingsTypeDef CONCAT(_modbus_, _suart); \
UART_HandleTypeDef CONCAT(_modbus_, _huart); \
TIM_SettingsTypeDef CONCAT(_modbus_, _stim); \
TIM_HandleTypeDef CONCAT(_modbus_, _htim); \
RS_HandleTypeDef CONCAT(h, _modbus_)
//--------------------------------------------------
///////////////////---MODBUS & MESSAGE DEFINES---////////////////////
/////////////////////////////////////////////////////////////////////
////////////////////---FUNCTIONS FOR USER---/////////////////////////
/**
* @brief First set up of MODBUS.
* @note Первый инит модбас. Заполняет структуры и инициализирует таймер и юарт для общения по модбас.
* Скважность ШИМ меняется по закону синусоиды, каждый канал генерирует свой полупериод синуса (от -1 до 0 И от 0 до 1)
* ШИМ генерируется на одном канале.
* @note This called from main
*/
void MODBUS_FirstInit(void);
/**
* @brief Set or Reset Coil at its global address.
* @param Addr - адрес коила.
* @param WriteVal - Что записать в коил: 0 или 1.
* @return ExceptionCode - Код исключения если коила по адресу не существует, и NO_ERRORS если все ок.
*
* @note Позволяет обратиться к любому коилу по его глобальному адрессу.
Вне зависимости от того как коилы размещены в памяти.
*/
MB_ExceptionTypeDef MB_Write_Coil_Global(uint16_t Addr, MB_CoilsOpTypeDef WriteVal);
/**
* @brief Read Coil at its global address.
* @param Addr - адрес коила.
* @param Exception - Указатель на переменную для кода исключения, в случа неудачи при чтении.
* @return uint16_t - Возвращает весь регистр с маской на запрошенном коиле.
*
* @note Позволяет обратиться к любому коилу по его глобальному адрессу.
Вне зависимости от того как коилы размещены в памяти.
*/
uint16_t MB_Read_Coil_Global(uint16_t Addr, MB_ExceptionTypeDef *Exception);
////////////////////---FUNCTIONS FOR USER---/////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////---PROCESS MODBUS COMMAND FUNCTIONS---//////////////////
/**
* @brief Check is address valid for certain array.
* @param Addr - начальный адресс.
* @param Qnt - количество запрашиваемых элементов.
* @param R_ARR_ADDR - начальный адресс массива R_ARR.
* @param R_ARR_NUMB - количество элементов в массиве R_ARR.
* @return ExceptionCode - ILLEGAL DATA ADRESS если адресс недействителен, и NO_ERRORS если все ок.
*
* @note Позволяет определить, брать ли данные по адрессу Addr из массива R_ARR.
* Если адресс Addr находится в диапазоне адрессов массива R_ARR, то возвращаем NO_ERROR.
* Если адресс Addr находится за пределами адрессов массива R_ARR - ILLEGAL_DATA_ADDRESSю.
*/
MB_ExceptionTypeDef MB_Check_Address_For_Arr(uint16_t Addr, uint16_t Qnt, uint16_t R_ARR_ADDR, uint16_t R_ARR_NUMB);
/**
* @brief Define Address Origin for Input/Holding Registers
* @param pRegs - указатель на указатель регистров.
* @param Addr - адрес начального регистра.
* @param Qnt - количество запрашиваемых регистров.
* @param WriteFlag - флаг регистр нужны для чтения или записи.
* @return ExceptionCode - Код исключения если есть, и NO_ERRORS если нет.
*
* @note Определение адреса начального регистра.
* @note WriteFlag пока не используется.
*/
MB_ExceptionTypeDef MB_DefineRegistersAddress(uint16_t **pRegs, uint16_t Addr, uint16_t Qnt, uint8_t WriteFlag);
/**
* @brief Define Address Origin for coils
* @param pCoils - указатель на указатель коилов.
* @param Addr - адресс начального коила.
* @param Qnt - количество запрашиваемых коилов.
* @param start_shift - указатель на переменную содержащую сдвиг внутри регистра для начального коила.
* @param WriteFlag - флаг коилы нужны для чтения или записи.
* @return ExceptionCode - Код исключения если есть, и NO_ERRORS если нет.
*
* @note Определение адреса начального регистра запрашиваемых коилов.
* @note WriteFlag используется для определния регистров GPIO: ODR или IDR.
*/
MB_ExceptionTypeDef MB_DefineCoilsAddress(uint16_t **pCoils, uint16_t Addr, uint16_t Qnt, uint16_t *start_shift, uint8_t WriteFlag);
/**
* @brief Proccess command Read Coils (01 - 0x01).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Read Coils.
*/
uint8_t MB_Read_Coils(RS_MsgTypeDef *modbus_msg);
/**
* @brief Proccess command Read Holding Registers (03 - 0x03).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Read Holding Registers.
*/
uint8_t MB_Read_Hold_Regs(RS_MsgTypeDef *modbus_msg);
/**
* @brief Proccess command Write Single Coils (05 - 0x05).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Single Coils.
*/
uint8_t MB_Write_Single_Coil(RS_MsgTypeDef *modbus_msg);
/**
* @brief Proccess command Write Multiple Coils (15 - 0x0F).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Multiple Coils.
*/
uint8_t MB_Write_Miltuple_Coils(RS_MsgTypeDef *modbus_msg);
/**
* @brief Proccess command Write Multiple Register (16 - 0x10).
* @param modbus_msg - указатель на структуру собщения modbus.
* @return fMessageHandled - статус о результате обработки комманды.
* @note Обработка команды Write Multiple Register.
*/
uint8_t MB_Write_Miltuple_Regs(RS_MsgTypeDef *modbus_msg);
/////////////---PROCESS MODBUS COMMAND FUNCTIONS---//////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////---CALC DEFINES---//////////////////////////
/* set USART_TypeDef for choosen numb of usart */
#if (MODBUS_UART_NUMB == 1)
#define USED_MODBUS_UART USART1
#define USE_USART1
#elif (MODBUS_UART_NUMB == 2)
#define USED_MODBUS_UART USART2
#define USE_USART2
#elif (MODBUS_UART_NUMB == 3)
#define USED_MODBUS_UART USART3
#define USE_USART3
#elif (MODBUS_UART_NUMB == 4)
#define USED_MODBUS_UART UART4
#define USE_UART4
#elif (MODBUS_UART_NUMB == 5)
#define USED_MODBUS_UART UART5
#define USE_UART6
#elif (MODBUS_UART_NUMB == 6)
#define USED_MODBUS_UART USART6
#define USE_USART6
#endif
#if (MODBUS_TIM_NUMB == 1)
#define USED_MODBUS_TIM TIM1
#define USE_TIM1
#elif (MODBUS_TIM_NUMB == 2)
#define USED_MODBUS_TIM TIM2
#define USE_TIM2
#elif (MODBUS_TIM_NUMB == 3)
#define USED_MODBUS_TIM TIM3
#define USE_TIM3
#elif (MODBUS_TIM_NUMB == 4)
#define USED_MODBUS_TIM TIM4
#define USE_TIM4
#elif (MODBUS_TIM_NUMB == 5)
#define USED_MODBUS_TIM TIM5
#define USE_TIM5
#elif (MODBUS_TIM_NUMB == 6)
#define USED_MODBUS_TIM TIM6
#define USE_TIM6
#elif (MODBUS_TIM_NUMB == 7)
#define USED_MODBUS_TIM TIM7
#define USE_TIM7
#elif (MODBUS_TIM_NUMB == 8)
#define USED_MODBUS_TIM TIM8
#define USE_TIM8
#elif (MODBUS_TIM_NUMB == 9)
#define USED_MODBUS_TIM TIM9
#define USE_TIM9
#elif (MODBUS_TIM_NUMB == 10)
#define USED_MODBUS_TIM TIM10
#define USE_TIM10
#elif (MODBUS_TIM_NUMB == 11)
#define USED_MODBUS_TIM TIM11
#define USE_TIM11
#elif (MODBUS_TIM_NUMB == 12)
#define USED_MODBUS_TIM TIM12
#define USE_TIM12
#elif (MODBUS_TIM_NUMB == 13)
#define USED_MODBUS_TIM TIM13
#define USE_TIM13
#elif (MODBUS_TIM_NUMB == 14)
#define USED_MODBUS_TIM TIM14
#define USE_TIM14
#endif
#endif //__MODBUS_H_

71
Code/Modbus/modbus_data.h
View File

@@ -1,71 +0,0 @@
//-----------MODBUS DEVICE DATA SETTING-------------
//--------------DEFINES FOR REGISTERS---------------
// DEFINES FOR ARRAYS
#define LOG_SIZE 500
#define R_SINE_LOG_ADDR 0
#define R_SINE_LOG_QNT LOG_SIZE
#define R_PWM_LOG_ADDR 500
#define R_PWM_LOG_QNT LOG_SIZE
#define R_CNT_LOG_ADDR 1000
#define R_CNT_LOG_QNT LOG_SIZE
#define R_TIME_LOG_ADDR 1500
#define R_TIME_LOG_QNT LOG_SIZE
#define R_SETTINGS_START_ADDR 20000
#define R_PWM_CTRL_ADDR R_SETTINGS_START_ADDR
#define R_PWM_CTRL_QNT 8
#define R_LOG_CTRL_ADDR (R_SETTINGS_START_ADDR+8)
#define R_LOG_CTRL_QNT 8
#define R_UART_CTRL_ADDR R_SETTINGS_START_ADDR+16
#define R_UART_CTRL_QNT 8
// DEFINES FOR REGISTERS
#define R_PWM_CTRL_PWM_VALUE 0 // PWM value: sin freq OR pwm duty
#define R_PWM_CTRL_PWM_HZ 1 // frequency of PWM Timer
#define R_PWM_CTRL_MIN_PULSE_DUR 2 // duration of shortest pulse in sine PWM
#define R_PWM_CTRL_DEAD_TIME 3 // duration between between switches half waves (channels)
#define R_PWM_CTRL_SIN_TABLE_SIZE 4 // size of sinus table
#define R_LOG_CTRL_LOG_SIZE 0 // size of number elements in log
#define R_LOG_CTRL_LOG_PWM_NUMB 1 // number of PWM periods in log
#define R_LOG_CTRL_LOG_HZ 2 // frequency of log Timer
#define R_UART_CTRL_SPEED 0 // sin frequency
//----------------DEFINES FOR COILS-----------------
// DEFINES FOR ARRAYS
#define C_GPIOD_ADDR 0
#define C_GPIOD_QNT 16 // minimum 16
#define C_CTRL_COILS_ADDR 0x10
#define C_CTRL_COILS_QNT 160 // minimum 16
// DEFINES FOR COILS
#define COIL_GPIOD_LED1 12
#define COIL_GPIOD_LED2 13
#define COIL_GPIOD_LED3 14
#define COIL_GPIOD_LED4 15
#define COIL_GPIOD_LED1_GLOBAL (C_GPIOD_ADDR+COIL_GPIOD_LED1)
#define COIL_GPIOD_LED2_GLOBAL (C_GPIOD_ADDR+COIL_GPIOD_LED2)
#define COIL_GPIOD_LED3_GLOBAL (C_GPIOD_ADDR+COIL_GPIOD_LED3)
#define COIL_GPIOD_LED4_GLOBAL (C_GPIOD_ADDR+COIL_GPIOD_LED4)
#define COIL_UART_CTRL (0)
#define COIL_UART_CTRL_GLOBAL (C_CTRL_COILS_ADDR+COIL_UART_CTRL)
#define COIL_PWM_DC_MODE (1)
#define COIL_PWM_DC_MODE_GLOBAL (C_CTRL_COILS_ADDR+COIL_PWM_DC_MODE)
#define COIL_PWM_CH_MODE (2)
#define COIL_PWM_CH_MODE_GLOBAL (C_CTRL_COILS_ADDR+COIL_PWM_CH_MODE)
#define COIL_PWM_PHASE_MODE (3)
#define COIL_PWM_PHASE_MODE_GLOBAL (C_CTRL_COILS_ADDR+COIL_PWM_PHASE_MODE)

502
Code/Modbus/rs_message.c
View File

@@ -1,502 +0,0 @@
/**********************************RS***************************************
Данный файл содержит базовые функции для реализации протоколов по RS/UART.
//-------------------Функции-------------------//
@func users
- Parse_Message/Collect_Message Заполнение структуры сообщения и буфера
- RS_Response Ответ на сообщение
- RS_Define_Size_of_RX_Message Определение размера принимаемых данных
@func general
- RS_Receive_IT Ожидание комманды и ответ на неё
- RS_Transmit_IT Отправление комманды и ожидание ответа
- RS_Init Инициализация переферии и структуры для RS
- RS_ReInit_UART Реинициализация UART для RS
- RS_Abort Отмена приема/передачи по ЮАРТ
- RS_Init Инициализация периферии и modbus handler
@func callback/handler
- RS_Handle_Receive_Start Функция для запуска приема или остановки RS
- RS_Handle_Transmit_Start Функция для запуска передачи или остановки RS
- RS_UART_RxCpltCallback Коллбек при окончании приема или передачи
RS_UART_TxCpltCallback
- RS_UART_Handler Обработчик прерывания для UART
- RS_TIM_Handler Обработчик прерывания для TIM
@func uart initialize (это было в отдельных файлах, мб надо обратно разнести)
- UART_Base_Init Инициализация UART для RS
- RS_UART_GPIO_Init Инициализация GPIO для RS
- UART_DMA_Init Инициализация DMA для RS
- UART_MspInit Аналог HAL_MspInit для RS
- UART_MspDeInit Аналог HAL_MspDeInit для RS
//-------------------Общее--------------------//
@note Для настройки RS/UART под нужный протокол, необходимо:
- Определить структуру сообщения RS_MsgTypeDef и
дефайны RX_FIRST_PART_SIZE и MSG_SIZE_MAX.
- Подключить этот файл в раздел USER SETTINGS rs_message.h.
- Определить функции для обработки сообщения @func users.
- Добавить UART/TIM Handler в Хендлер используемых UART/TIM.
***************************************************************************/
#include "rs_message.h"
uint8_t RS_Buffer[MSG_SIZE_MAX]; // uart buffer
//-------------------------------------------------------------------
//-------------------------GENERAL FUNCTIONS-------------------------
/**
* @brief Start receive IT.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации приема.
*/
RS_StatusTypeDef RS_Receive_IT(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg)
{
RS_StatusTypeDef RS_RES = 0;
HAL_StatusTypeDef uart_res = 0;
//-------------CHECK RS LINE----------------
// check that receive isnt busy
if( RS_Is_RX_Busy(hRS) ) // if tx busy - return busy status
return RS_BUSY;
//-----------INITIALIZE RECEIVE-------------
// if all OK: start receiving
RS_Set_Busy(hRS); // set RS busy
RS_Set_RX_Flags(hRS); // initialize flags for receive
hRS->pMessagePtr = RS_msg; // set pointer to message structire for filling it from UARTHandler fucntions
// start receiving
uart_res = HAL_UART_Receive_IT(hRS->huart, hRS->pBufferPtr, RX_FIRST_PART_SIZE); // receive until ByteCnt+1 byte,
// then in Callback restart receive for rest bytes
// if receive isnt started - abort RS
if(uart_res != HAL_OK)
{
RS_RES = RS_Abort(hRS, ABORT_RS);
}
else
RS_RES = RS_OK;
hRS->RS_STATUS = RS_RES;
return RS_RES; // returns result of receive init
}
/**
* @brief Start transmit IT.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации передачи.
*/
RS_StatusTypeDef RS_Transmit_IT(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg)
{
RS_StatusTypeDef RS_RES = 0;
HAL_StatusTypeDef uart_res = 0;
//-------------CHECK RS LINE----------------
// check that transmit isnt busy
if( RS_Is_TX_Busy(hRS) ) // if tx busy - return busy status
return RS_BUSY;
// check receive line
//------------COLLECT MESSAGE---------------
RS_RES = Collect_Message(hRS, RS_msg, hRS->pBufferPtr);
if (RS_RES != RS_OK) // if message isnt collect - stop RS and return error in RS_RES
{// need collect message status, so doesnt write abort to RS_RES
RS_Abort(hRS, ABORT_RS);
RS_Handle_Receive_Start(hRS, hRS->pMessagePtr); // restart receive
}
else // if collect successful
{
//----------INITIALIZE TRANSMIT-------------
RS_Set_Busy(hRS); // set RS busy
RS_Set_TX_Flags(hRS); // initialize flags for transmit IT
hRS->pMessagePtr = RS_msg; // set pointer for filling given structure from UARTHandler fucntion
// if all OK: start transmitting
uart_res = HAL_UART_Transmit_IT(hRS->huart, hRS->pBufferPtr, hRS->RS_Message_Size);
// if transmit isnt started - abort RS
if(uart_res != HAL_OK)
{
RS_RES = RS_Abort(hRS, ABORT_RS);
}
else
RS_RES = RS_OK;
}
hRS->RS_STATUS = RS_RES;
return RS_RES; // returns result of transmit init
}
/**
* @brief Initialize UART and handle RS stucture.
* @param hRS - указатель на хендлер RS.
* @param suart - указатель на структуру с настройками UART.
* @param stim - указатель на структуру с настройками таймера.
* @param pRS_BufferPtr - указатель на буффер для приема-передачи по UART. Если он NULL, то поставиться библиотечный буфер.
* @return RS_RES - статус о состоянии RS после инициализации.
* @note Инициализация перефирии и структуры для приема-передачи по RS.
*/
RS_StatusTypeDef RS_Init(RS_HandleTypeDef *hRS, UART_SettingsTypeDef *suart, TIM_SettingsTypeDef *stim, uint8_t *pRS_BufferPtr)
{
// check that hRS is defined
if (hRS == NULL)
return RS_ERR;
// check that huart is defined
if ((suart->huart.Instance == NULL) || (suart->huart.Init.BaudRate == NULL))
return RS_ERR;
// init uart
UART_Base_Init(suart);
hRS->huart = &suart->huart;
// check that timeout in interrupt needed
if (hRS->sRS_Timeout)
{
if (stim->htim.Instance == NULL) // check is timer defined
return RS_ERR;
// calc frequency corresponding to timeout and tims 1ms tickbase
stim->sTickBaseMHz = TIM_TickBase_1MS;
stim->htim.Init.Period = hRS->sRS_Timeout;
TIM_Base_Init(stim);
hRS->htim = &stim->htim;
}
if (hRS->sRS_RX_Size_Mode == NULL)
return RS_ERR;
// check that buffer is defined
if (hRS->pBufferPtr == NULL)
{
hRS->pBufferPtr = RS_Buffer; // if no - set default
}
else
hRS->pBufferPtr = pRS_BufferPtr; // if yes - set by user
return RS_OK;
}
/**
* @brief ReInitialize UART and RS receive.
* @param hRS - указатель на хендлер RS.
* @param suart - указатель на структуру с настройками UART.
* @return RS_RES - статус о состоянии RS после инициализации.
* @note Реинициализация UART и приема по RS.
*/
HAL_StatusTypeDef RS_ReInit_UART(RS_HandleTypeDef *hRS, UART_SettingsTypeDef *suart)
{
HAL_StatusTypeDef RS_RES;
hRS->fReInit_UART = 0;
// check is settings are valid
if(Check_UART_Init_Struct(suart) != HAL_OK)
return HAL_ERROR;
RS_Abort(hRS, ABORT_RS);
UART_MspDeInit(&suart->huart);
RS_RES = UART_Base_Init(suart);
RS_Receive_IT(hRS, hRS->pMessagePtr);
return RS_RES;
}
/**
* @brief Abort RS/UART.
* @param hRS - указатель на хендлер RS.
* @param AbortMode - выбор, что надо отменить.
- ABORT_TX: Отмена передачи по ЮАРТ, с очищением флагов TX,
- ABORT_RX: Отмена приема по ЮАРТ, с очищением флагов RX,
- ABORT_RX_TX: Отмена приема и передачи по ЮАРТ,
- ABORT_RS: Отмена приема-передачи RS, с очищением всей структуры.
* @return RS_RES - статус о состоянии RS после аборта.
* @note Отмена работы UART в целом или отмена приема/передачи RS.
Также очищается хендл hRS.
*/
RS_StatusTypeDef RS_Abort(RS_HandleTypeDef *hRS, RS_AbortTypeDef AbortMode)
{
HAL_StatusTypeDef uart_res = 0;
hRS->htim->Instance->CNT = 0;
__HAL_TIM_CLEAR_IT(hRS->htim, TIM_IT_UPDATE);
if(hRS->sRS_Timeout) // if timeout setted
HAL_TIM_Base_Stop_IT(hRS->htim); // stop timeout
if((AbortMode&ABORT_RS) == 0x00)
{
if((AbortMode&ABORT_RX) == ABORT_RX)
{
uart_res = HAL_UART_AbortReceive(hRS->huart); // abort receive
RS_Reset_RX_Flags(hRS);
}
if((AbortMode&ABORT_TX) == ABORT_TX)
{
uart_res = HAL_UART_AbortTransmit(hRS->huart); // abort transmit
RS_Reset_TX_Flags(hRS);
}
}
else
{
uart_res = HAL_UART_Abort(hRS->huart);
RS_Clear_All(hRS);
}
hRS->RS_STATUS = RS_ABORTED;
return RS_ABORTED;
}
//-------------------------GENERAL FUNCTIONS-------------------------
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//--------------------CALLBACK/HANDLER FUNCTIONS---------------------
/**
* @brief Handle for starting receive.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации приема или окончания общения.
* @note Определяет начинать прием команды/ответа или нет.
*/
RS_StatusTypeDef RS_Handle_Receive_Start(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg)
{
RS_StatusTypeDef RS_RES = 0;
switch(hRS->sRS_Mode)
{
case SLAVE_ALWAYS_WAIT: // in slave mode with permanent waiting
RS_RES = RS_Receive_IT(hRS, RS_msg); break; // start receiving again
case SLAVE_TIMEOUT_WAIT: // in slave mode with timeout waiting (start receiving cmd by request)
RS_Set_Free(hRS); RS_RES = RS_OK; break; // end RS communication (set RS unbusy)
}
return RS_RES;
}
/**
* @brief Handle for starting transmit.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации передачи.
* @note Определяет отвечать ли на команду или нет.
*/
RS_StatusTypeDef RS_Handle_Transmit_Start(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg)
{
RS_StatusTypeDef RS_RES = 0;
switch(hRS->sRS_Mode)
{
case SLAVE_ALWAYS_WAIT: // in slave mode always response
case SLAVE_TIMEOUT_WAIT: // transmit response
RS_RES = RS_Transmit_IT(hRS, RS_msg); break;
}
return RS_RES;
}
/**
* @brief UART RX Callback: define behaviour after receiving parts of message.
* @param hRS - указатель на хендлер RS.
* @return RS_RES - статус о состоянии RS после обработки приема.
* @note Контролирует прием сообщения: определяет размер принимаемой посылки и обрабатывает его.
*/
RS_StatusTypeDef RS_UART_RxCpltCallback(RS_HandleTypeDef *hRS)
{
RS_StatusTypeDef RS_RES = 0;
HAL_StatusTypeDef uart_res = 0;
// if we had received bytes before ByteCnt
if((hRS->sRS_RX_Size_Mode == RS_RX_Size_NotConst) && (hRS->fRX_Half == 0)) // if data size isnt constant and its first half, and
{ // First receive part of message, then define size of rest of message, and start receive it
hRS->fRX_Half = 1;
//---------------FIND DATA SIZE-----------------
uint32_t NuRS_of_Rest_Bytes = 0;
RS_RES = RS_Define_Size_of_RX_Message(hRS, &NuRS_of_Rest_Bytes);
// if there is no bytes to receive OR we need to skip this message - restart receive
if ((NuRS_of_Rest_Bytes == 0) || (RS_RES == RS_SKIP))
{
RS_Abort(hRS, ABORT_RX);
RS_RES = RS_Handle_Receive_Start(hRS, hRS->pMessagePtr);
return RS_RES;
}
//-------------START UART RECEIVE---------------
uart_res = HAL_UART_Receive_IT(hRS->huart, (hRS->pBufferPtr + RX_FIRST_PART_SIZE), NuRS_of_Rest_Bytes);
if(uart_res != HAL_OK)
{// need uart status, so doesnt write abort to RS_RES
RS_RES = RS_Abort(hRS, ABORT_RS);
}
else
RS_RES = RS_OK;
}
else // if we had received whole message
{
hRS->fRX_Half = 0;
//---------PROCESS DATA & ENDING RECEIVING--------
RS_Set_RX_End(hRS);
if(hRS->sRS_Timeout) // if timeout setted
HAL_TIM_Base_Stop_IT(hRS->htim); // stop timeout
// parse received data
RS_RES = Parse_Message(hRS, hRS->pMessagePtr, hRS->pBufferPtr); // parse message
// RESPONSE
RS_RES = RS_Response(hRS, hRS->pMessagePtr);
}
return RS_RES;
}
/**
* @brief UART TX Callback: define behaviour after transmiting message.
* @param hRS - указатель на хендлер RS.
* @return RS_RES - статус о состоянии RS после обработки приема.
* @note Определяет поведение RS после передачи сообщения.
*/
RS_StatusTypeDef RS_UART_TxCpltCallback(RS_HandleTypeDef *hRS)
{
RS_StatusTypeDef RS_RES = RS_OK;
HAL_StatusTypeDef uart_res = 0;
//--------------ENDING TRANSMITTING-------------
RS_Set_TX_End(hRS);
//-----------START RECEIVING or END RS----------
RS_RES = RS_Handle_Receive_Start(hRS, hRS->pMessagePtr);
return RS_RES;
}
/**
* @brief Handler for UART.
* @param hRS - указатель на хендлер RS.
* @note Обрабатывает ошибки если есть и вызывает RS Коллбеки.
* Добавить вызов этой функции в UARTx_IRQHandler().
*/
void RS_UART_Handler(RS_HandleTypeDef *hRS)
{
HAL_UART_IRQHandler(hRS->huart);
//-------------CALL RS CALLBACKS------------
/* IF NO ERROR OCCURS */
if(hRS->huart->ErrorCode == 0)
{
hRS->htim->Instance->CNT = 0; // reset cnt;
/* Start timeout */
if(hRS->sRS_Timeout) // if timeout setted
if((hRS->huart->RxXferCount+1 == hRS->huart->RxXferSize) && RS_Is_RX_Busy(hRS)) // if first byte is received and receive is active
HAL_TIM_Base_Start_IT(hRS->htim);
/* RX Callback */
if (( hRS->huart->RxXferCount == 0U) && RS_Is_RX_Busy(hRS) && // if all bytes are received and receive is active
hRS->huart->RxState != HAL_UART_STATE_BUSY_RX) // also check that receive "REALLY" isnt busy
RS_UART_RxCpltCallback(hRS);
/* TX Callback */
if (( hRS->huart->TxXferCount == 0U) && RS_Is_TX_Busy(hRS) && // if all bytes are transmited and transmit is active
hRS->huart->gState != HAL_UART_STATE_BUSY_TX) // also check that receive "REALLY" isnt busy
RS_UART_TxCpltCallback(hRS);
}
//----------------ERRORS HANDLER----------------
else
{
/* de-init uart transfer */
RS_Abort(hRS, ABORT_RS);
RS_Handle_Receive_Start(hRS, hRS->pMessagePtr);
// later, maybe, will be added specific handlers for err
}
}
/**
* @brief Handler for TIM.
* @param hRS - указатель на хендлер RS.
* @note Попадание сюда = таймаут и перезапуск RS приема
* Добавить вызов этой функции в TIMx_IRQHandler().
*/
void RS_TIM_Handler(RS_HandleTypeDef *hRS)
{
HAL_TIM_IRQHandler(hRS->htim);
HAL_TIM_Base_Stop_IT(hRS->htim);
RS_Abort(hRS, ABORT_RS);
RS_Handle_Receive_Start(hRS, hRS->pMessagePtr);
}
//--------------------CALLBACK/HANDLER FUNCTIONS---------------------
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//--------------WEAK PROTOTYPES FOR PROCESSING MESSAGE---------------
///**
// * @brief Respond accord to received message.
// * @param hRS - указатель на хендлер RS.
// * @param RS_msg - указатель на структуру сообщения.
// * @return RS_RES - статус о результате ответа на комманду.
// * @note Обработка принятой комманды и ответ на неё.
// */
//__weak RS_StatusTypeDef RS_Response(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg)
//{
// /* Redefine function for user purposes */
// return RS_ERR;
//}
//
///**
// * @brief Collect message in buffer to transmit it.
// * @param hRS - указатель на хендлер RS.
// * @param RS_msg - указатель на структуру сообщения.
// * @param msg_uart_buff - указатель на буффер UART.
// * @return RS_RES - статус о результате заполнения буфера.
// * @note Заполнение буффера UART из структуры сообщения.
// */
//__weak RS_StatusTypeDef Collect_Message(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg, uint8_t *msg_uart_buff)
//{
// /* Redefine function for user purposes */
// return RS_ERR;
//}
//
///**
// * @brief Parse message from buffer to process it.
// * @param hRS - указатель на хендлер RS.
// * @param RS_msg - указатель на структуру сообщения.
// * @param msg_uart_buff - указатель на буффер UART.
// * @return RS_RES - статус о результате заполнения структуры.
// * @note Заполнение структуры сообщения из буффера UART.
// */
//__weak RS_StatusTypeDef Parse_Message(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg, uint8_t *msg_uart_buff)
//{
// /* Redefine function for user purposes */
// return RS_ERR;
//}
//
///**
// * @brief Define size of RX Message that need to be received.
// * @param hRS - указатель на хендлер RS.
// * @param rx_data_size - указатель на переменную для записи кол-ва байт для принятия.
// * @return RS_RES - статус о корректности рассчета кол-ва байт для принятия.
// * @note Определение сколько байтов надо принять по протоколу.
// */
//__weak RS_StatusTypeDef RS_Define_Size_of_RX_Message(RS_HandleTypeDef *hRS, uint32_t *rx_data_size)
//{
// /* Redefine function for user purposes */
// return RS_ERR;
//}
//--------------WEAK PROTOTYPES FOR PROCESSING MESSAGE---------------
//-------------------------------------------------------------------

297
Code/Modbus/rs_message.h
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@@ -1,297 +0,0 @@
/**********************************RS***************************************
Данный файл содержит объявления базовых функции и дефайны для реализации
протоколов по RS/UART.
***************************************************************************/
#ifndef __RS_LIB_H_
#define __RS_LIB_H_
#include "modbus.h"
#include "periph_general.h"
#include "crc_algs.h"
/////////////////////////////////////////////////////////////////////
////////////////////////////---DEFINES---////////////////////////////
/* Check that all defines required by RS are defined */
#ifndef MSG_SIZE_MAX
#error Define MSG_SIZE_MAX (Maximum size of message). This is necessary to create buffer for UART.
#endif
#ifndef RX_FIRST_PART_SIZE
#error Define RX_FIRST_PART_SIZE (Size of first part of message). This is necessary to receive the first part of the message, from which determine the size of the remaining part of the message.
#endif
/* Clear message-uart buffer */
#define RS_Clear_Buff(_buff_) for(int i=0; i<MSG_SIZE_MAX;i++) _buff_[i] = NULL
/* Set/Reset flags */
#define RS_Set_Free(_hRS_) _hRS_->fRS_Busy = 0
#define RS_Set_Busy(_hRS_) _hRS_->fRS_Busy = 1
#define RS_Set_RX_Flags(_hRS_) _hRS_->fRX_Busy = 1; _hRS_->fRX_Done = 0; _hRS_->fRX_Half = 0
#define RS_Set_TX_Flags(_hRS_) _hRS_->fTX_Busy = 1; _hRS_->fTX_Done = 0
#define RS_Reset_RX_Flags(_hRS_) _hRS_->fRX_Busy = 0; _hRS_->fRX_Done = 0; _hRS_->fRX_Half = 0
#define RS_Reset_TX_Flags(_hRS_) _hRS_->fTX_Busy = 0; _hRS_->fTX_Done = 0
#define RS_Set_RX_End_Flag(_hRS_) _hRS_->fRX_Done = 1
#define RS_Set_TX_End_Flag(_hRS_) _hRS_->fTX_Done = 1
#define RS_Set_RX_End(_hRS_) RS_Reset_RX_Flags(_hRS_); RS_Set_RX_End_Flag(_hRS_)
#define RS_Set_TX_End(_hRS_) RS_Reset_TX_Flags(_hRS_); RS_Set_TX_End_Flag(_hRS_)
/* Clear all RS stuff */
#define RS_Clear_All(_hRS_) RS_Clear_Buff(_hRS_->pBufferPtr); RS_Reset_RX_Flags(_hRS_); RS_Reset_TX_Flags(_hRS_);
//#define MB_Is_RX_Busy(_hRS_) ((_hRS_->huart->gState&HAL_USART_STATE_BUSY_RX) == HAL_USART_STATE_BUSY_RX)
//#define MB_Is_TX_Busy(_hRS_) ((_hRS_->huart->gState&HAL_USART_STATE_BUSY_RX) == HAL_USART_STATE_BUSY_TX)
#define RS_Is_RX_Busy(_hRS_) (_hRS_->fRX_Busy == 1)
#define RS_Is_TX_Busy(_hRS_) (_hRS_->fTX_Busy == 1)
////////////////////////////---DEFINES---////////////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////---STRUCTURES & ENUMS---//////////////////////
//------------------ENUMERATIONS--------------------
/* Enums for respond CMD about RS status*/
typedef enum // RS_StatusTypeDef
{
/* IN-CODE STATUS (start from 0x01, and goes up)*/
/*0x01*/ RS_OK = 0x01,
/*0x02*/ RS_ERR,
/*0x03*/ RS_ABORTED,
/*0x04*/ RS_BUSY,
/*0x05*/ RS_SKIP,
/*0x06*/ RS_COLLECT_MSG_ERR,
/*0x07*/ RS_PARSE_MSG_ERR,
// reserved values
// /*0x00*/ RS_UNKNOWN_ERR = 0x00, // reserved for case, if no one error founded (nothing changed response from zero)
}RS_StatusTypeDef;
/* Enums for RS Modes */
typedef enum // RS_ModeTypeDef
{
SLAVE_ALWAYS_WAIT = 0x01, // Slave mode with infinity waiting
SLAVE_TIMEOUT_WAIT = 0x02, // Slave mode with waiting with timeout
// MASTER = 0x03, // Master mode
}RS_ModeTypeDef;
/* Enums for RS UART Modes */
typedef enum // RS_ITModeTypeDef
{
BLCK_MODE = 0x00, // Blocking mode
IT_MODE = 0x01, // Interrupt mode
}RS_ITModeTypeDef;
/* Enums for Abort modes */
typedef enum // RS_AbortTypeDef
{
ABORT_TX = 0x01, // Abort transmit
ABORT_RX = 0x02, // Abort receive
ABORT_RX_TX = 0x03, // Abort receive and transmit
ABORT_RS = 0x04, // Abort uart and reset RS structure
}RS_AbortTypeDef;
/* Enums for RX Size modes */
typedef enum // RS_RXSizeTypeDef
{
RS_RX_Size_Const = 0x01, // size of receiving message is constant
RS_RX_Size_NotConst = 0x02, // size of receiving message isnt constant
}RS_RXSizeTypeDef;
//-----------STRUCTURE FOR HANDLE RS------------
/**
* @brief Handle for RS communication.
* @note Prefixes: h - handle, s - settings, f - flag
*/
typedef struct // RS_HandleTypeDef
{
/* MESSAGE */
uint8_t ID; // ID of RS "channel"
RS_MsgTypeDef *pMessagePtr; // pointer to message struct
uint8_t *pBufferPtr; // pointer to message buffer
uint32_t RS_Message_Size; // size of whole message, not only data
/* HANDLERS and SETTINGS */
UART_HandleTypeDef *huart; // handler for used uart
TIM_HandleTypeDef *htim; // handler for used tim
RS_ModeTypeDef sRS_Mode; // setting: slave or master @ref RS_ModeTypeDef
RS_ITModeTypeDef sRS_IT_Mode; // setting: 1 - IT mode, 0 - Blocking mode
uint16_t sRS_Timeout; // setting: timeout in ms
RS_RXSizeTypeDef sRS_RX_Size_Mode; // setting: 1 - not const, 0 - const
/* FLAGS */
// These flags for controling receive/transmit
unsigned fRX_Half:1; // flag: 0 - receiving msg before ByteCnt, 0 - receiving msg after ByteCnt
unsigned fRS_Busy:1; // flag: 1 - RS is busy, 0 - RS isnt busy
unsigned fRX_Busy:1; // flag: 1 - receiving is active, 0 - receiving isnt active
unsigned fTX_Busy:1; // flag: 1 - transmiting is active, 0 - transmiting isnt active
unsigned fRX_Done:1; // flag: 1 - receiving is done, 0 - receiving isnt done
unsigned fTX_Done:1; // flag: 1 - transmiting is done, 0 - transmiting isnt done
// setted by user
unsigned fMessageHandled:1; // flag: 1 - RS command is handled, 0 - RS command isnt handled yet
unsigned fEchoResponse:1; // flag: 1 - response with received msg, 0 - response with own msg
unsigned fDeferredResponse:1; // flag: 1 - response not in interrupt, 0 - response in interrupt
unsigned fReInit_UART:1; // flag: 1 - need to reinitialize uart, 0 - nothing
/* RS STATUS */
RS_StatusTypeDef RS_STATUS; // RS status
}RS_HandleTypeDef;
///////////////////////---STRUCTURES & ENUMS---//////////////////////
/////////////////////////////////////////////////////////////////////
///////////////////////////---FUNCTIONS---///////////////////////////
//----------------FUNCTIONS FOR PROCESSING MESSAGE-------------------
/*--------------------Defined by users purposes--------------------*/
/**
* @brief Respond accord to received message.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о результате ответа на комманду.
* @note Обработка принятой комманды и ответ на неё.
*/
RS_StatusTypeDef RS_Response(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg);
/**
* @brief Collect message in buffer to transmit it.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @param msg_uart_buff - указатель на буффер UART.
* @return RS_RES - статус о результате заполнения буфера.
* @note Заполнение буффера UART из структуры сообщения.
*/
RS_StatusTypeDef Collect_Message(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg, uint8_t *msg_uart_buff);
/**
* @brief Parse message from buffer to process it.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @param msg_uart_buff - указатель на буффер UART.
* @return RS_RES - статус о результате заполнения структуры.
* @note Заполнение структуры сообщения из буффера UART.
*/
RS_StatusTypeDef Parse_Message(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg, uint8_t *msg_uart_buff);
/**
* @brief Define size of RX Message that need to be received.
* @param hRS - указатель на хендлер RS.
* @param rx_data_size - указатель на переменную для записи кол-ва байт для принятия.
* @return RS_RES - статус о корректности рассчета кол-ва байт для принятия.
* @note Определение сколько байтов надо принять по протоколу.
*/
RS_StatusTypeDef RS_Define_Size_of_RX_Message(RS_HandleTypeDef *hRS, uint32_t *rx_data_size);
//-------------------------GENERAL FUNCTIONS-------------------------
/*-----------------Should be called from main code-----------------*/
/**
* @brief Start receive IT.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации приема.
*/
RS_StatusTypeDef RS_Receive_IT(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg);
/**
* @brief Start transmit IT.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации передачи.
*/
RS_StatusTypeDef RS_Transmit_IT(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg);
/**
* @brief Initialize UART and handle RS stucture.
* @param hRS - указатель на хендлер RS.
* @param suart - указатель на структуру с настройками UART.
* @param stim - указатель на структуру с настройками таймера.
* @param pRS_BufferPtr - указатель на буффер для приема-передачи по UART. Если он NULL, то поставиться библиотечный буфер.
* @return RS_RES - статус о состоянии RS после инициализации.
*/
RS_StatusTypeDef RS_Init(RS_HandleTypeDef *hRS, UART_SettingsTypeDef *suart, TIM_SettingsTypeDef *stim, uint8_t *pRS_BufferPtr);
/**
* @brief ReInitialize UART and RS receive.
* @param hRS - указатель на хендлер RS.
* @param suart - указатель на структуру с настройками UART.
* @return RS_RES - статус о состоянии RS после инициализации.
*/
HAL_StatusTypeDef RS_ReInit_UART(RS_HandleTypeDef *hRS, UART_SettingsTypeDef *suart);
/**
* @brief Abort RS/UART.
* @param hRS - указатель на хендлер RS.
* @param AbortMode - выбор, что надо отменить.
- ABORT_TX: Отмена передачи по ЮАРТ, с очищением флагов TX,
- ABORT_RX: Отмена приема по ЮАРТ, с очищением флагов RX,
- ABORT_RX_TX: Отмена приема и передачи по ЮАРТ,
- ABORT_RS: Отмена приема-передачи RS, с очищением всей структуры.
* @return RS_RES - статус о состоянии RS после аборта.
* @note Отмена работы UART в целом или отмена приема/передачи RS.
Также очищается хендл hRS.
*/
RS_StatusTypeDef RS_Abort(RS_HandleTypeDef *hRS, RS_AbortTypeDef AbortMode);
//-------------------------GENERAL FUNCTIONS-------------------------
//-------------------------------------------------------------------
//--------------------CALLBACK/HANDLER FUNCTIONS---------------------
/**
* @brief Handle for starting receive.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации приема или окончания общения.
* @note Определяет начинать прием команды/ответа или нет.
*/
RS_StatusTypeDef RS_Handle_Receive_Start(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg);
/**
* @brief Handle for starting transmit.
* @param hRS - указатель на хендлер RS.
* @param RS_msg - указатель на структуру сообщения.
* @return RS_RES - статус о состоянии RS после инициализации передачи.
* @note Определяет отвечать ли на команду или нет.
*/
RS_StatusTypeDef RS_Handle_Transmit_Start(RS_HandleTypeDef *hRS, RS_MsgTypeDef *RS_msg);
/**
* @brief UART RX Callback: define behaviour after receiving parts of message.
* @param hRS - указатель на хендлер RS.
* @return RS_RES - статус о состоянии RS после обработки приема.
* @note Контролирует прием сообщения: определяет размер принимаемой посылки и обрабатывает его.
*/
RS_StatusTypeDef RS_UART_RxCpltCallback(RS_HandleTypeDef *hRS);
/**
* @brief UART TX Callback: define behaviour after transmiting message.
* @param hRS - указатель на хендлер RS.
* @return RS_RES - статус о состоянии RS после обработки приема.
* @note Определяет поведение RS после передачи сообщения.
*/
RS_StatusTypeDef RS_UART_TxCpltCallback(RS_HandleTypeDef *hRS);
/**
* @brief Handler for UART.
* @param hRS - указатель на хендлер RS.
* @note Обрабатывает ошибки если есть и вызывает RS Коллбеки.
* Добавить вызов этой функции в UARTx_IRQHandler().
*/
void RS_UART_Handler(RS_HandleTypeDef *hRS);
/**
* @brief Handler for TIM.
* @param hRS - указатель на хендлер RS.
* @note Попадание сюда = таймаут и перезапуск RS приема
* Добавить вызов этой функции в TIMx_IRQHandler().
*/
void RS_TIM_Handler(RS_HandleTypeDef *hRS);
//--------------------CALLBACK/HANDLER FUNCTIONS---------------------
///////////////////////////---FUNCTIONS---///////////////////////////
#endif // __RS_LIB_H_

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Code/PWM/control.c
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@@ -1,240 +0,0 @@
#include "pwm.h"
TIM_SettingsTypeDef TIM_CTRL = {0};
// variables for filling arrays
int Numb_Of_Peroids = 2; // number of periods
int Samples_Per_Peroid = 0; // how many samples in one period
int Size_Of_Log = 0; // size of written data to log
int log_ind = 0; // index of log arrays
int cnt_to_cnt_log = 0; // counter for log_cnt
int sine_ind_prev = 0;
/**
* @brief Filling logs.
* @note Заполнение логов: синус, шим, пила.
* @note This called from TIM_CTRL_Handler
*/
void Fill_Logs_with_Data(void)
{
// calc pwm duty from timer
float PWM_Duty;
if(PWM_Get_Mode(&hpwm1, PWM_DC_MODE) == 0) // if sinus need to be written
{
if(PWM_Get_Mode(&hpwm1, PWM_CH_MODE)) // if its signed sine mode (two channels)
{
if(hpwm1.Duty_Table_Ind < hpwm1.Duty_Table_Size/2) // first half get from channel 1
PWM_Duty = (((float)PWM_Get_Compare1(&hpwm1))/(PWM_Get_Autoreload(&hpwm1)))+1;
else // second half get from channel 2
PWM_Duty = 1-(((float)PWM_Get_Compare2(&hpwm1))/(PWM_Get_Autoreload(&hpwm1)));
}
else // if its unsigned sine mode (single channel)
{ // just get current pwm duty
PWM_Duty = ((float)PWM_Get_Compare1(&hpwm1)/PWM_Get_Autoreload(&hpwm1));
}
}
else // if its dc pwm mode
{ // just get current pwm duty
if(PWM_Get_Mode(&hpwm1, PWM_CH_MODE)) // if its second channels mode
PWM_Duty = ((float)PWM_Get_Compare2(&hpwm1)/PWM_Get_Autoreload(&hpwm1));
else // if its first channel mode
PWM_Duty = ((float)PWM_Get_Compare1(&hpwm1)/PWM_Get_Autoreload(&hpwm1));
}
// WRITE SINUS TO WHOLE ARRAY
// sine_log[log_ind] = sin_val;
if(PWM_Get_Mode(&hpwm1,PWM_DC_MODE) == 0) // in table mode write PWM Duty (write sine) with scale 1/2 from sin table max value (0xFFFF/2)
sine_log[log_ind] = PWM_Duty*(0x8000-1);
else // in dc mode write PWM Duty (write sine)
sine_log[log_ind] = 0;
// WRITE PWM
if(PWM_Get_Mode(&hpwm1,PWM_DC_MODE)) // in DC mode
{
// write 1 - if log_ind < Size_Of_Period*PWM_Dury
// write 0 - otherwise
pwm_log[log_ind] = (log_ind%(Size_Of_Log/Numb_Of_Peroids) < (Size_Of_Log/Numb_Of_Peroids+1)*hpwm1.PWM_Value/100)? 1: 0;
}
else // in table mode
{
// write fill whole pwm array at one interrupt
int PWM_Period_End_Ind = (Size_Of_Log/Numb_Of_Peroids);
int PWM_Step_End_Ind;
if(PWM_Get_Mode(&hpwm1,PWM_CH_MODE))
PWM_Step_End_Ind = PWM_Period_End_Ind*fabs(PWM_Duty-1);
else
PWM_Step_End_Ind = PWM_Period_End_Ind*PWM_Duty;
for(int i = 0; i <= PWM_Step_End_Ind; i++)
{
for (int j = 0; j < Numb_Of_Peroids; j++)
pwm_log[i+j*PWM_Period_End_Ind] = 1;
}
for(int i = PWM_Step_End_Ind+1; i < PWM_Period_End_Ind; i++)
for (int j = 0; j < Numb_Of_Peroids; j++)
pwm_log[i+j*PWM_Period_End_Ind] = 0;
}
// WRITE COUNTER
cnt_log[log_ind] = cnt_to_cnt_log;
cnt_to_cnt_log++;
if(cnt_to_cnt_log>=Size_Of_Log/2)
cnt_to_cnt_log = 0;
// INCREMENT AND RESET COUNTER
log_ind++;
if(PWM_Get_Mode(&hpwm1,PWM_DC_MODE) == 0) // if its PWM table mode
{
// SYNCHRONIZE PERIOD OF SIN IN LOG
// (это надо, чтобы данные не съезжали из-за несинхронизированного периода)
// wait until period ended
if(log_ind>Size_Of_Log-1) // if logs are filled
{
if((unsigned)hpwm1.Duty_Table_Ind < sine_ind_prev) // and if new period started
{
log_ind = 0; // reset counter
sine_ind_prev = (unsigned)hpwm1.Duty_Table_Ind;
}
}
// update prev variable only if log currently writing
else
sine_ind_prev = (unsigned)hpwm1.Duty_Table_Ind;
}
else // if its PWM DC mode
{
// if logs are filled
if(log_ind>Size_Of_Log-1)
log_ind = 0;
}
// if its overflow log array size - reset log_ind
if(log_ind>LOG_SIZE-1)
{
log_ind = 0;
sine_ind_prev = (unsigned)hpwm1.Duty_Table_Ind;
}
}
/**
* @brief Update log parameters.
* @note Проверка надо ли обновлять параметры логов, и если надо - обновляет их.
* @note This called from TIM_CTRL_Handler
*/
void Update_Params_For_Log(void)
{
unsigned UpdateLog = 0;
// READ NUMB OF PERIOD IN LOGS
if(Numb_Of_Peroids != log_ctrl[R_LOG_CTRL_LOG_PWM_NUMB])
{
Numb_Of_Peroids = log_ctrl[R_LOG_CTRL_LOG_PWM_NUMB];
// update logs params
UpdateLog = 1;
}
// READ SIZE OF LOGS
if(Size_Of_Log != log_ctrl[R_LOG_CTRL_LOG_SIZE])
{
Size_Of_Log = log_ctrl[R_LOG_CTRL_LOG_SIZE];
// update logs params
UpdateLog = 1;
}
// UPDATE LOG PARAMS
if(UpdateLog)
{
// set logs params
Set_Log_Params();
}
}
/**
* @brief Set up log parameters.
* @note Устанавливает настройки логов и проверяет их на корректность.
*/
void Set_Log_Params(void)
{
// SET LOG PARAMS
log_ind = 0;
Samples_Per_Peroid = TIM_CTRL.sTimFreqHz/hpwm1.PWM_Value;
if(Size_Of_Log > LOG_SIZE) // if its too much data in log
{
Numb_Of_Peroids = (LOG_SIZE/Samples_Per_Peroid);
log_ctrl[R_LOG_CTRL_LOG_SIZE] = Numb_Of_Peroids;
Size_Of_Log = Numb_Of_Peroids*Samples_Per_Peroid;
}
// clear logs arrays
for(int i = Size_Of_Log; i < LOG_SIZE; i++)
{
sine_log[i] = 0;
pwm_log[i] = 0;
cnt_log[i] = 0;
}
}
/**
* @brief reInitialization of control timer.
* @note Перенастраивает таймер согласно принятным настройкам в log_ctrl.
* @note This called from main while
*/
void Control_Timer_ReInit(TIM_SettingsTypeDef *stim)
{
TIM_Base_MspDeInit(&stim->htim);
hpwm1.stim.sTickBaseMHz = PROJSET.TIM_CTRL_TICKBASE;
TIM_Base_Init(stim);
HAL_TIM_Base_Start_IT(&stim->htim); // timer for sinus
HAL_NVIC_SetPriority(TIM8_BRK_TIM12_IRQn, 1, 1);
}
/**
* @brief First initialization of Control Timer.
* @note Первый управляющего таймера. Таймер записывает логи и обновляет параметры ШИМ.
* @note This called from main
*/
void Control_Timer_FirstInit(void)
{
//-------CONTROL TIMER INIT----------
// tim settings
TIM_CTRL.htim.Instance = TIM12;
TIM_CTRL.sTimMode = TIM_IT_MODE;
TIM_CTRL.sTickBaseMHz = PROJSET.TIM_CTRL_TICKBASE;
TIM_CTRL.sTimAHBFreqMHz = PROJSET.TIM_CTRL_AHB_FREQ;
TIM_CTRL.sTimFreqHz = HZ_TIMER_CTRL;
TIM_Base_Init(&TIM_CTRL);
HAL_NVIC_SetPriority(TIM8_BRK_TIM12_IRQn, 1, 1);
HAL_TIM_Base_Start_IT(&TIM_CTRL.htim); // timer for sinus
// FILL TIME ARRAY WITH TIME
for(int i = 0; i <= R_TIME_LOG_QNT; i++)
time_log[i] = i;
}
//-------------------------------------------------------------------
//------------------------HANDLERS FUNCTIONS-------------------------
//-------------CONTROL TIMER---------------
void TIM8_BRK_TIM12_IRQHandler(void)
{
Trace_CTRL_TIM_Enter();
HAL_TIM_IRQHandler(&TIM_CTRL.htim);
Fill_Logs_with_Data();
Update_Params_For_Log();
Update_Params_For_PWM(&hpwm1);
WriteSettingsToMem();
Trace_CTRL_TIM_Exit();
}

48
Code/PWM/control.h
View File

@@ -1,48 +0,0 @@
#ifndef __CONTROL_H_
#define __CONTROL_H_
#include "periph_general.h"
#include "modbus.h"
#include "math.h"
#include "settings.h"
#define M_PI 3.14159265358979323846 /* pi */
extern TIM_SettingsTypeDef TIM_CTRL;
//---------------------this called from TIM_CTRL_Handler()-----------------------
/**
* @brief Update log parameters.
* @note Проверка надо ли обновлять параметры логов, и если надо - обновляет их.
* @note This called from TIM_CTRL_Handler
*/
void Update_Params_For_Log(void);
/**
* @brief Filling logs.
* @note заполнение логов: синус, шим, пила.
* @note this called from TIM_CTRL_Handler
*/
void Fill_Logs_with_Data(void);
/**
* @brief Set up log parameters.
* @note Устанавливает настройки логов и проверяет их на корректность.
*/
void Set_Log_Params(void);
/**
* @brief First initialization of Control Timer.
* @note Первый управляющего таймера. Таймер записывает логи и обновляет параметры ШИМ.
* @note This called from main
*/
void Control_Timer_FirstInit(void);
// this called from main while(1)
/**
* @brief reInitialization of control timer.
* @param stim - указатель на настройки таймера.
* @note Перенастраивает таймер согласно принятным настройкам в log_ctrl.
* @note This called from main while
*/
void Control_Timer_ReInit(TIM_SettingsTypeDef *stim);
#endif // __CONTROL_H_

855
Code/PWM/pwm.c
View File

@@ -1,855 +0,0 @@
#include "pwm.h"
//#include "rng.h"
PWM_HandleTypeDef hpwm1;
PWM_SlaveHandleTypeDef hpwm2;
PWM_SlaveHandleTypeDef hpwm3;
uint32_t sin_table[SIN_TABLE_SIZE_MAX];
unsigned ActiveChannelSHDW_Master;
float DeadTimeCnt_Master;
unsigned ActiveChannelSHDW_Slave2;
float DeadTimeCnt_Slave2;
unsigned ActiveChannelSHDW_Slave3;
float DeadTimeCnt_Slave3;
/**
* @brief First set up of PWM.
* @note Первый инит ШИМ. Заполняет структуры и инициализирует таймер для генерации синуоидального ШИМ.
* Скважность ШИМ меняется по закону синусоиды, каждый канал генерирует свой полупериод синуса (от -1 до 0 И от 0 до 1)
* ШИМ генерируется на одном канале.
* @note This called from main
*/
void PWM_Sine_FirstInit(void)
{
hpwm1.pDuty_Table_Origin = SIN_TABLE_ORIGIN;
//---------PWM TIMER1 INIT------------
// channels settings
hpwm1.sConfigOC.OCMode = TIM_OCMODE_PWM1;
hpwm1.sConfigOC.Pulse = 0;
hpwm1.sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
hpwm1.sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
// tim1 settings
hpwm1.stim.htim.Instance = TIMER_PWM1_INSTANCE;
hpwm1.stim.sTimMode = TIM_IT_MODE;
hpwm1.stim.sTimFreqHz = HZ_TIMER_PWM;
hpwm1.stim.sTickBaseMHz = PROJSET.TIM_PWM_TICKBASE;
hpwm1.stim.sTimAHBFreqMHz = PROJSET.TIM_PWM_AHB_FREQ;
hpwm1.GPIOx = TIMER_PWM1_GPIOx;
hpwm1.GPIO_PIN_X1 = PROJSET.TIM_PWM1_GPIO_PIN_X1;
hpwm1.GPIO_PIN_X2 = PROJSET.TIM_PWM1_GPIO_PIN_X2;
hpwm1.PWM_Channel1 = PROJSET.TIM_PWM1_TIM_CHANNEL1;
hpwm1.PWM_Channel2 = PROJSET.TIM_PWM1_TIM_CHANNEL2;
hpwm1.hpwm2 = (void *)&hpwm2;
hpwm1.hpwm3 = (void *)&hpwm3;
TIM_Base_Init(&hpwm1.stim);
TIM_Output_PWM_Init(&hpwm1.stim.htim, &hpwm1.sConfigOC, hpwm1.PWM_Channel1, hpwm1.GPIOx, hpwm1.GPIO_PIN_X1);
TIM_Output_PWM_Init(&hpwm1.stim.htim, &hpwm1.sConfigOC, hpwm1.PWM_Channel2, hpwm1.GPIOx, hpwm1.GPIO_PIN_X2);
// PWM SLAVES INIT
hpwm2.hMasterPWM = &hpwm1;
hpwm2.stim = hpwm1.stim;
hpwm2.stim.htim.Instance = (TIM_TypeDef *)PROJSET.TIM_PWM2_INSTANCE;
hpwm2.GPIOx = (GPIO_TypeDef *)PROJSET.TIM_PWM2_GPIOx;
hpwm2.GPIO_PIN_X1 = PROJSET.TIM_PWM2_GPIO_PIN_X1;
hpwm2.GPIO_PIN_X2 = PROJSET.TIM_PWM2_GPIO_PIN_X2;
hpwm2.PWM_Channel1 = PROJSET.TIM_PWM2_TIM_CHANNEL1;
hpwm2.PWM_Channel2 = PROJSET.TIM_PWM2_TIM_CHANNEL2;
hpwm2.Duty_Shift_Ratio = (float)2/3;
hpwm3.hMasterPWM = &hpwm1;
hpwm3.stim = hpwm1.stim;
hpwm3.stim.htim.Instance = (TIM_TypeDef *)PROJSET.TIM_PWM3_INSTANCE;
hpwm3.GPIOx = (GPIO_TypeDef *)PROJSET.TIM_PWM3_GPIOx;
hpwm3.GPIO_PIN_X1 = PROJSET.TIM_PWM3_GPIO_PIN_X1;
hpwm3.GPIO_PIN_X2 = PROJSET.TIM_PWM3_GPIO_PIN_X2;
hpwm3.PWM_Channel1 = PROJSET.TIM_PWM3_TIM_CHANNEL1;
hpwm3.PWM_Channel2 = PROJSET.TIM_PWM3_TIM_CHANNEL2;
hpwm3.Duty_Shift_Ratio = (float)-2/3;
PWM_SlavePhase_Init(&hpwm2);
PWM_SlavePhase_Init(&hpwm3);
//----------TIMERS START-------------
HAL_TIM_Base_Start_IT(&hpwm1.stim.htim); // timer for PWM
HAL_TIM_PWM_Start(&hpwm1.stim.htim, hpwm1.PWM_Channel1); // PWM channel 1
HAL_TIM_PWM_Start(&hpwm1.stim.htim, hpwm1.PWM_Channel2); // PWM channel 2
}
/**
* @brief PWM Handler.
* @param hpwm - указатель на хендл ШИМ.
* @note Управляет скважностью ШИМ.
* @note This called from TIM_PWM_Handler
*/
void PWM_Handler(PWM_HandleTypeDef *hpwm)
{
//------------SINUS MODE-------------
if(PWM_Get_Mode(&hpwm1,PWM_DC_MODE) == 0)
{
if(hpwm->PWM_Value != 0) // if there some frequency
{
unsigned sin_ind = PWM_Get_Duty_Table_Ind(hpwm, hpwm->stim.sTimFreqHz);
// overflow check
if(sin_ind >= hpwm->Duty_Table_Size)
sin_ind -= hpwm->Duty_Table_Size;
if(sin_ind >= hpwm->Duty_Table_Size) // if its still overflow reset it
sin_ind = 0;
// if unsigned sine enabled
if(PWM_Get_Mode(hpwm, PWM_CH_MODE) == 0)
{
// set pwm duty
PWM_Set_Duty_From_Table(hpwm, sin_ind); // set first channel
PWM_SlavePhase_Set_DutyTable_Unsigned(PWM_Set_pSlaveHandle(hpwm,hpwm2), sin_ind);
PWM_SlavePhase_Set_DutyTable_Unsigned(PWM_Set_pSlaveHandle(hpwm,hpwm3), sin_ind);
}
// if signed sine enabled
else
{
int Duty = PWM_Get_Table_Element_Signed(hpwm, sin_ind);
if(Duty >= 0)
{
PWM_Set_Compare1(hpwm, Duty); // set first channel
PWM_Set_Compare2(hpwm, 0); // reset second channel
}
else // если это вторая полуволна
{
PWM_Set_Compare1(hpwm, 0); // reset first channel
PWM_Set_Compare2(hpwm, -Duty); // set second channel
}
PWM_SlavePhase_Set_DutyTable_Signed(PWM_Set_pSlaveHandle(hpwm,hpwm2), sin_ind);
PWM_SlavePhase_Set_DutyTable_Signed(PWM_Set_pSlaveHandle(hpwm,hpwm3), sin_ind);
}
}
else // if freq = 0 reset all channels
{
PWM_Set_Compare1(hpwm, 0); // reset first channel
PWM_Set_Compare2(hpwm, 0); // reset second channel
PWM_Set_Compare1(PWM_Set_pSlaveHandle(hpwm,hpwm2), 0); // reset first channel
PWM_Set_Compare2(PWM_Set_pSlaveHandle(hpwm,hpwm2), 0); // reset second channel
PWM_Set_Compare1(PWM_Set_pSlaveHandle(hpwm,hpwm3), 0); // reset first channel
PWM_Set_Compare2(PWM_Set_pSlaveHandle(hpwm,hpwm3), 0); // reset second channel
}
}
//-----------PWM DC MODE-------------
else
{
PWM_Set_Compare1(PWM_Set_pSlaveHandle(hpwm,hpwm2), 0); // reset first channel
PWM_Set_Compare2(PWM_Set_pSlaveHandle(hpwm,hpwm2), 0); // reset second channel
PWM_Set_Compare1(PWM_Set_pSlaveHandle(hpwm,hpwm3), 0); // reset first channel
PWM_Set_Compare2(PWM_Set_pSlaveHandle(hpwm,hpwm3), 0); // reset second channel
// uint32_t pwm_rng = 0;
// HAL_RNG_GenerateRandomNumber(&hrng, &pwm_rng);
// pwm_rng = ((pwm_rng&0xFFFF)/(0xFFFF/PWM_Get_Autoreload(hpwm)))/((float)100/hpwm->PWM_Value);
// if (pwm_rng < PWM_Calc_Min_Duty(hpwm))
// pwm_rng = PWM_Calc_Min_Duty(hpwm);
// if second channel enabled
if(PWM_Get_Mode(hpwm, PWM_CH_MODE))
{
PWM_Set_Compare1(hpwm, 0); // reset first channel
PWM_Set_Duty_From_Percent(hpwm, hpwm->PWM_Channel2); // set second channel
// __HAL_TIM_SET_COMPARE(&(hpwm->stim.htim), TIM_CHANNEL_2, pwm_rng); // set second channel
}
// if first channel enabled
else
{
// __HAL_TIM_SET_COMPARE(&(hpwm->stim.htim), TIM_CHANNEL_1, pwm_rng); // set second channel
PWM_Set_Duty_From_Percent(hpwm, hpwm->PWM_Channel1); // set first channel
PWM_Set_Compare2(hpwm, 0); // reset second channel
}
}
//-----CHECK CHANNELS FOR ERRORS-----
uint16_t min_duty = PWM_Calc_Min_Duty(hpwm);
// IF FIRST CHANNEL IS ACRIVE
if(PWM_Get_Compare1(hpwm) != 0)
{
// Duty shoud be bigger or equeal than min duration
if (PWM_Get_Compare1(hpwm)<min_duty)
PWM_Set_Compare1(hpwm, min_duty);
// Duty shoud be less or equeal than ARR-min duration
if (PWM_Get_Compare1(hpwm)>PWM_Get_Autoreload(hpwm)-min_duty)
PWM_Set_Compare1(hpwm, PWM_Get_Autoreload(hpwm)-min_duty);
}
// IF SECOND CHANNEL IS ACRIVE
else if(PWM_Get_Compare2(hpwm) != 0)
{
// Duty shoud be bigger or equeal than min duration
if (PWM_Get_Compare2(hpwm)<min_duty)
PWM_Set_Compare2(hpwm, min_duty);
// Duty shoud be less or equeal than ARR
if (PWM_Get_Compare2(hpwm)>PWM_Get_Autoreload(hpwm)-min_duty)
PWM_Set_Compare2(hpwm, PWM_Get_Autoreload(hpwm)-min_duty);
}
// IF BOTH CHANNEL IS ACRIVE
if((PWM_Get_Compare1(hpwm) != 0) && (PWM_Get_Compare2(hpwm) != 0))
{
// Only one channel shoud be active so disable all
PWM_Set_Compare1(hpwm, 0);
PWM_Set_Compare2(hpwm, 0);
}
PWM_SlavePhase_Check_Channels(PWM_Set_pSlaveHandle(hpwm,hpwm2));
PWM_SlavePhase_Check_Channels(PWM_Set_pSlaveHandle(hpwm,hpwm3));
if(hpwm->PWM_DeadTime)
{
PWM_CreateDeadTime(hpwm, &DeadTimeCnt_Master, &ActiveChannelSHDW_Master);
PWM_SlavePhase_CreateDeadTime(PWM_Set_pSlaveHandle(hpwm,hpwm2), &DeadTimeCnt_Slave2, &ActiveChannelSHDW_Slave2);
PWM_SlavePhase_CreateDeadTime(PWM_Set_pSlaveHandle(hpwm,hpwm3), &DeadTimeCnt_Slave3, &ActiveChannelSHDW_Slave3);
}
}
/**
* @brief Update PWM parameters.
* @note Проверка надо ли обновлять параметры ШИМ, и если надо - обновляет их.
* @note This called from TIM_CTRL_Handler
*/
void Update_Params_For_PWM(PWM_HandleTypeDef *hpwm)
{
unsigned UpdateModeParams = 0;
unsigned UpdateLog = 0;
// READ PWM_DC_MODE
if(PWM_Get_Mode(hpwm, PWM_DC_MODE) != (MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_DC_MODE) << PWM_DC_MODE_Pos))
{
if(MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_DC_MODE))
{
hpwm->sPWM_Mode |= PWM_DC_MODE;
}
else
{
hpwm->sPWM_Mode &= ~PWM_DC_MODE;
}
// update mode params
UpdateModeParams = 1;
// update logs params
UpdateLog = 1;
}
// READ PWM_CH_MODE
if(PWM_Get_Mode(hpwm, PWM_CH_MODE) != (MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_CH_MODE) << PWM_CH_MODE_Pos))
{
if(MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_CH_MODE))
{
hpwm->sPWM_Mode |= PWM_CH_MODE;
}
else
{
hpwm->sPWM_Mode &= ~PWM_CH_MODE;
}
// update mode params
UpdateModeParams = 1;
// update logs params
UpdateLog = 1;
}
// READ PWM_CH_MODE
if(PWM_Get_Mode(hpwm, PWM_PHASE_MODE) != (MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_PHASE_MODE) << PWM_PHASE_MODE_Pos))
{
if(MB_Read_Coil_Local(&coils_regs[0], COIL_PWM_PHASE_MODE))
{
hpwm->sPWM_Mode |= PWM_PHASE_MODE;
}
else
{
hpwm->sPWM_Mode &= ~PWM_PHASE_MODE;
}
// update mode params
UpdateModeParams = 1;
// update logs params
UpdateLog = 1;
}
// READ PWM_VALUE
if(hpwm->PWM_Value != int_to_percent(pwm_ctrl[R_PWM_CTRL_PWM_VALUE]))
{
hpwm->PWM_Value = int_to_percent(pwm_ctrl[R_PWM_CTRL_PWM_VALUE]);
// update logs params
UpdateLog = 1;
}
// READ TABLE_SIZE
if(hpwm->Duty_Table_Size != pwm_ctrl[R_PWM_CTRL_SIN_TABLE_SIZE])
{
hpwm->Duty_Table_Size = PWM_Fill_Sine_Table(&hpwm1, pwm_ctrl[R_PWM_CTRL_SIN_TABLE_SIZE]);
pwm_ctrl[R_PWM_CTRL_SIN_TABLE_SIZE] = hpwm->Duty_Table_Size;
}
// READ MIN PULSE DURATION
if(hpwm->PWM_MinPulseDur != pwm_ctrl[R_PWM_CTRL_MIN_PULSE_DUR])
{
hpwm->PWM_MinPulseDur = pwm_ctrl[R_PWM_CTRL_MIN_PULSE_DUR];
// update mode params
UpdateModeParams = 1;
// update logs params
UpdateLog = 1;
}
// READ DEAD TIME
if(hpwm->PWM_DeadTime != pwm_ctrl[R_PWM_CTRL_DEAD_TIME])
{
hpwm->PWM_DeadTime = pwm_ctrl[R_PWM_CTRL_DEAD_TIME];
}
// UPDATE PWM PARAMS
if(UpdateModeParams)
{
// UPDATE DUTY TABLE SCALE
PWM_Update_DutyTableScale(hpwm);
// update logs params
UpdateLog = 1;
}
// UPDATE LOG PARAMS
if(UpdateLog)
{
// set logs params
Set_Log_Params();
}
}
/**
* @brief reInitialization of PWM TIM.
* @param hpwm - указатель на хендл ШИМ.
* @note Перенастраивает таймер согласно принятным настройкам в pwm_ctrl
* ШИМ генерируется на одном канале.
*/
void PWM_Sine_ReInit(PWM_HandleTypeDef *hpwm)
{
Trace_PWM_reInit_Enter();
TIM_Base_MspDeInit(&hpwm->stim.htim);
hpwm1.stim.sTickBaseMHz = TIMER_PWM_TICKBASE;
TIM_Base_Init(&hpwm->stim);
TIM_Output_PWM_Init(&hpwm->stim.htim, &hpwm->sConfigOC, hpwm->PWM_Channel1, hpwm->GPIOx, hpwm->GPIO_PIN_X1);
TIM_Output_PWM_Init(&hpwm->stim.htim, &hpwm->sConfigOC, hpwm->PWM_Channel2, hpwm->GPIOx, hpwm->GPIO_PIN_X2);
PWM_Update_DutyTableScale(hpwm);
//----------TIMERS START-------------
HAL_TIM_Base_Start_IT(&hpwm1.stim.htim); // timer for PWM
HAL_TIM_PWM_Start(&hpwm1.stim.htim, hpwm->PWM_Channel1); // PWM channel 1
HAL_TIM_PWM_Start(&hpwm1.stim.htim, hpwm->PWM_Channel2); // PWM channel 2
Trace_PWM_reInit_Exit();
}
/**
* @brief Getting ind for Duty Table.
* @param hpwm - указатель на хендл ШИМ.
* @param FreqTIM - частота таймера ШИМ.
* @note Рассчитывает индекс для таблицы скважностей.
* PWM_Value в hpwm - частота с которой эта таблица должна выводиться на ШИМ
* @note This called from TIM_PWM_Handler
*/
uint32_t PWM_Get_Duty_Table_Ind(PWM_HandleTypeDef *hpwm, float FreqTIM)
{
float sine_ind_step;
uint32_t sine_ind;
// calc ind for sin table
sine_ind_step = hpwm->Duty_Table_Size/(FreqTIM/hpwm->PWM_Value);
hpwm->Duty_Table_Ind += sine_ind_step;
if(hpwm->Duty_Table_Ind >= hpwm->Duty_Table_Size)
hpwm->Duty_Table_Ind -= hpwm->Duty_Table_Size;
// if its too big (e.g. inf)
if(hpwm->Duty_Table_Ind >= 0xFFFF)
hpwm->Duty_Table_Ind = 0;
return hpwm->Duty_Table_Ind;
}
/**
* @brief Create Dead Time when switches channels.
* @param hpwm - указатель на хендл ШИМ.
*/
void PWM_CreateDeadTime(PWM_HandleTypeDef *hpwm, float *LocalDeadTimeCnt, unsigned *LocalActiveChannel)
{
// get current active channel
hpwm->fActiveChannel = (PWM_Get_Compare2(hpwm) != 0); // if channel two is active - write 1, otherwise - 0
// when channels are swithed and no dead time currently active
if(*LocalActiveChannel != hpwm->fActiveChannel)
{ // update active channel
*LocalActiveChannel = hpwm->fActiveChannel;
// set deadtime
*LocalDeadTimeCnt = hpwm->PWM_DeadTime;
Trace_PWM_DeadTime_Enter();
}
// decrement dead time
*LocalDeadTimeCnt -= (PWM_Get_Autoreload(hpwm)+1)*hpwm->stim.sTickBaseMHz;
if(*LocalDeadTimeCnt > 0) // if dead time is still active
{ // reset all channels
// reset channels
PWM_Set_Compare1(hpwm, 0);
PWM_Set_Compare2(hpwm, 0);
}
else // if dead time is done
{ // set it to zero
*LocalDeadTimeCnt = 0;
Trace_PWM_DeadTime_Exit();
}
}
/**
* @brief Filling table with one period of sinus values.
* @param hpwm - указатель на хендл ШИМ.
* @param table_size - размер таблицы.
* @note Формирует таблицу синусов размером table_size.
*/
uint32_t PWM_Fill_Sine_Table(PWM_HandleTypeDef *hpwm, uint32_t table_size)
{
if((hpwm == NULL) || (hpwm->pDuty_Table_Origin == NULL) || (table_size == 0))
{
return 0;
}
if (table_size > SIN_TABLE_SIZE_MAX)
table_size = SIN_TABLE_SIZE_MAX;
hpwm->Duty_Table_Size = table_size;
float pi_step = 2*M_PI/(hpwm->Duty_Table_Size);
float pi_val = 0;
float sin_koef = 0;
uint32_t sin_val = 0;
// fill table with sinus
for(int i = 0; i < hpwm->Duty_Table_Size; i++)
{
// rotate pi
pi_val += pi_step;
// calc sin value
sin_koef = (float)0xFFFF;
sin_val = (sin(pi_val)+1)*sin_koef/2;
sin_table[i] = sin_val;
}
// fill rest of table with zeros
for(int i = hpwm->Duty_Table_Size; i < SIN_TABLE_SIZE_MAX; i++)
sin_table[i] = 0;
// if second channel is enabled
PWM_Update_DutyTableScale(hpwm);
return hpwm->Duty_Table_Size;
}
/**
* @brief Calc and update new Duty Table Scale.
* @param hpwm - указатель на хендл ШИМ.
* @note Используется, когда изменяется значение регистра ARR.
*/
void PWM_Update_DutyTableScale(PWM_HandleTypeDef *hpwm)
{
// UPDATE DUTY TABLE SCALE
if(PWM_Get_Mode(hpwm, PWM_CH_MODE)) // if second channel is enabled
{
hpwm->Duty_Table_Scale = PWM_Calc_Duty_Scale(&hpwm1, 0x8000);
}
else
{
hpwm->Duty_Table_Scale = PWM_Calc_Duty_Scale(&hpwm1, 0xFFFF);
}
// for case if min pulse dur is too big and scale is negative
if (hpwm->Duty_Table_Scale < 0)
hpwm->Duty_Table_Scale = 1;
}
//-------------------------------------------------------------------
//-----------------------THREEPHASE FUNCTIONS------------------------
/**
* @brief Initialization of Slave PWM TIM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Вызывает функции инициализации и включения слейв ШИМ.
*/
void PWM_SlavePhase_Init(PWM_SlaveHandleTypeDef *hspwm)
{
TIM_Base_Init(&hspwm->stim);
TIM_Output_PWM_Init(&hspwm->stim.htim, &hspwm->hMasterPWM->sConfigOC, hspwm->PWM_Channel1, hspwm->GPIOx, hspwm->GPIO_PIN_X1);
TIM_Output_PWM_Init(&hspwm->stim.htim, &hspwm->hMasterPWM->sConfigOC, hspwm->PWM_Channel2, hspwm->GPIOx, hspwm->GPIO_PIN_X2);
// if three phase enables
//----------TIMERS START-------------
HAL_TIM_Base_Start(&hspwm->stim.htim);
HAL_TIM_PWM_Start(&hspwm->stim.htim, hspwm->PWM_Channel1); // PWM channel 1
HAL_TIM_PWM_Start(&hspwm->stim.htim, hspwm->PWM_Channel2); // PWM channel 2
if(PWM_Get_Mode(hspwm->hMasterPWM, PWM_PHASE_MODE) == 0) // if three phase disabled
{
PWM_Set_Compare1(hspwm, 0); // reset first channel
PWM_Set_Compare2(hspwm, 0); // reset second channel
}
}
/**
* @brief reInitialization of Slave PWM TIM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Перенастраивает таймер согласно принятным настройкам в pwm_ctrl.
*/
void PWM_SlavePhase_reInit(PWM_SlaveHandleTypeDef *hspwm)
{
PWM_Slave_CopyTimSetting(hspwm, sTimFreqHz);
TIM_Base_MspDeInit(&hspwm->stim.htim);
PWM_SlavePhase_Init(hspwm);
}
/**
* @brief Set Duty from table on Slave PWM at one channel by sin_ind of the Master PWM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param sin_ind - индекс таблицы для Мастер ШИМ.
* @note Индекс для свейл ШИМ расчитывается в самой функции.
*/
void PWM_SlavePhase_Set_DutyTable_Unsigned(PWM_SlaveHandleTypeDef *hspwm, uint16_t sin_ind)
{
// if three phase enables
if (PWM_Get_Mode(hspwm->hMasterPWM, PWM_PHASE_MODE))
{
if(hspwm->Duty_Shift_Ratio > 0)
sin_ind += hspwm->hMasterPWM->Duty_Table_Size*hspwm->Duty_Shift_Ratio;
else
sin_ind += hspwm->hMasterPWM->Duty_Table_Size*(1+hspwm->Duty_Shift_Ratio);
// overflow check
if(sin_ind > hspwm->hMasterPWM->Duty_Table_Size)
sin_ind -= hspwm->hMasterPWM->Duty_Table_Size;
PWM_Set_SlaveDuty_From_Table(hspwm, sin_ind); // set first channel
}
}
/**
* @brief Set Duty from table on Slave PWM at two channel by sin_ind of the Master PWM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param sin_ind - индекс таблицы для Мастер ШИМ.
* @note Индекс для свейл ШИМ расчитывается в самой функции.
*/
void PWM_SlavePhase_Set_DutyTable_Signed(PWM_SlaveHandleTypeDef *hspwm, uint16_t sin_ind)
{
int Duty;
// if three phase enables
if (PWM_Get_Mode(hspwm->hMasterPWM, PWM_PHASE_MODE))
{
if(hspwm->Duty_Shift_Ratio > 0)
sin_ind += hspwm->hMasterPWM->Duty_Table_Size*hspwm->Duty_Shift_Ratio;
else
sin_ind += hspwm->hMasterPWM->Duty_Table_Size*(1+hspwm->Duty_Shift_Ratio);
// overflow check
if(sin_ind >= hspwm->hMasterPWM->Duty_Table_Size)
sin_ind -= hspwm->hMasterPWM->Duty_Table_Size;
Duty = PWM_Get_Table_Element_Signed(hspwm->hMasterPWM, sin_ind);
// если это первая полуволна
if(Duty > 0)
{
PWM_Set_Compare1(hspwm, Duty+PWM_Calc_Min_Duty(hspwm->hMasterPWM)); // set first channel
PWM_Set_Compare2(hspwm, 0); // reset second channel
}
else // если это вторая полуволна
{
PWM_Set_Compare1(hspwm, 0); // reset first channel
PWM_Set_Compare2(hspwm, (-Duty)+PWM_Calc_Min_Duty(hspwm->hMasterPWM)); // set second channel
}
//if(hspwm == &hpwm2)
//__ASM("");
}
else // if three phase disabled
{
PWM_Set_Compare1(hspwm, 0); // reset first channel
PWM_Set_Compare2(hspwm, 0); // reset second channel
}
}
/**
* @brief Check is all Slave channels works properly.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Проверка работает ли только один из каналов, и проверка чтобы CCRx <= ARR
* @note В мастере проверка происходит напрямую в PWM_Handler.
*/
void PWM_SlavePhase_Check_Channels(PWM_SlaveHandleTypeDef *hspwm)
{
// if three phase enables
if (PWM_Get_Mode(hspwm->hMasterPWM, PWM_PHASE_MODE))
{
uint16_t min_duty = PWM_Calc_Min_Duty(hspwm->hMasterPWM);
// IF FIRST CHANNEL IS ACRIVE
if(PWM_Get_Compare1(hspwm) != 0)
{
// Duty shoud be bigger or equeal than min duration
if (PWM_Get_Compare1(hspwm)<min_duty)
PWM_Set_Compare1(hspwm, min_duty);
// Duty shoud be less or equeal than ARR-min duration
if (PWM_Get_Compare1(hspwm)>PWM_Get_Autoreload(hspwm)-min_duty)
PWM_Set_Compare1(hspwm, PWM_Get_Autoreload(hspwm)-min_duty);
}
// IF SECOND CHANNEL IS ACRIVE
else if(PWM_Get_Compare2(hspwm) != 0)
// Duty shoud be bigger or equeal than min duration
if (PWM_Get_Compare2(hspwm)<min_duty)
PWM_Set_Compare2(hspwm, min_duty);
// Duty shoud be less or equeal than ARR
if (PWM_Get_Compare2(hspwm)>PWM_Get_Autoreload(hspwm)-min_duty)
PWM_Set_Compare2(hspwm, PWM_Get_Autoreload(hspwm)-min_duty);
// IF BOTH CHANNEL IS ACRIVE
if((PWM_Get_Compare1(hspwm) != 0) && (PWM_Get_Compare2(hspwm) != 0))
{
// Only one channel shoud be active so disable all
PWM_Set_Compare1(hspwm, 0);
PWM_Set_Compare2(hspwm, 0);
}
}
else
{
// reset channels
PWM_Set_Compare1(hspwm, 0); // reset first channel
PWM_Set_Compare2(hspwm, 0); // reset second channel
}
}
/**
* @brief Create Dead Time for Slave PWM when switches channels.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param LocalDeadTimeCnt - указатель на переменную для отсчитывания дедтайма.
* @param LocalActiveChannel - указатель на переменную для отслеживания смены канала.
* @note Аналог функции PWM_CreateDeadTime но для слейв ШИМов.
*/
void PWM_SlavePhase_CreateDeadTime(PWM_SlaveHandleTypeDef *hspwm, float *LocalDeadTimeCnt, unsigned *LocalActiveChannel)
{
// get current active channel
hspwm->fActiveChannel = (PWM_Get_Compare2(hspwm) != 0); // if channel two is active - write 1, otherwise - 0
// when channels are swithed and no dead time currently active
if(*LocalActiveChannel != hspwm->fActiveChannel)
{ // update active channel
*LocalActiveChannel = hspwm->fActiveChannel;
// set deadtime
*LocalDeadTimeCnt = hspwm->hMasterPWM->PWM_DeadTime;
Trace_PWM_DeadTime_Enter();
}
// decrement dead time
*LocalDeadTimeCnt -= (PWM_Get_Autoreload(hspwm)+1)*hspwm->hMasterPWM->stim.sTickBaseMHz;
if(*LocalDeadTimeCnt > 0) // if dead time is still active
{ // reset all channels
// reset channels
PWM_Set_Compare1(hspwm, 0);
PWM_Set_Compare2(hspwm, 0);
}
else // if dead time is done
{ // set it to zero
*LocalDeadTimeCnt = 0;
Trace_PWM_DeadTime_Exit();
}
}
//-------------------------------------------------------------------
//------------------------HANDLERS FUNCTIONS-------------------------
//---------------PWM TIMER-----------------
#if (PWM_MASTER_TIM_NUMB == 1) || (PWM_MASTER_TIM_NUMB == 10) // choose handler for TIM
void TIM1_UP_TIM10_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 2)
void TIM2_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 3)
void TIM3_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 4)
void TIM4_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 5)
void TIM5_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 6)
void TIM6_DAC_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 7)
void TIM7_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 8) || (PWM_MASTER_TIM_NUMB == 13)
void TIM8_UP_TIM13_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 1) || (PWM_MASTER_TIM_NUMB == 9)
void TIM1_BRK_TIM9_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 1) || (PWM_MASTER_TIM_NUMB == 11)
void TIM1_TRG_COM_TIM11_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 8) || (PWM_MASTER_TIM_NUMB == 12)
void TIM8_BRK_TIM12_IRQHandler(void)
#elif (PWM_MASTER_TIM_NUMB == 8) || (PWM_MASTER_TIM_NUMB == 14)
void TIM8_TRG_COM_TIM14_IRQHandler(void)
#endif
{
Trace_PWM_TIM_Enter();
HAL_TIM_IRQHandler(&hpwm1.stim.htim);
PWM_Handler(&hpwm1);
Trace_PWM_TIM_Exit();
}
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//-----------------------------OUTDATE-------------------------------
#ifdef OUTDATE
/**
* @brief First set up of PWM Single Channel.
* @note Первый инит ШИМ. Заполняет структуры и инициализирует таймер для генерации синуоидального ШИМ.
* Скважность ШИМ меняется по закону синусоиды, сдвинутой в положительную область (от 0 до 2)
* ШИМ генерируется на одном канале.
* @note This called from main
*/
void PWM_SineSingChannel_FirstInit(void)
{
hpwm1.pDuty_Table_Origin = SIN_TABLE_ORIGIN;
//---------PWM TIMER1 INIT------------
// channel settings
hpwm1.sConfigOC.OCMode = TIM_OCMODE_PWM1;
hpwm1.sConfigOC.Pulse = 0;
hpwm1.sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
hpwm1.sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
// tim1 settings
hpwm1.stim.htim.Instance = TIMER_PWM1_INSTANCE;
hpwm1.stim.sTimMode = TIM_IT_MODE;
hpwm1.stim.sTickBaseMHz = TIM_TickBase_1US;
hpwm1.stim.sTimAHBFreqMHz = 72;
hpwm1.stim.sTimFreqHz = HZ_TIMER_PWM;
hpwm1.GPIOx = GPIOD;
hpwm1.GPIO_PIN_X1 = GPIO_PIN_12;
TIM_Base_Init(&hpwm1.stim);
TIM_Output_PWM_Init(&hpwm1.stim.htim, &hpwm1.sConfigOC, hpwm->PWM_Channel1, hpwm1.GPIOx, hpwm1.GPIO_PIN_X1);
//----------TIMERS START-------------
HAL_TIM_PWM_Start_IT(&hpwm1.stim.htim, hpwm->PWM_Channel1); // timer for PWM
}
#ifdef SINE_THREE_PHASE_PWM_ENABLE
//---------PWM TIMER2 INIT------------
// tim2 settings
hpwm2 = hpwm1;
hpwm2.stim.htim.Instance = TIM5;
hpwm2.GPIOx = GPIOA;
hpwm2.GPIO_PIN_X = GPIO_PIN_0;
TIM_Base_Init(&hpwm2.stim);
TIM_Output_PWM_Init(&hpwm2.stim.htim, &hpwm2.sConfigOC, TIM_CHANNEL_1, hpwm2.GPIOx, hpwm2.GPIO_PIN_X);
//---------PWM TIMER3 INIT------------
// tim3 settings
hpwm3 = hpwm2;
hpwm3.stim.htim.Instance = TIM8;
hpwm3.GPIOx = GPIOC;
hpwm3.GPIO_PIN_X = GPIO_PIN_6;
TIM_Base_Init(&hpwm3.stim);
TIM_Output_PWM_Init(&hpwm3.stim.htim, &hpwm3.sConfigOC, TIM_CHANNEL_1, hpwm3.GPIOx, hpwm3.GPIO_PIN_X);
HAL_TIM_PWM_Start(&hpwm2.stim.htim, TIM_CHANNEL_1); // timer for PWM
HAL_TIM_PWM_Start(&hpwm3.stim.htim, TIM_CHANNEL_1); // timer for PWM
#endif // SINE_THREE_PHASE_PWM_ENABLE
void PWM_Threephase_Init(void)
{
#ifdef INTERNAL_THREE_PHASE_PWM_ENABLE
TIM_OC_InitTypeDef sPWMConfigOC = {0};
TIM_OC_InitTypeDef sOCConfigOC = {0};
int us100Time = 10000/TIM_CTRL.sTimFreqHz; // 1/TIM_CTRL.sTimFreqHz * 10^6 - Sample time in us
// PWM CHANNEL SETTINGS
sPWMConfigOC.OCMode = TIM_OCMODE_PWM1;
sPWMConfigOC.Pulse = us100Time/2;
sPWMConfigOC.OCPolarity = TIM_OCPOLARITY_LOW;
sPWMConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
// CC CHANNEL SETTINGS
sOCConfigOC.OCMode = TIM_OCMODE_ACTIVE;
sOCConfigOC.Pulse = (2*us100Time-1) / 3;
sOCConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
// TIMER1 PWM MASTER INIT
TIM_3PWM1.htim = &tim_3pwm1;
TIM_3PWM1.htim->Instance = TIM1;
TIM_3PWM1.htim->Init.Prescaler = 7200-1; // 1 us
TIM_3PWM1.htim->Init.Period = us100Time-1; // period in us = Sample time in us
TIM_3PWM1.sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC2REF;
TIM_3PWM1.sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
TIM_3PWM1.sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
TIM_Base_Init(&TIM_3PWM1);
TIM_Output_PWM_Init(TIM_3PWM1.htim, &sPWMConfigOC, TIM_CHANNEL_1, GPIOE, GPIO_PIN_9);
HAL_TIM_OC_ConfigChannel(TIM_3PWM1.htim, &sOCConfigOC, TIM_CHANNEL_2);
// TIMER2 PWM SLAVE INIT
TIM_3PWM2 = TIM_3PWM1;
TIM_3PWM2.htim = &tim_3pwm2;
*TIM_3PWM2.htim = *TIM_3PWM1.htim;
TIM_3PWM2.htim->Instance = TIM2;
TIM_3PWM1.TIM_MODE = TIM_DEFAULT;
TIM_3PWM2.sSlaveConfig.SlaveMode = TIM_SLAVEMODE_TRIGGER;
TIM_3PWM2.sSlaveConfig.InputTrigger = TIM_TS_ITR0;
TIM_Base_Init(&TIM_3PWM2);
TIM_Output_PWM_Init(TIM_3PWM2.htim, &sPWMConfigOC, TIM_CHANNEL_1, GPIOA, GPIO_PIN_5);
HAL_TIM_OC_ConfigChannel(TIM_3PWM2.htim, &sOCConfigOC, TIM_CHANNEL_2);
// TIMER3 PWM SLAVE INIT
TIM_3PWM3 = TIM_3PWM2;
TIM_3PWM3.htim = &tim_3pwm3;
*TIM_3PWM3.htim = *TIM_3PWM2.htim;
TIM_3PWM3.htim->Instance = TIM3;
TIM_3PWM3.sSlaveConfig.InputTrigger = TIM_TS_ITR1;
TIM_Base_Init(&TIM_3PWM3);
TIM_Output_PWM_Init(TIM_3PWM3.htim, &sPWMConfigOC, TIM_CHANNEL_1, GPIOA, GPIO_PIN_6);
hpwm1.Duty_Table_Size = PWM_Fill_Sine_Table(&sin_table, SIN_TABLE_SIZE_MAX);
// TIMERS START
HAL_TIM_OC_Start(TIM_3PWM3.htim, TIM_CHANNEL_2);
HAL_TIM_PWM_Start(TIM_3PWM3.htim, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(TIM_3PWM2.htim, TIM_CHANNEL_1);
HAL_TIM_OC_Start(TIM_3PWM2.htim, TIM_CHANNEL_2);
HAL_TIM_OC_Start(TIM_3PWM1.htim, TIM_CHANNEL_2);
HAL_TIM_PWM_Start(TIM_3PWM1.htim, TIM_CHANNEL_1);
#endif // INTERNAL_THREE_PHASE_PWM_ENABLE
}
#endif

324
Code/PWM/pwm.h
View File

@@ -1,324 +0,0 @@
/********************************MODBUS*************************************
Данный файл содержит объявления базовых функции и дефайны для реализации
MODBUS.
Данный файл необходимо подключить в rs_message.h. После подключать rs_message.h
к основному проекту.
***************************************************************************/
#ifndef __PWM_H_
#define __PWM_H_
#include "control.h"
extern uint32_t sin_table[SIN_TABLE_SIZE_MAX];
#define int_to_percent(_int_) ((float)_int_/100)
/////////////////////////////////////////////////////////////////////
////////////////////////////---DEFINES---////////////////////////////
//----------------------------PWM HANDLE----------------------------//
/**
* @brief Calc duration of minimum pulse in ticks.
* @param _hpwm_ - указатель на хендл pwm.
* @return _val_ - количество тиков кратчайшего импульса.
*/
#define PWM_Calc_Min_Duty(_hpwm_) ((_hpwm_)->PWM_MinPulseDur/(_hpwm_)->stim.sTickBaseMHz)
/**
* @brief Calc Scale Koef for Table & AUTORELOAD REGISTER
* @param _hpwm_ - указатель на хендл pwm.
* @param _scale_ - верхняя граница диапазона значений.
* @return _koef_ - коэффициент для масштабирования.
* @note Данный макрос рассчитывает коэффициент для приведения значений с диапазоном [0,_scale_]
к регистру автозагрузки с диапазоном [0,ARR].
* @note Если задана минимальная длительность импульса в тактах n, она вычитается из ARR: [0, ARR-2*n]
И потом регистр ARR заполняется так, что диапазон его значений будет [n, ARR-n] @ref PWM_Get_Table_Element_Unsigned
*/
#define PWM_Calc_Duty_Scale(_hpwm_, _scale_) ((float)PWM_Get_Autoreload(_hpwm_))/(_scale_)
/**
* @brief Get Table Element Scaled corresponding to TIM ARR register
* @param _hpwm_ - указатель на хендл pwm.
* @param _ind_ - номер элемента из таблицы скважностей.
* @return _val_ - масштабированный под регистры таймера значение.
* @note Если задана минимальная длительность импульса в тактах n,
то регистр ARR заполняется так, что диапазон его значений будет [n, ARR-n]
*/
#define PWM_Get_Table_Element_Unsigned(_hpwm_,_ind_) (*((_hpwm_)->pDuty_Table_Origin+_ind_)*((_hpwm_)->Duty_Table_Scale))
/**
* @brief Get Table Element Scaled and Shifted corresponding to TIM ARR register
* @param _hpwm_ - указатель на хендл pwm.
* @param _ind_ - номер элемента из таблицы скважностей.
* @return _val_ - масштабированный под регистры таймера значение.
* @note По сути такая же как PWM_Get_Table_Element_Unsigned но добавляется сдвиг на одну амплитуду для учитывания знака.
(если точнее, то сдвиг добавляется для компенсации сдвига, который имитирует знак)
* @note 0x8000*(_hpwm_)->Duty_Table_Scale - т.к. первая полуволна находится в диапазоне (0x8000-0xFFFF) вычитаем константу 0x8000 с масштабированием
*/
#define PWM_Get_Table_Element_Signed(_hpwm_,_ind_) ((int)(*((_hpwm_)->pDuty_Table_Origin+_ind_)*((_hpwm_)->Duty_Table_Scale))-0x8000*(_hpwm_)->Duty_Table_Scale)
/**
* @brief Create pointer to slave PWM from pointer to void in PWM_HandleTypeDef.
* @param _hpwm_ - указатель на хендл pwm.
* @param _slavepwm_ - имя слейв pwm.
* @return _pslavepwm_ - указатель на структуру PWM_SlaveHandleTypeDef.
*/
#define PWM_Set_pSlaveHandle(_hpwm_,_slavepwm_) ((PWM_SlaveHandleTypeDef *)_hpwm_->_slavepwm_)
/**
* @brief Copy setting from master TIM_SettingsTypeDef to slave TIM_SettingsTypeDef.
* @param _hpwm_ - указатель на хендл pwm.
* @return _set_ - имя настройки.
*/
#define PWM_Slave_CopyTimSetting(_hspwm_, _set_) ((_hspwm_)->stim._set_ = (_hspwm_)->hMasterPWM->stim._set_)
//---------------------------TIMER REGS----------------------------//
/**
* @brief Set PWM autoreload value (max duty value).
* @param _hpwm_ - указатель на хендл pwm.
* @param _val_ - значение, которое нужно записать в Compare.
*/
#define PWM_Get_Autoreload(_hpwm_) __HAL_TIM_GET_AUTORELOAD(&((_hpwm_)->stim.htim))
/**
* @brief Get PWM Duty on corresponding channel.
* @param _hpwm_ - указатель на хендл pwm.
* @param _val_ - значение, которое нужно записать в Compare.
*/
#define PWM_Get_Compare1(_hpwm_) __HAL_TIM_GET_COMPARE(&((_hpwm_)->stim.htim), (_hpwm_)->PWM_Channel1)
#define PWM_Get_Compare2(_hpwm_) __HAL_TIM_GET_COMPARE(&((_hpwm_)->stim.htim), (_hpwm_)->PWM_Channel2)
/**
* @brief Set PWM Duty on corresponding channel.
* @param _hpwm_ - указатель на хендл pwm.
* @param _val_ - значение, которое нужно записать в Compare.
*/
#define PWM_Set_Compare1(_hpwm_, _val_) __HAL_TIM_SET_COMPARE(&((_hpwm_)->stim.htim), (_hpwm_)->PWM_Channel1, (_val_))
#define PWM_Set_Compare2(_hpwm_, _val_) __HAL_TIM_SET_COMPARE(&((_hpwm_)->stim.htim), (_hpwm_)->PWM_Channel2, (_val_))
/**
* @brief Set PWM Duty From PWM_Value Percent
* @param _hpwm_ - указатель на хендл pwm.
* @param _channel_ - канал для выставления скважности.
* @param _ind_ - номер элемента из таблицы скважностей.
*/
#define PWM_Set_Duty_From_Percent(_hpwm_, _channel_) __HAL_TIM_SET_COMPARE(&((_hpwm_)->stim.htim), _channel_, ((_hpwm_)->PWM_Value/100)*(PWM_Get_Autoreload(_hpwm_)+1))
/**
* @brief Set PWM Duty From table
* @param _hpwm_ - указатель на хендл pwm.
* @param _channel_ - канал для выставления скважности.
* @param _ind_ - номер элемента из таблицы скважностей.
*/
#define PWM_Set_Duty_From_Table(_hpwm_, _ind_) (PWM_Set_Compare1(_hpwm_, (PWM_Get_Table_Element_Unsigned((_hpwm_), (_ind_))+1)))
/**
* @brief Set PWM Duty From table
* @param _hpwm_ - указатель на хендл pwm.
* @param _channel_ - канал для выставления скважности.
* @param _ind_ - номер элемента из таблицы скважностей.
*/
#define PWM_Set_SlaveDuty_From_Table(_hpwm_, _ind_) (PWM_Set_Compare1(_hpwm_, (PWM_Get_Table_Element_Unsigned((_hpwm_)->hMasterPWM, (_ind_))+1)))
// MODE DEFINES
#define PWM_DC_MODE_Pos (0)
#define PWM_CH_MODE_Pos (1)
#define PWM_PHASE_MODE_Pos (2)
#define PWM_DC_MODE (1<<(PWM_DC_MODE_Pos)) // 0 - set pwm duty from table with PWM_Value period, 1 - set pwm duty PWM_Value (in percent)
#define PWM_CH_MODE (1<<(PWM_CH_MODE_Pos))
// DC MODE: 0 - pwm on channel 1, 1 - pwm on channel 2
// TABLE MODE: 0 - signed mode, 1 - unsigned mode
#define PWM_PHASE_MODE (1<<(PWM_PHASE_MODE_Pos))
#define PWM_Get_Mode(_hpwm_, _mode_) ((_hpwm_)->sPWM_Mode&(_mode_))
/* Structure for PWM modes */
typedef enum
{
PWM_TABLE_UNSIGN = 0, /* set pwm duty from table with PWM_Value period */
PWM_TABLE_SIGN = PWM_CH_MODE, /* set pwm duty from table with PWM_Value period on two channels (positive and negative halfes) */
PWM_DC_POS = PWM_DC_MODE, /* set pwm duty PWM_Value (in percent) on first channel */
PWM_DC_NEG = PWM_DC_MODE|PWM_CH_MODE, /* set pwm duty PWM_Value (in percent) on second channel */
PWM_PHASE_UNSIGN = PWM_PHASE_MODE, /* set pwm table duty on three pins, with requested shift */
PWM_PHASE_SIGN = PWM_CH_MODE|PWM_PHASE_MODE, /* set pwm table duty on six pins (two pins = one phase (positive and negative halfes)) */
}PWM_ModeTypeDef;
/**
* @brief Handle for PWM.
* @note Prefixes: h - handle, s - settings, f - flag
*/
typedef struct // PWM_HandleTypeDef
{
/* PWM VARIABLES */
PWM_ModeTypeDef sPWM_Mode; /* PWM Mode: 0 - DC mode, 1 - Table mode */
float PWM_Value; /* DC mode: PWM duty, Table mode: frequency*/
uint32_t PWM_MinPulseDur; /* minimum pulse duration for PWM in us*/
uint32_t PWM_DeadTime; /* dead-Time between switches half waves (channels) in us */
/* SETTINGS FOR TIMER */
TIM_SettingsTypeDef stim; /* settings for TIM */
TIM_OC_InitTypeDef sConfigOC; /* settings for oc channel */
unsigned fActiveChannel; /* flag for active oc channel: 0 - first channel, 1 - second channel */
uint16_t PWM_Channel1; /* instance of first channel */
uint16_t PWM_Channel2; /* instance of second channel */
/* VARIABLES FOR TABLE DUTY PARAMETERS */
uint32_t *pDuty_Table_Origin; /* pointer to table of pwm duties */
uint32_t Duty_Table_Size; /* size of duty table */
float Duty_Table_Ind; /* current ind of duty table */
float Duty_Table_Scale; /* scale for TIM ARR register */
/* SETTIGNS FOR PWM OUTPUT */
GPIO_TypeDef *GPIOx; /* GPIO port for PWM output */
uint32_t GPIO_PIN_X1; /* GPIO pin for PWM output */
uint32_t GPIO_PIN_X2; /* GPIO pin for PWM output (second half wave) */
/* SLAVES PWM */
void *hpwm2;
void *hpwm3;
}PWM_HandleTypeDef;
extern PWM_HandleTypeDef hpwm1;
/**
* @brief Handle for Slave PWM.
* @note Prefixes: h - handle, s - settings, f - flag
*/
typedef struct // PWM_SlaveHandleTypeDef
{
/* MASTER PWM*/
PWM_HandleTypeDef *hMasterPWM; /* master pwm handle */
/* SETTINGS FOR TIMER */
TIM_SettingsTypeDef stim; /* slave tim handle */
unsigned fActiveChannel; /* flag for active oc channel: 0 - first channel, 1 - second channel */
uint16_t PWM_Channel1; /* instance of first channel */
uint16_t PWM_Channel2; /* instance of second channel */
/* VARIABLES FOR TABLE DUTY PARAMETERS */
float Duty_Table_Ind; /* current ind of duty table */
float Duty_Shift_Ratio; /* Ratio of table shift: 0.5 shift - shift = Table_Size/2 */
/* SETTIGNS FOR PWM OUTPUT */
GPIO_TypeDef *GPIOx; /* GPIO port for PWM output */
uint32_t GPIO_PIN_X1; /* GPIO pin for PWM output */
uint32_t GPIO_PIN_X2; /* GPIO pin for PWM output (second half wave) */
}PWM_SlaveHandleTypeDef;
extern PWM_SlaveHandleTypeDef hpwm2;
extern PWM_SlaveHandleTypeDef hpwm3;
//--------------------------------PWM FUNCTIONS----------------------------------
/**
* @brief reInitialization of PWM TIM.
* @param hpwm - указатель на хендл ШИМ.
* @note Перенастраивает таймер согласно принятным настройкам в pwm_ctrl.
*/
void PWM_Sine_ReInit(PWM_HandleTypeDef *hpwm);
/**
* @brief Initialization of Slave PWM TIM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Вызывает функции инициализации и включения слейв ШИМ.
*/
void PWM_SlavePhase_Init(PWM_SlaveHandleTypeDef *hspwm);
/**
* @brief reInitialization of Slave PWM TIM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Перенастраивает таймер согласно принятным настройкам в pwm_ctrl.
*/
void PWM_SlavePhase_reInit(PWM_SlaveHandleTypeDef *hspwm);
/**
* @brief Filling table with one period of sinus values.
* @param hpwm - указатель на хендл ШИМ.
* @param table_size - размер таблицы.
* @note Формирует таблицу синусов размером table_size.
*/
uint32_t PWM_Fill_Sine_Table(PWM_HandleTypeDef *hpwm, uint32_t table_size);
/**
* @brief Calc and update new Duty Table Scale.
* @param hpwm - указатель на хендл ШИМ.
* @note Используется, когда изменяется значение регистра ARR.
*/
void PWM_Update_DutyTableScale(PWM_HandleTypeDef *hpwm);
//---------------------this called from TIM_PWM_Handler()------------------------
// MASTER PWM FUNCTIONS
/**
* @brief PWM Handler.
* @param hpwm - указатель на хендл ШИМ.
* @note Управляет скважность ШИМ в режиме PWM_TABLE.
* @note This called from TIM_PWM_Handler
*/
void PWM_Handler(PWM_HandleTypeDef *hpwm);
/**
* @brief Getting ind for Duty Table.
* @param hpwm - указатель на хендл ШИМ.
* @param FreqTIM - частота таймера ШИМ.
* @note Рассчитывает индекс для таблицы скважностей.
* PWM_Value в hpwm - частота с которой эта таблица должна выводиться на ШИМ
* @note This called from TIM_PWM_Handler
*/
uint32_t PWM_Get_Duty_Table_Ind(PWM_HandleTypeDef *hpwm, float FreqTIM);
/**
* @brief Create Dead Time when switches channels.
* @param hpwm - указатель на хендл ШИМ.
* @param LocalDeadTimeCnt - указатель на переменную для отсчитывания дедтайма.
* @param LocalActiveChannel - указатель на переменную для отслеживания смены канала.
*/
void PWM_CreateDeadTime(PWM_HandleTypeDef *hpwm, float *LocalDeadTimeCnt, unsigned *LocalActiveChannel);
// SLAVE PWM FUNCTIONS
/**
* @brief Set Duty from table on Slave PWM at one channel by sin_ind of the Master PWM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param sin_ind - индекс таблицы для Мастер ШИМ.
* @note Индекс для свейл ШИМ расчитывается в самой функции.
*/
void PWM_SlavePhase_Set_DutyTable_Unsigned(PWM_SlaveHandleTypeDef *hspwm, uint16_t sin_ind);
/**
* @brief Set Duty from table on Slave PWM at two channel by sin_ind of the Master PWM.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param sin_ind - индекс таблицы для Мастер ШИМ.
* @note Индекс для свейл ШИМ расчитывается в самой функции.
*/
void PWM_SlavePhase_Set_DutyTable_Signed(PWM_SlaveHandleTypeDef *hspwm, uint16_t sin_ind);
/**
* @brief Check is all Slave channels works properly.
* @param hspwm - указатель на хендл слейв ШИМ.
* @note Проверка работает ли только один из каналов, и проверка чтобы CCRx <= ARR
* @note В мастере проверка происходит напрямую в PWM_Handler.
*/
void PWM_SlavePhase_Check_Channels(PWM_SlaveHandleTypeDef *hspwm);
/**
* @brief Create Dead Time for Slave PWM when switches channels.
* @param hspwm - указатель на хендл слейв ШИМ.
* @param LocalDeadTimeCnt - указатель на переменную для отсчитывания дедтайма.
* @param LocalActiveChannel - указатель на переменную для отслеживания смены канала.
* @note Аналог функции PWM_CreateDeadTime но для слейв ШИМов.
*/
void PWM_SlavePhase_CreateDeadTime(PWM_SlaveHandleTypeDef *hspwm, float *LocalDeadTimeCnt, unsigned *LocalActiveChannel);
//---------------------this called from TIM_CTRL_Handler()-----------------------
/**
* @brief Update PWM parameters.
* @param hpwm - указатель на хендл ШИМ.
* @note Проверка надо ли обновлять параметры ШИМ, и если надо - обновляет их.
* @note This called from TIM_CTRL_Handler
*/
void Update_Params_For_PWM(PWM_HandleTypeDef *hpwm);
//---------------------------this called from main()-----------------------------
/**
* @brief First set up of PWM Two Channel.
* @note Первый инит ШИМ. Заполняет структуры и инициализирует таймер для генерации синуоидального ШИМ.
* Скважность ШИМ меняется по закону синусоиды, каждый канал генерирует свой полупериод синуса (от -1 до 0 И от 0 до 1)
* ШИМ генерируется на одном канале.
* @note This called from main OR by setted coil
*/
void PWM_Sine_FirstInit(void);
#endif // __PWM_H_

265
Code/PWM/settings.c
View File

@@ -1,265 +0,0 @@
#include "control.h"
ProjectSettings_TypeDef PROJSET;
uint32_t PageError = 0x00;
uint8_t UpdateSettings = 0;
void WriteSettingsToMem(void)
{
FillStructWithDefines();
//HAL_FLASH_Unlock();
//
//CheckSettingsInFLASH();
//
//if(CheckIsSettingsValid(&PROJSET)) // if new settings are invalid
// PROJSET = *PROJSET_MEM; // take the old settings from mem
//else // if new settings are valid
// SetFlagUpdateSettingsInMem(); // save the new settings in mem (set flag to do this)
//
//HAL_FLASH_Lock();
}
void SetFlagUpdateSettingsInMem(void)
{
//UpdateSettings = 0;
//// MODBUS settings
//if(PROJSET_MEM->MB_DEVICE_ID != PROJSET.MB_DEVICE_ID)
// UpdateSettings = 1;
//if(PROJSET_MEM->MB_SPEED != PROJSET.MB_SPEED)
// UpdateSettings = 1;
//if(PROJSET_MEM->MB_GPIOX != PROJSET.MB_GPIOX)
// UpdateSettings = 1;
//if(PROJSET_MEM->MB_GPIO_PIN_RX != PROJSET.MB_GPIO_PIN_RX)
// UpdateSettings = 1;
//if(PROJSET_MEM->MB_GPIO_PIN_RX != PROJSET.MB_GPIO_PIN_RX)
// UpdateSettings = 1;
//if(PROJSET_MEM->MB_MAX_TIMEOUT != PROJSET.MB_MAX_TIMEOUT)
// UpdateSettings = 1;
//
//// PWM settings
//if(PROJSET_MEM->TIM_PWM_TICKBASE != PROJSET.TIM_PWM_TICKBASE)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM_AHB_FREQ != PROJSET.TIM_PWM_AHB_FREQ)
// UpdateSettings = 1;
//
//if(PROJSET_MEM->TIM_PWM1_TIM_CHANNEL1 != PROJSET.TIM_PWM1_TIM_CHANNEL1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM1_TIM_CHANNEL2 != PROJSET.TIM_PWM1_TIM_CHANNEL2)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM1_GPIOx != PROJSET.TIM_PWM1_GPIOx)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM1_GPIO_PIN_X1 != PROJSET.TIM_PWM1_GPIO_PIN_X1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM1_GPIO_PIN_X2 != PROJSET.TIM_PWM1_GPIO_PIN_X2)
// UpdateSettings = 1;
//
//if(PROJSET_MEM->TIM_PWM2_INSTANCE != PROJSET.TIM_PWM2_INSTANCE)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM2_TIM_CHANNEL1 != PROJSET.TIM_PWM2_TIM_CHANNEL1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM2_TIM_CHANNEL2 != PROJSET.TIM_PWM2_TIM_CHANNEL2)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM2_GPIOx != PROJSET.TIM_PWM2_GPIOx)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM2_GPIO_PIN_X1 != PROJSET.TIM_PWM2_GPIO_PIN_X1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM2_GPIO_PIN_X2 != PROJSET.TIM_PWM2_GPIO_PIN_X2)
// UpdateSettings = 1;
//
//if(PROJSET_MEM->TIM_PWM3_INSTANCE != PROJSET.TIM_PWM3_INSTANCE)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM3_TIM_CHANNEL1 != PROJSET.TIM_PWM3_TIM_CHANNEL1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM3_TIM_CHANNEL2 != PROJSET.TIM_PWM3_TIM_CHANNEL2)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM3_GPIOx != PROJSET.TIM_PWM3_GPIOx)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM3_GPIO_PIN_X1 != PROJSET.TIM_PWM3_GPIO_PIN_X1)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_PWM3_GPIO_PIN_X2 != PROJSET.TIM_PWM3_GPIO_PIN_X2)
// UpdateSettings = 1;
//
//// CTRL settings
//if(PROJSET_MEM->TIM_CTRL_TICKBASE != PROJSET.TIM_CTRL_TICKBASE)
// UpdateSettings = 1;
//if(PROJSET_MEM->TIM_CTRL_AHB_FREQ != PROJSET.TIM_CTRL_AHB_FREQ)
// UpdateSettings = 1;
}
void UpdateSettingsInMem(void)
{
//if(UpdateSettings)
//{
// FLASH_EraseInitTypeDef EraseInitStruct;
// PageError = 0x00;
//
// EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;// erase pages
// EraseInitStruct.Banks = FLASH_BANK_1;
// EraseInitStruct.Sector = FLASH_SECTOR_4; //first sector for erase
// EraseInitStruct.NbSectors = 1;// num of sector that need to be erased
//
// HAL_FLASH_Unlock();
// HAL_FLASHEx_Erase(&EraseInitStruct, &PageError);
//
//
// /* Wait for last operation to be completed */
// if(FLASH_WaitForLastOperation((uint32_t)50000U) == HAL_OK)
// {
// /* If the previous operation is completed, proceed to program the new data */
// CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
// FLASH->CR |= FLASH_PSIZE_WORD;
// FLASH->CR |= FLASH_CR_PG;
// *PROJSET_MEM = PROJSET; // save the new settings in mem
// }
// HAL_FLASH_Lock();
// UpdateSettings = 0;
//}
}
void FillSettingsWithDefines(void)
{
// rewrite all setting corresponding to defines
//FLASH_EraseInitTypeDef EraseInitStruct;
//PageError = 0x00;
//
//EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;// erase pages
//EraseInitStruct.Banks = FLASH_BANK_1;
//EraseInitStruct.Sector = FLASH_SECTOR_4; //first sector for erase
//EraseInitStruct.NbSectors = 1;// num of sector that need to be erased
//
//HAL_FLASH_Unlock();
//HAL_FLASHEx_Erase(&EraseInitStruct, &PageError);
//// MODBUS settings
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_DEVICE_ID, MODBUS_DEVICE_ID);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_SPEED, MODBUS_SPEED);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_GPIOX, (uint32_t)MODBUS_GPIOX);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_GPIO_PIN_RX, MODBUS_GPIO_PIN_RX);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_GPIO_PIN_TX, MODBUS_GPIO_PIN_TX);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_MAX_TIMEOUT, MODBUS_MAX_TIMEOUT);
//FLASH_WRITE_SETTING(PROJSET_MEM->MB_TIM_AHB_FREQ, MODBUS_TIM_AHB_FREQ);
//
//// PWM settings
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM_TICKBASE, TIMER_PWM_TICKBASE);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM_AHB_FREQ, TIMER_PWM_AHB_FREQ);
//
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM1_TIM_CHANNEL1, TIMER_PWM1_TIM_CHANNEL1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM1_TIM_CHANNEL2, TIMER_PWM1_TIM_CHANNEL2);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM1_GPIOx, (uint32_t)TIMER_PWM1_GPIOx);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM1_GPIO_PIN_X1, TIMER_PWM1_GPIO_PIN_X1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM1_GPIO_PIN_X2, TIMER_PWM1_GPIO_PIN_X2);
//
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_INSTANCE, (uint32_t)TIMER_PWM2_INSTANCE);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_TIM_CHANNEL1, TIMER_PWM2_TIM_CHANNEL1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_TIM_CHANNEL2, TIMER_PWM2_TIM_CHANNEL2);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_GPIOx, (uint32_t)TIMER_PWM2_GPIOx);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_GPIO_PIN_X1, TIMER_PWM2_GPIO_PIN_X1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM2_GPIO_PIN_X2, TIMER_PWM2_GPIO_PIN_X2);
//
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_INSTANCE, (uint32_t)TIMER_PWM3_INSTANCE);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_TIM_CHANNEL1, TIMER_PWM3_TIM_CHANNEL1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_TIM_CHANNEL2, TIMER_PWM3_TIM_CHANNEL2);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_GPIOx, (uint32_t)TIMER_PWM3_GPIOx);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_GPIO_PIN_X1, TIMER_PWM3_GPIO_PIN_X1);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_PWM3_GPIO_PIN_X2, TIMER_PWM3_GPIO_PIN_X2);
//
//// CTRL settings
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_CTRL_TICKBASE, TIMER_CTRL_TICKBASE);
//FLASH_WRITE_SETTING(PROJSET_MEM->TIM_CTRL_AHB_FREQ, TIMER_CTRL_AHB_FREQ);
//HAL_FLASH_Lock();
}
void FillStructWithDefines(void)
{
// rewrite all setting corresponding to defines
// MODBUS settings
STRUCT_WRITE_SETTING(PROJSET.MB_DEVICE_ID, MODBUS_DEVICE_ID);
STRUCT_WRITE_SETTING(PROJSET.MB_SPEED, MODBUS_SPEED);
STRUCT_WRITE_SETTING(PROJSET.MB_GPIOX, MODBUS_GPIOX);
STRUCT_WRITE_SETTING(PROJSET.MB_GPIO_PIN_RX, MODBUS_GPIO_PIN_RX);
STRUCT_WRITE_SETTING(PROJSET.MB_GPIO_PIN_TX, MODBUS_GPIO_PIN_TX);
STRUCT_WRITE_SETTING(PROJSET.MB_MAX_TIMEOUT, MODBUS_MAX_TIMEOUT);
STRUCT_WRITE_SETTING(PROJSET.MB_TIM_AHB_FREQ, MODBUS_TIM_AHB_FREQ);
// PWM settings
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM_TICKBASE, TIMER_PWM_TICKBASE);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM_AHB_FREQ, TIMER_PWM_AHB_FREQ);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM1_TIM_CHANNEL1, TIMER_PWM1_TIM_CHANNEL1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM1_TIM_CHANNEL2, TIMER_PWM1_TIM_CHANNEL2);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM1_GPIOx, TIMER_PWM1_GPIOx);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM1_GPIO_PIN_X1, TIMER_PWM1_GPIO_PIN_X1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM1_GPIO_PIN_X2, TIMER_PWM1_GPIO_PIN_X2);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_INSTANCE, TIMER_PWM2_INSTANCE);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_TIM_CHANNEL1, TIMER_PWM2_TIM_CHANNEL1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_TIM_CHANNEL2, TIMER_PWM2_TIM_CHANNEL2);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_GPIOx, TIMER_PWM2_GPIOx);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_GPIO_PIN_X1, TIMER_PWM2_GPIO_PIN_X1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM2_GPIO_PIN_X2, TIMER_PWM2_GPIO_PIN_X2);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_INSTANCE, TIMER_PWM3_INSTANCE);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_TIM_CHANNEL1, TIMER_PWM3_TIM_CHANNEL1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_TIM_CHANNEL2, TIMER_PWM3_TIM_CHANNEL2);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_GPIOx, TIMER_PWM3_GPIOx);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_GPIO_PIN_X1, TIMER_PWM3_GPIO_PIN_X1);
STRUCT_WRITE_SETTING(PROJSET.TIM_PWM3_GPIO_PIN_X2, TIMER_PWM3_GPIO_PIN_X2);
// CTRL settings
STRUCT_WRITE_SETTING(PROJSET.TIM_CTRL_TICKBASE, TIMER_CTRL_TICKBASE);
STRUCT_WRITE_SETTING(PROJSET.TIM_CTRL_AHB_FREQ, TIMER_CTRL_AHB_FREQ);
}
void CheckSettingsInFLASH(void)
{
//if(CheckIsSettingsValid(PROJSET_MEM))
// FillSettingsWithDefines();
//
//PROJSET = *PROJSET_MEM;
}
int CheckIsSettingsValid(ProjectSettings_TypeDef *set_struct)
{
// if some of setting are missing
// chech MODBUS
if((!IS_UART_BAUDRATE(set_struct->MB_SPEED) || (set_struct->MB_SPEED ) == 0) ||
(!IS_GPIO_ALL_INSTANCE((GPIO_TypeDef *)set_struct->MB_GPIOX)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->MB_GPIO_PIN_TX)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->MB_GPIO_PIN_RX)) ||
((set_struct->MB_TIM_AHB_FREQ) == 0))
{
return 1;
}
// chech control tim
if((set_struct->TIM_CTRL_AHB_FREQ) == 0)
{
return 1;
}
// chech PWM tims
if((set_struct->TIM_PWM_AHB_FREQ) == 0 ||
(!IS_GPIO_ALL_INSTANCE((GPIO_TypeDef *)set_struct->TIM_PWM1_GPIOx)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM1_GPIO_PIN_X1)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM1_GPIO_PIN_X2)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM1_TIM_CHANNEL1)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM1_TIM_CHANNEL2)) ||
(!IS_TIM_INSTANCE((TIM_TypeDef *)set_struct->TIM_PWM2_INSTANCE)) ||
(!IS_GPIO_ALL_INSTANCE((GPIO_TypeDef *)set_struct->TIM_PWM2_GPIOx)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM2_GPIO_PIN_X1)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM2_GPIO_PIN_X2)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM2_TIM_CHANNEL1)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM2_TIM_CHANNEL2)) ||
(!IS_TIM_INSTANCE((TIM_TypeDef *)set_struct->TIM_PWM3_INSTANCE)) ||
(!IS_GPIO_ALL_INSTANCE((GPIO_TypeDef *)set_struct->TIM_PWM3_GPIOx)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM3_GPIO_PIN_X1)) ||
(!IS_GPIO_PIN((GPIO_TypeDef *)set_struct->TIM_PWM3_GPIO_PIN_X2)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM3_TIM_CHANNEL1)) ||
(!IS_TIM_CHANNELS(set_struct->TIM_PWM3_TIM_CHANNEL2)))
{
return 1;
}
return 0;
}

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/********************************MODBUS*************************************
Данный файл содержит объявления базовых функции и дефайны для реализации
MODBUS.
Данный файл необходимо подключить в rs_message.h. После подключать rs_message.h
к основному проекту.
***************************************************************************/
#ifndef __PROJ_SETTINGS_H_
#define __PROJ_SETTINGS_H_
#include "stm32f4xx_hal.h"
//--------DEFINES FOR SETTING OF SETTINGS-----------
#define SETTINGS_FLASH_ADDRESS_SHIFT (0x10000)
#define SETTINGS_FLASH_ADDRESS (FLASH_BASE + SETTINGS_FLASH_ADDRESS_SHIFT)
#define EEPROM_BASE
#define SETTINGS_EEPROM_ADDRESS_SHIFT
#define SETTINGS_EEPROM_ADDRESS (EEPROM_BASE + SETTINGS_EEPROM_ADDRESS_SHIFT)
#ifdef USE_EEPROM
#define SETTINGS_ADDRESS SETTINGS_EEPROM_ADDRESS
#else // USE_EEPROM
#define SETTINGS_ADDRESS (SETTINGS_FLASH_ADDRESS)
#endif // USE_EEPROM
//--------------------------------------------------
//------------DEFINES FOR PWM SETTING---------------
// settings defines
#define HZ_TIMER_CTRL 400
#define HZ_TIMER_PWM 1000
// TIM PWM1 SETTINGS
#define PWM_MASTER_TIM_NUMB 4
#define TIMER_PWM_TICKBASE TIM_TickBase_1US
#define TIMER_PWM_AHB_FREQ 72
#define TIMER_PWM1_INSTANCE TIM4
#define TIMER_PWM1_TIM_CHANNEL1 TIM_CHANNEL_1
#define TIMER_PWM1_TIM_CHANNEL2 TIM_CHANNEL_2
#define TIMER_PWM1_GPIOx GPIOD
#define TIMER_PWM1_GPIO_PIN_X1 GPIO_PIN_12
#define TIMER_PWM1_GPIO_PIN_X2 GPIO_PIN_13
// TIM PWM2 SETTINGS
#define TIMER_PWM2_INSTANCE TIM3
#define TIMER_PWM2_TIM_CHANNEL1 TIM_CHANNEL_3
#define TIMER_PWM2_TIM_CHANNEL2 TIM_CHANNEL_4
#define TIMER_PWM2_GPIOx GPIOB
#define TIMER_PWM2_GPIO_PIN_X1 GPIO_PIN_0
#define TIMER_PWM2_GPIO_PIN_X2 GPIO_PIN_1
// TIM PWM3 SETTINGS
#define TIMER_PWM3_INSTANCE TIM1
#define TIMER_PWM3_TIM_CHANNEL1 TIM_CHANNEL_1
#define TIMER_PWM3_TIM_CHANNEL2 TIM_CHANNEL_2
#define TIMER_PWM3_GPIOx GPIOE
#define TIMER_PWM3_GPIO_PIN_X1 GPIO_PIN_9
#define TIMER_PWM3_GPIO_PIN_X2 GPIO_PIN_11
// TIM CTRL SETTINGS
#define TIMER_CTRL_TICKBASE TIM_TickBase_1US
#define TIMER_CTRL_AHB_FREQ 72
// PWM SETTINGS
#define SIN_TABLE_ORIGIN sin_table
#define SIN_TABLE_SIZE_MAX 1000
//--------------------------------------------------
//----------DEFINES FOR MODBUS SETTING--------------
#define MODBUS_UART_NUMB 3 // number of used uart
#define MODBUS_SPEED 115200
#define MODBUS_GPIOX GPIOB
#define MODBUS_GPIO_PIN_RX GPIO_PIN_11
#define MODBUS_GPIO_PIN_TX GPIO_PIN_10
/* accord to this define sets define USED_MB_UART = USARTx */
#define MODBUS_TIM_NUMB 7 // number of used uart
#define MODBUS_TIM_AHB_FREQ 72
/* accord to this define sets define USED_MB_TIM = TIMx */
/* defines for modbus behaviour */
#define MODBUS_DEVICE_ID 1 // number of used uart
#define MODBUS_MAX_TIMEOUT 5000 // is ms
// custom define for size of receive message
//--------------------------------------------------
typedef struct
{
// ctrl periph settings
uint64_t TIM_CTRL_TICKBASE;
uint64_t TIM_CTRL_AHB_FREQ;
// pwm peripth settings
uint64_t TIM_PWM_TICKBASE;
uint64_t TIM_PWM_AHB_FREQ;
// uint64_t TIM_PWM1_INSTANCE;
uint64_t TIM_PWM1_TIM_CHANNEL1;
uint64_t TIM_PWM1_TIM_CHANNEL2;
uint64_t TIM_PWM1_GPIOx;
uint64_t TIM_PWM1_GPIO_PIN_X1;
uint64_t TIM_PWM1_GPIO_PIN_X2;
uint64_t TIM_PWM2_INSTANCE;
uint64_t TIM_PWM2_TIM_CHANNEL1;
uint64_t TIM_PWM2_TIM_CHANNEL2;
uint64_t TIM_PWM2_GPIOx;
uint64_t TIM_PWM2_GPIO_PIN_X1;
uint64_t TIM_PWM2_GPIO_PIN_X2;
uint64_t TIM_PWM3_INSTANCE;
uint64_t TIM_PWM3_TIM_CHANNEL1;
uint64_t TIM_PWM3_TIM_CHANNEL2;
uint64_t TIM_PWM3_GPIOx;
uint64_t TIM_PWM3_GPIO_PIN_X1;
uint64_t TIM_PWM3_GPIO_PIN_X2;
// modbus peripth settings
uint64_t MB_DEVICE_ID;
uint64_t MB_SPEED;
uint64_t MB_GPIOX;
uint64_t MB_GPIO_PIN_RX;
uint64_t MB_GPIO_PIN_TX;
uint64_t MB_MAX_TIMEOUT;
uint64_t MB_TIM_AHB_FREQ;
// uint32_t MB_UART_NUMB;
// uint32_t MB_TIM_NUMB;
}ProjectSettings_TypeDef;
extern ProjectSettings_TypeDef PROJSET;
//#define PROJSET_MEM ((ProjectSettings_TypeDef *)SETTINGS_ADDRESS)
//#define HAL_FLASH_GET_TYPEPROGRAM(_val_) (sizeof(PROJSET_MEM->MB_DEVICE_ID)/2 - 1)
#define HAL_FLASH_GET_TYPEPROGRAM(_val_) FLASH_TYPEPROGRAM_WORD
#define FLASH_WRITE_SETTING(_setting_, _val_) HAL_FLASH_Program(HAL_FLASH_GET_TYPEPROGRAM(_setting_), (uint32_t)(&_setting_), (uint32_t)_val_);
#define STRUCT_WRITE_SETTING(_setting_, _val_) (_setting_ = _val_)
void FillStructWithDefines(void);
void SetFlagUpdateSettingsInMem(void);
void UpdateSettingsInMem(void);
void WriteSettingsToMem(void);
void FillSettingsWithDefines(void);
void CheckSettingsInFLASH(void);
int CheckIsSettingsValid(ProjectSettings_TypeDef *set_struct);
#endif // __PROJ_SETTINGS_H_

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/**
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx
* @{
*/
#ifndef __STM32F1XX_H
#define __STM32F1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F1)
#define STM32F1
#endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.3
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F100xB)
#include "stm32f100xb_matlab.h"
#elif defined(STM32F100xE)
#include "stm32f100xe_matlab.h"
#elif defined(STM32F101x6)
#include "stm32f101x6_matlab.h"
#elif defined(STM32F101xB)
#include "stm32f101xb_matlab.h"
#elif defined(STM32F101xE)
#include "stm32f101xe_matlab.h"
#elif defined(STM32F101xG)
#include "stm32f101xg_matlab.h"
#elif defined(STM32F102x6)
#include "stm32f102x6_matlab.h"
#elif defined(STM32F102xB)
#include "stm32f102xb_matlab.h"
#elif defined(STM32F103x6)
#include "stm32f103x6_matlab.h"
#elif defined(STM32F103xB)
#include "stm32f103xb_matlab.h"
#elif defined(STM32F103xE)
#include "stm32f103xe_matlab.h"
#elif defined(STM32F103xG)
#include "stm32f103xg_matlab.h"
#elif defined(STM32F105xC)
#include "stm32f105xc_matlab.h"
#elif defined(STM32F107xC)
#include "stm32f107xc_matlab.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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#define __disable_irq()
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __IO
#define __IO volatile
#endif
#ifndef __inline
#define __inline inline
#endif
#ifndef __NOINLINE
#define __NOINLINE __declspec(noinline)
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __declspec(selectany)
// #define __weak __WEAK
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
//#define __CLZ (uint8_t)clz
//
//#define __CTZ (uint8_t)ctz
#define __CLZ
#define __CTZ
#define __RBIT
#ifndef __weak
#define __weak
#endif
#define __DSB()
#define __ISB()
#define __NOP()
#define __WFI()
#define __SEV()
#define __WFE()
#define __DMB()

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MCU_STM32F1xx_Matlab/Drivers/CMSIS/core_cm1_matlab.h Normal file
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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 04. June 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GENERIC
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
#else
uint32_t RESERVED1[1U];
#endif
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29U];
__OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
typedef struct _cortex_memory
{
uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
}MCU_CortexMemoryTypeDef;
extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_GENERIC */

55
MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h → MCU_STM32F1xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h
View File

@@ -1,18 +1,10 @@
/**
**************************************************************************
* @file core_cm4_matlab.h
* @brief Заголовочный файл ядра Core CM4 для MATLAB.
**************************************************************************
@details
/************************************************************************
Данный файл является копией core_cm4.h, только первые ~160 строк, которые
определяют компилятор АРМ, удалены.
МАТЛАБ компилирует через код через комплилятор MSVC для блока S-Function
Также добавлена инклюд с имитирацией памяти ядра (~10)
Также добавлена структура имитирующая память ядра (~1360)
**************************************************************************/
#ifndef __CMSIS_GENERIC
#include "stm32f407xx_matlab_memory.h"
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
@@ -1352,7 +1344,50 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
typedef struct _cortex_memory
{
uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
}MCU_CortexMemoryTypeDef;
extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
/*@} */

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