Всякие фиксы модели и заготовки для АЦП

И почему то все равно MATLAB намертво блокирует mingw64.... Приходится перезапускать матлаб для перекомпиляции
This commit is contained in:
Razvalyaev 2025-11-09 21:04:52 +03:00
parent be84043f18
commit 79ff2667c4
74 changed files with 2371 additions and 609 deletions

3
.gitignore vendored
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@ -58,3 +58,6 @@ JLinkLog.txt
# VS Code Generated Files
/.vs/
/MATLAB/MCU.exp
/MATLAB/MCU.lib
/MATLAB/MCU.mexw64.manifest

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@ -262,8 +262,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -310,8 +310,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -215,8 +215,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -220,8 +220,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -284,8 +284,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -290,8 +290,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -218,8 +218,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -223,8 +223,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -287,8 +287,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -293,8 +293,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct
@ -592,7 +592,7 @@ typedef struct _memory
{
//uint8_t RESERVED[FLASH_BASE_SHIFT];
uint8_t FLASH_BASE[FLASH_SIZE];
uint8_t FLASH_BASE[10];
uint8_t FLASH_BANK1_END[10];
uint8_t SRAM_BASE[SRAM_SIZE];
uint8_t SRAM_BB_BASE[SRAM_SIZE];

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@ -362,8 +362,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -362,8 +362,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -361,8 +361,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -363,8 +363,8 @@ typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
__IO uint64_t CPAR;
__IO uint64_t CMAR;
} DMA_Channel_TypeDef;
typedef struct

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@ -223,9 +223,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -223,9 +223,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -334,9 +334,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -358,9 +358,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -241,9 +241,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -241,9 +241,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -238,9 +238,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -224,9 +224,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -344,9 +344,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -345,9 +345,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -383,9 +383,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -333,9 +333,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -354,9 +354,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -384,9 +384,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -360,9 +360,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -362,9 +362,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -361,9 +361,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -363,9 +363,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -372,9 +372,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -364,9 +364,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -365,9 +365,9 @@ typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint64_t PAR; /*!< DMA stream x peripheral address register */
__IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;

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@ -91,10 +91,15 @@
#define __CLZ
#define __CTZ
#define __RBIT
#ifdef __MINGW64__
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#else
#ifndef __weak
#define __weak
#endif
#endif
#define __DSB()
#define __ISB()
#define __NOP()

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@ -1,4 +1,5 @@
#include "stm32_matlab_adc.h"
#include "stm32_matlab_dma.h"
#include <string.h>
@ -22,19 +23,26 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
if (!(ADCx->CR2 & ADC_CR2_ADON)) return;
// Start conversion on SWSTART
// ПЕРВОЕ: Проверка внешнего триггера (для режима по триггеру)
if (!(ADCx->CR2 & ADC_CR2_CONT)) { // Только если не continuous mode
ADC_Check_External_Trigger(ADCx, ADCS);
}
// ВТОРОЕ: Software trigger
if (ADCx->CR2 & ADC_CR2_SWSTART) {
ADC_Start_Conversion(ADCx, ADCS);
ADCx->CR2 &= ~ADC_CR2_SWSTART;
}
// Handle ongoing conversion - ïðîâåðÿåì ïî ôëàãó ñîñòîÿíèÿ
// ТРЕТЬЕ: Обработка текущего преобразования
if (ADCS->conversion_time_elapsed >= 0) {
ADCS->conversion_time_elapsed += ADCS->simulation_step;
double total_time = ADC_Get_Total_Conversion_Time(ADCx, ADCS);
// ИСПОЛЬЗУЕМ ОБЩЕЕ ВРЕМЯ ДЛЯ ВСЕЙ ПОСЛЕДОВАТЕЛЬНОСТИ
double total_time = ADC_Get_Total_Sequence_Time(ADCx, ADCS);
if (ADCS->conversion_time_elapsed >= total_time) {
ADC_Complete_Conversion(ADCx, ADCS);
ADC_Complete_Conversion(ADCx, ADCS); // Обрабатываем ВСЕ каналы
// Continuous mode auto-restart
if (ADCx->CR2 & ADC_CR2_CONT) {
@ -42,19 +50,18 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
}
}
}
}
void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
// Îïðåäåëÿåì êàíàë äëÿ êîíâåðñèè
// Определяем канал для конверсии
if (ADCx->CR1 & ADC_CR1_SCAN) {
// Ðåæèì ñêàíèðîâàíèÿ
// Режим сканирования
ADCS->current_rank = 0;
ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, 0);
}
else {
// Îäèíî÷íûé êàíàë
// Одиночный канал
ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, 0);
}
@ -63,81 +70,210 @@ void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
void ADC_Complete_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
// Êîíâåðòèðóåì àíàëîãîâîå çíà÷åíèå â öèôðîâîå
uint32_t seq_len = ADC_Get_Sequence_Length(ADCx);
// Обрабатываем ВСЕ каналы последовательности за один вызов
for (uint32_t rank = 0; rank < seq_len; rank++) {
uint32_t channel = ADC_Get_Sequence_Channel(ADCx, rank);
// 1. Конвертируем один канал
double analog_val = 0;
if (ADCS->channel_connected[ADCS->current_channel]) {
analog_val = ADCS->channel_values[ADCS->current_channel];
if (ADCS->channel_connected[channel]) {
analog_val = ADCS->channel_values[channel];
}
if (analog_val < 0)
analog_val = 0;
if (analog_val > 3.3)
analog_val = 3.3;
if (analog_val < 0) analog_val = 0;
if (analog_val > 3.3) analog_val = 3.3;
// Ñíà÷àëà âû÷èñëÿåì çíà÷åíèå ÀÖÏ
// Вычисляем значение АЦП
ADCS->last_conversion_value = (uint16_t)((analog_val / 3.3) * 4095.0);
// Ïîòîì äîáàâëÿåì øóì â LSB
// Добавляем шум
int32_t noisy_value = (int32_t)ADCS->last_conversion_value + (rand() % (2 * ADC_NOISE_LSB + 1)) - ADC_NOISE_LSB;
// Ñàòóðàöèÿ öèôðîâîãî çíà÷åíèÿ
if (noisy_value < 0) noisy_value = 0;
if (noisy_value > 4095) noisy_value = 4095;
ADCS->last_conversion_value = (uint16_t)noisy_value;
// Çàïèñûâàåì â DR
// 2. Записываем в DR
ADCx->DR = ADCS->last_conversion_value;
// Óñòàíàâëèâàåì ôëàã EOC
// 3. Устанавливаем флаг EOC
ADCx->SR |= ADC_SR_EOC;
// Îáðàáîòêà DMA
// 4. СРАЗУ вызываем DMA для этой конверсии
if (ADCx->CR2 & ADC_CR2_DMA) {
ADC_DMA_Transfer(ADCx, ADCS);
if (ADCx == ADC3) {
DMA_Sim_Transfer(DMA2, 0); // Выполняем одну передачу
}
// Îáðàáîòêà ñêàíèðîâàíèÿ
if (ADCx->CR1 & ADC_CR1_SCAN) {
ADCS->current_rank++;
uint32_t seq_len = ADC_Get_Sequence_Length(ADCx);
if (ADCS->current_rank < seq_len) {
// Ñëåäóþùèé êàíàë â ïîñëåäîâàòåëüíîñòè
ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, ADCS->current_rank);
ADCS->conversion_time_elapsed = 0;
return;
else if (ADCx == ADC1) {
DMA_Sim_Transfer(DMA2, 4); // Для ADC1
}
else {
// Êîíåö ïîñëåäîâàòåëüíîñòè
#ifdef ADC_SR_EOS
ADCx->SR |= ADC_SR_EOS;
#endif
}
}
ADCS->conversion_time_elapsed = 0;
// Устанавливаем EOS в конце последовательности
ADCx->SR |= ADC_SR_EOC;
ADCS->conversion_time_elapsed = -1;
}
/////////////////////////////---TIMER TRIGGER SUPPORT---//////////////////////////
uint8_t ADC_Check_Timer_Trigger(ADC_TypeDef* ADCx, uint32_t trigger_source)
{
// Анализируем источник триггера из регистров ADC
switch (trigger_source) {
#ifdef ADC_EXTERNALTRIGCONV_T2_TRGO
case ADC_EXTERNALTRIGCONV_T2_TRGO:
return Slave_Channels.TIM2_TRGO;
#endif
#ifdef ADC_EXTERNALTRIGCONV_T3_TRGO
case ADC_EXTERNALTRIGCONV_T3_TRGO:
return Slave_Channels.TIM3_TRGO;
#endif
#ifdef ADC_EXTERNALTRIGCONV_T8_TRGO
case ADC_EXTERNALTRIGCONV_T8_TRGO:
return Slave_Channels.TIM8_TRGO;
#endif
#ifdef ADC_EXTERNALTRIGCONV_T1_CC1
case ADC_EXTERNALTRIGCONV_T1_CC1:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T1_CC2
case ADC_EXTERNALTRIGCONV_T1_CC2:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T1_CC3
case ADC_EXTERNALTRIGCONV_T1_CC3:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T2_CC2
case ADC_EXTERNALTRIGCONV_T2_CC2:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T2_CC3
case ADC_EXTERNALTRIGCONV_T2_CC3:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T2_CC4
case ADC_EXTERNALTRIGCONV_T2_CC4:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T3_CC1
case ADC_EXTERNALTRIGCONV_T3_CC1:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T4_CC4
case ADC_EXTERNALTRIGCONV_T4_CC4:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T5_CC1
case ADC_EXTERNALTRIGCONV_T5_CC1:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T5_CC2
case ADC_EXTERNALTRIGCONV_T5_CC2:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T5_CC3
case ADC_EXTERNALTRIGCONV_T5_CC3:
#endif
#ifdef ADC_EXTERNALTRIGCONV_T8_CC1
case ADC_EXTERNALTRIGCONV_T8_CC1:
#endif
#ifdef ADC_EXTERNALTRIGCONV_Ext_IT11
case ADC_EXTERNALTRIGCONV_Ext_IT11:
#endif
default:
return 0;
}
}
void ADC_Check_External_Trigger(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
#ifdef STM32F1
// Для STM32F1 проверяем бит EXTTRIG
if (!(ADCx->CR2 & ADC_CR2_EXTTRIG)) return;
// Получаем источник триггера и фронт
uint32_t trigger_source = (ADCx->CR2 & ADC_CR2_EXTSEL); // Для F1 EXTSEL[2:0] биты 19:17
uint32_t trigger_edge = (ADCx->CR2 & ADC_CR2_EXTTRIG) ? 1 : 0; // Для F1 просто включен/выключен
#elif defined(STM32F4)
// Для STM32F4 проверяем EXTEN и EXTSEL
if (!(ADCx->CR2 & ADC_CR2_EXTEN)) return; // Для F4 проверяем EXTEN
// Получаем источник триггера и фронт
uint32_t trigger_source = (ADCx->CR2 & ADC_CR2_EXTSEL);
uint32_t trigger_edge = (ADCx->CR2 & ADC_CR2_EXTEN);
#else
return; // Неподдерживаемая платформа
#endif
uint8_t current_trigger_state = ADC_Check_Timer_Trigger(ADCx, trigger_source);
uint8_t trigger_occurred = 0;
#ifdef STM32F1
// Для F1 - простой rising edge при наличии триггера
if (trigger_edge) {
trigger_occurred = current_trigger_state && !ADCS->last_trigger_state;
}
#endif
#ifdef STM32F4
switch (trigger_edge)
{
case ADC_EXTERNALTRIGCONVEDGE_RISING:
trigger_occurred = current_trigger_state && !ADCS->last_trigger_state;
break;
case ADC_EXTERNALTRIGCONVEDGE_FALLING:
trigger_occurred = !current_trigger_state && ADCS->last_trigger_state;
break;
case ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING:
trigger_occurred = (current_trigger_state && !ADCS->last_trigger_state) ||
(!current_trigger_state && ADCS->last_trigger_state);
break;
default:
break;
}
#endif
if (trigger_occurred) {
ADC_Start_Conversion(ADCx, ADCS);
}
ADCS->last_trigger_state = current_trigger_state;
}
/////////////////////////////---REGISTER-BASED FUNCTIONS---///////////////////
double ADC_Get_Total_Conversion_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
// Ïîëó÷àåì sampling time èç ðåãèñòðîâ
// Получаем sampling time из регистров
uint32_t sampling_cycles = ADC_Get_Sampling_Cycles(ADCx, ADCS->current_channel);
// Conversion cycles ôèêñèðîâàíû äëÿ ðàçðåøåíèÿ
uint32_t conversion_cycles = 12; // Äëÿ 12-bit
// Conversion cycles фиксированы для разрешения
uint32_t conversion_cycles = 12; // Для 12-bit
double total_cycles = sampling_cycles + conversion_cycles;
double adc_clock = ADCS->adc_clock_freq; // ×àñòîòà øèíû
double adc_clock = ADCS->adc_clock_freq; // Частота шины
return total_cycles / adc_clock;
}
double ADC_Get_Total_Sequence_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
uint32_t total_cycles = 0;
uint32_t seq_len = ADC_Get_Sequence_Length(ADCx);
for (uint32_t rank = 0; rank < seq_len; rank++) {
uint32_t channel = ADC_Get_Sequence_Channel(ADCx, rank);
uint32_t sampling_cycles = ADC_Get_Sampling_Cycles(ADCx, channel);
total_cycles += sampling_cycles + 12; // sampling + conversion
}
return total_cycles / ADCS->adc_clock_freq;
}
uint32_t ADC_Get_Sampling_Cycles(ADC_TypeDef* ADCx, uint32_t channel)
{
// Ïîëó÷àåì sampling time èç SMPR1/SMPR2
// Получаем sampling time из SMPR1/SMPR2
uint32_t smpr_code;
if (channel <= 9) {
smpr_code = (ADCx->SMPR2 >> (channel * 3)) & 0x7;
@ -176,7 +312,7 @@ uint32_t ADC_Get_Sequence_Channel(ADC_TypeDef* ADCx, uint32_t rank)
}
/////////////////////////////---DMA FUNCTIONS---///////////////////////////////
void ADC_DMA_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
void ADC_DMA_Sim_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS)
{
if (!ADCS->dma_buffer || ADCS->dma_buffer_size == 0) return;

View File

@ -5,11 +5,11 @@
#ifdef STM32F1
#define ADC_NOISE_LSB 10 // Шум в LSB (квантах АЦП)
#define ADC_NOISE_LSB 30 // Большой шум STMF103 в LSB (квантах АЦП)
#endif
#ifdef STM32F4
#define ADC_NOISE_LSB 2 // Шум в LSB (квантах АЦП)
#define ADC_NOISE_LSB 10 // Шум в LSB (квантах АЦП)
#endif
/////////////////////////////---STRUCTURES---///////////////////////////
@ -32,6 +32,11 @@ struct ADC_Sim
// Timing
double simulation_step;
double adc_clock_freq;
// Добавьте для поддержки триггеров
uint8_t external_trigger_enabled;
uint32_t trigger_source;
uint8_t last_trigger_state;
};
///////////////////////////////////////////////////////////////////////
@ -42,11 +47,13 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
void ADC_Complete_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
void ADC_Check_External_Trigger(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
double ADC_Get_Total_Conversion_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
double ADC_Get_Total_Sequence_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
uint32_t ADC_Get_Sampling_Cycles(ADC_TypeDef* ADCx, uint32_t channel);
uint32_t ADC_Get_Sequence_Length(ADC_TypeDef* ADCx);
uint32_t ADC_Get_Sequence_Channel(ADC_TypeDef* ADCx, uint32_t rank);
void ADC_DMA_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
void ADC_DMA_Sim_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS);
void ADC_Set_Channel_Value(ADC_TypeDef* ADCx, uint32_t channel, double voltage);
void ADC_SIM_DEINIT(void);

View File

@ -0,0 +1,591 @@
#include "stm32_matlab_dma.h"
#include <string.h>
// DMA stream simulation structures
#ifdef USE_DMA1
struct DMA_Stream_Sim dma1_stream0s;
struct DMA_Stream_Sim dma1_stream1s;
struct DMA_Stream_Sim dma1_stream2s;
struct DMA_Stream_Sim dma1_stream3s;
struct DMA_Stream_Sim dma1_stream4s;
struct DMA_Stream_Sim dma1_stream5s;
struct DMA_Stream_Sim dma1_stream6s;
struct DMA_Stream_Sim dma1_stream7s;
#endif
#ifdef USE_DMA2
struct DMA_Stream_Sim dma2_stream0s;
struct DMA_Stream_Sim dma2_stream1s;
struct DMA_Stream_Sim dma2_stream2s;
struct DMA_Stream_Sim dma2_stream3s;
struct DMA_Stream_Sim dma2_stream4s;
struct DMA_Stream_Sim dma2_stream5s;
struct DMA_Stream_Sim dma2_stream6s;
struct DMA_Stream_Sim dma2_stream7s;
#endif
void DMA_Call_IRQHandller(DMA_TypeDef* DMAx, uint32_t stream);
// Модифицируем основную функцию выполнения передачи
void DMA_Sim_Transfer(DMA_TypeDef* DMAx, uint32_t stream)
{
struct DMA_Stream_Sim* stream_sim = DMA_Get_Stream_Sim(DMAx, stream);
if (!stream_sim) return;
// Проверяем включен ли stream в регистрах
uint8_t hardware_enabled = DMA_Is_Stream_Enabled(DMAx, stream);
if (!hardware_enabled) {
// Если аппаратно выключен, сбрасываем состояние
if (stream_sim->enabled) {
memset(stream_sim, 0, sizeof(struct DMA_Stream_Sim));
}
return;
}
// Если аппаратно включен, инициализируем если нужно
if (!stream_sim->enabled) {
stream_sim->peripheral_address = DMA_Get_Peripheral_Address(DMAx, stream);
stream_sim->memory_address = DMA_Get_Memory_Address(DMAx, stream);
stream_sim->buffer_size = DMA_Get_Buffer_Size(DMAx, stream);
stream_sim->circular_mode = DMA_Get_Circular_Mode(DMAx, stream);
stream_sim->data_size = DMA_Get_DataSize(DMAx, stream); // Сохраняем размер данных
stream_sim->current_index = 0;
stream_sim->transfer_complete = 0;
stream_sim->enabled = 1;
stream_sim->transfer_enabled = 1;
}
// Проверяем нужно ли выполнить передачу
if (!stream_sim->transfer_enabled) return;
if (!stream_sim->peripheral_address || !stream_sim->memory_address) return;
// ВЫПОЛНЯЕМ ПЕРЕДАЧУ С УЧЕТОМ РАЗМЕРА ДАННЫХ
switch (stream_sim->data_size) {
case 1: // 8-bit data
{
uint8_t current_value = *(uint8_t*)stream_sim->peripheral_address;
((uint8_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value;
}
break;
case 2: // 16-bit data
{
uint16_t current_value = *(uint16_t*)stream_sim->peripheral_address;
((uint16_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value;
}
break;
case 4: // 32-bit data
{
uint32_t current_value = *(uint32_t*)stream_sim->peripheral_address;
((uint32_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value;
}
break;
default: // По умолчанию 8-bit
{
uint8_t current_value = *(uint8_t*)stream_sim->peripheral_address;
((uint8_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value;
}
break;
}
stream_sim->current_index++;
// Проверяем завершение передачи
if (stream_sim->current_index >= stream_sim->buffer_size) {
stream_sim->transfer_complete = 1;
if (stream_sim->circular_mode) {
stream_sim->current_index = 0;
} else {
stream_sim->transfer_enabled = 0;
stream_sim->enabled = 0;
DMA_Call_IRQHandller(DMAx, stream);
}
}
}
/////////////////////////////---HELPER FUNCTIONS---//////////////////////////
struct DMA_Stream_Sim* DMA_Get_Stream_Sim(DMA_TypeDef* DMAx, uint32_t stream)
{
#ifdef USE_DMA1
if (DMAx == DMA1) {
switch (stream) {
case 0: return &dma1_stream0s;
case 1: return &dma1_stream1s;
case 2: return &dma1_stream2s;
case 3: return &dma1_stream3s;
case 4: return &dma1_stream4s;
case 5: return &dma1_stream5s;
case 6: return &dma1_stream6s;
case 7: return &dma1_stream7s;
}
}
#endif
#ifdef USE_DMA2
if (DMAx == DMA2) {
switch (stream) {
case 0: return &dma2_stream0s;
case 1: return &dma2_stream1s;
case 2: return &dma2_stream2s;
case 3: return &dma2_stream3s;
case 4: return &dma2_stream4s;
case 5: return &dma2_stream5s;
case 6: return &dma2_stream6s;
case 7: return &dma2_stream7s;
}
}
#endif
return NULL;
}
uint8_t DMA_Is_Stream_Enabled(DMA_TypeDef* DMAx, uint32_t stream)
{
// Проверяем регистры DMA чтобы определить включен ли stream
#ifdef STM32F1
if (DMAx == DMA1) {
volatile uint32_t* cr_reg = NULL;
switch (stream) {
case 0: cr_reg = &DMA1_Channel1->CCR; break;
case 1: cr_reg = &DMA1_Channel2->CCR; break;
case 2: cr_reg = &DMA1_Channel3->CCR; break;
case 3: cr_reg = &DMA1_Channel4->CCR; break;
case 4: cr_reg = &DMA1_Channel5->CCR; break;
case 5: cr_reg = &DMA1_Channel6->CCR; break;
case 6: cr_reg = &DMA1_Channel7->CCR; break;
}
if (cr_reg) {
return (*cr_reg & DMA_CCR_EN) != 0;
}
}
#elif defined(STM32F4)
if (DMAx == DMA1) {
volatile uint32_t* cr_reg = NULL;
switch (stream) {
case 0: cr_reg = &DMA1_Stream0->CR; break;
case 1: cr_reg = &DMA1_Stream1->CR; break;
case 2: cr_reg = &DMA1_Stream2->CR; break;
case 3: cr_reg = &DMA1_Stream3->CR; break;
case 4: cr_reg = &DMA1_Stream4->CR; break;
case 5: cr_reg = &DMA1_Stream5->CR; break;
case 6: cr_reg = &DMA1_Stream6->CR; break;
case 7: cr_reg = &DMA1_Stream7->CR; break;
}
if (cr_reg) {
return (*cr_reg & DMA_SxCR_EN) != 0;
}
}
else if (DMAx == DMA2) {
volatile uint32_t* cr_reg = NULL;
switch (stream) {
case 0: cr_reg = &DMA2_Stream0->CR; break;
case 1: cr_reg = &DMA2_Stream1->CR; break;
case 2: cr_reg = &DMA2_Stream2->CR; break;
case 3: cr_reg = &DMA2_Stream3->CR; break;
case 4: cr_reg = &DMA2_Stream4->CR; break;
case 5: cr_reg = &DMA2_Stream5->CR; break;
case 6: cr_reg = &DMA2_Stream6->CR; break;
case 7: cr_reg = &DMA2_Stream7->CR; break;
}
if (cr_reg) {
return (*cr_reg & DMA_SxCR_EN) != 0;
}
}
#endif
return 0;
}
uint32_t* DMA_Get_Peripheral_Address(DMA_TypeDef* DMAx, uint32_t stream)
{
// Получаем адрес периферии из регистров DMA
#ifdef STM32F1
if (DMAx == DMA1) {
switch (stream) {
case 0: return (uint64_t*)DMA1_Channel1->CPAR;
case 1: return (uint64_t*)DMA1_Channel2->CPAR;
case 2: return (uint64_t*)DMA1_Channel3->CPAR;
case 3: return (uint64_t*)DMA1_Channel4->CPAR;
case 4: return (uint64_t*)DMA1_Channel5->CPAR;
case 5: return (uint64_t*)DMA1_Channel6->CPAR;
case 6: return (uint64_t*)DMA1_Channel7->CPAR;
}
}
#elif defined(STM32F4)
if (DMAx == DMA1) {
volatile uint64_t* par_reg = NULL;
switch (stream) {
case 0: par_reg = &DMA1_Stream0->PAR; break;
case 1: par_reg = &DMA1_Stream1->PAR; break;
case 2: par_reg = &DMA1_Stream2->PAR; break;
case 3: par_reg = &DMA1_Stream3->PAR; break;
case 4: par_reg = &DMA1_Stream4->PAR; break;
case 5: par_reg = &DMA1_Stream5->PAR; break;
case 6: par_reg = &DMA1_Stream6->PAR; break;
case 7: par_reg = &DMA1_Stream7->PAR; break;
}
if (par_reg) {
return (uint64_t*)*par_reg;
}
}
else if (DMAx == DMA2) {
volatile uint64_t* par_reg = NULL;
switch (stream) {
case 0: par_reg = &DMA2_Stream0->PAR; break;
case 1: par_reg = &DMA2_Stream1->PAR; break;
case 2: par_reg = &DMA2_Stream2->PAR; break;
case 3: par_reg = &DMA2_Stream3->PAR; break;
case 4: par_reg = &DMA2_Stream4->PAR; break;
case 5: par_reg = &DMA2_Stream5->PAR; break;
case 6: par_reg = &DMA2_Stream6->PAR; break;
case 7: par_reg = &DMA2_Stream7->PAR; break;
}
if (par_reg) {
return (uint64_t*)*par_reg;
}
}
#endif
return NULL;
}
uint32_t* DMA_Get_Memory_Address(DMA_TypeDef* DMAx, uint32_t stream)
{
// Получаем адрес памяти из регистров DMA
#ifdef STM32F1
if (DMAx == DMA1) {
switch (stream) {
case 0: return (uint64_t*)DMA1_Channel1->CPAR;
case 1: return (uint64_t*)DMA1_Channel2->CPAR;
case 2: return (uint64_t*)DMA1_Channel3->CPAR;
case 3: return (uint64_t*)DMA1_Channel4->CPAR;
case 4: return (uint64_t*)DMA1_Channel5->CPAR;
case 5: return (uint64_t*)DMA1_Channel6->CPAR;
case 6: return (uint64_t*)DMA1_Channel7->CPAR;
}
}
#elif defined(STM32F4)
if (DMAx == DMA1) {
volatile uint64_t* mar_reg = NULL;
switch (stream) {
case 0: mar_reg = &DMA1_Stream0->M0AR; break;
case 1: mar_reg = &DMA1_Stream1->M0AR; break;
case 2: mar_reg = &DMA1_Stream2->M0AR; break;
case 3: mar_reg = &DMA1_Stream3->M0AR; break;
case 4: mar_reg = &DMA1_Stream4->M0AR; break;
case 5: mar_reg = &DMA1_Stream5->M0AR; break;
case 6: mar_reg = &DMA1_Stream6->M0AR; break;
case 7: mar_reg = &DMA1_Stream7->M0AR; break;
}
if (mar_reg) {
return (uint64_t*)*mar_reg;
}
}
else if (DMAx == DMA2) {
volatile uint64_t* mar_reg = NULL;
switch (stream) {
case 0: mar_reg = &DMA2_Stream0->M0AR; break;
case 1: mar_reg = &DMA2_Stream1->M0AR; break;
case 2: mar_reg = &DMA2_Stream2->M0AR; break;
case 3: mar_reg = &DMA2_Stream3->M0AR; break;
case 4: mar_reg = &DMA2_Stream4->M0AR; break;
case 5: mar_reg = &DMA2_Stream5->M0AR; break;
case 6: mar_reg = &DMA2_Stream6->M0AR; break;
case 7: mar_reg = &DMA2_Stream7->M0AR; break;
}
if (mar_reg) {
return (uint64_t*)*mar_reg;
}
}
#endif
return NULL;
}
uint32_t DMA_Get_Buffer_Size(DMA_TypeDef* DMAx, uint32_t stream)
{
// Получаем размер буфера из регистров DMA
#ifdef STM32F1
if (DMAx == DMA1) {
switch (stream) {
case 0: return DMA1_Channel1->CNDTR;
case 1: return DMA1_Channel2->CNDTR;
case 2: return DMA1_Channel3->CNDTR;
case 3: return DMA1_Channel4->CNDTR;
case 4: return DMA1_Channel5->CNDTR;
case 5: return DMA1_Channel6->CNDTR;
case 6: return DMA1_Channel7->CNDTR;
}
}
#elif defined(STM32F4)
if (DMAx == DMA1) {
volatile uint64_t* mar_reg = NULL;
switch (stream) {
case 0: mar_reg = &DMA1_Stream0->NDTR; break;
case 1: mar_reg = &DMA1_Stream1->NDTR; break;
case 2: mar_reg = &DMA1_Stream2->NDTR; break;
case 3: mar_reg = &DMA1_Stream3->NDTR; break;
case 4: mar_reg = &DMA1_Stream4->NDTR; break;
case 5: mar_reg = &DMA1_Stream5->NDTR; break;
case 6: mar_reg = &DMA1_Stream6->NDTR; break;
case 7: mar_reg = &DMA1_Stream7->NDTR; break;
}
if (mar_reg) {
return (uint64_t*)*mar_reg;
}
}
else if (DMAx == DMA2) {
volatile uint64_t* mar_reg = NULL;
switch (stream) {
case 0: mar_reg = &DMA2_Stream0->NDTR; break;
case 1: mar_reg = &DMA2_Stream1->NDTR; break;
case 2: mar_reg = &DMA2_Stream2->NDTR; break;
case 3: mar_reg = &DMA2_Stream3->NDTR; break;
case 4: mar_reg = &DMA2_Stream4->NDTR; break;
case 5: mar_reg = &DMA2_Stream5->NDTR; break;
case 6: mar_reg = &DMA2_Stream6->NDTR; break;
case 7: mar_reg = &DMA2_Stream7->NDTR; break;
}
if (mar_reg) {
return (uint64_t*)*mar_reg;
}
}
#endif
return 0;
}
uint8_t DMA_Get_Circular_Mode(DMA_TypeDef* DMAx, uint32_t stream)
{
// Проверяем циклический режим
#ifdef STM32F1
if (DMAx == DMA1) {
switch (stream) {
case 0: return (DMA1_Channel1->CCR & DMA_CCR_CIRC) != 0;
case 1: return (DMA1_Channel2->CCR & DMA_CCR_CIRC) != 0;
case 2: return (DMA1_Channel3->CCR & DMA_CCR_CIRC) != 0;
case 3: return (DMA1_Channel4->CCR & DMA_CCR_CIRC) != 0;
case 4: return (DMA1_Channel5->CCR & DMA_CCR_CIRC) != 0;
case 5: return (DMA1_Channel6->CCR & DMA_CCR_CIRC) != 0;
case 6: return (DMA1_Channel7->CCR & DMA_CCR_CIRC) != 0;
}
}
if (DMAx == DMA1) {
switch (stream) {
case 0: return (DMA1_Stream1->CR & DMA_SxCR_CIRC) != 0;
case 1: return (DMA1_Stream11->CR & DMA_SxCR_CIRC) != 0;
case 2: return (DMA1_Stream13->CR & DMA_SxCR_CIRC) != 0;
case 3: return (DMA1_Stream14->CR & DMA_SxCR_CIRC) != 0;
case 4: return (DMA1_Stream15->CR & DMA_SxCR_CIRC) != 0;
case 5: return (DMA1_Stream16->CR & DMA_SxCR_CIRC) != 0;
case 6: return (DMA1_Stream17->CR & DMA_SxCR_CIRC) != 0;
}
}
#elif defined(STM32F4)
if (DMAx == DMA1 || DMAx == DMA2) {
volatile uint32_t* cr_reg = NULL;
switch (stream) {
case 0: return (DMA2_Stream1->CR & DMA_SxCR_CIRC) != 0;
case 1: return (DMA2_Stream1->CR & DMA_SxCR_CIRC) != 0;
case 2: return (DMA2_Stream3->CR & DMA_SxCR_CIRC) != 0;
case 3: return (DMA2_Stream4->CR & DMA_SxCR_CIRC) != 0;
case 4: return (DMA2_Stream5->CR & DMA_SxCR_CIRC) != 0;
case 5: return (DMA2_Stream6->CR & DMA_SxCR_CIRC) != 0;
case 6: return (DMA2_Stream7->CR & DMA_SxCR_CIRC) != 0;
}
}
#endif
return 0;
}
// функцию для определения размера данных DMA
uint32_t DMA_Get_DataSize(DMA_TypeDef* DMAx, uint32_t stream)
{
#ifdef STM32F4
if (DMAx == DMA1 || DMAx == DMA2) {
volatile uint32_t* cr_reg = NULL;
// Получаем регистр CR для соответствующего потока
if (DMAx == DMA1) {
switch (stream) {
case 0: cr_reg = &DMA1_Stream0->CR; break;
case 1: cr_reg = &DMA1_Stream1->CR; break;
case 2: cr_reg = &DMA1_Stream2->CR; break;
case 3: cr_reg = &DMA1_Stream3->CR; break;
case 4: cr_reg = &DMA1_Stream4->CR; break;
case 5: cr_reg = &DMA1_Stream5->CR; break;
case 6: cr_reg = &DMA1_Stream6->CR; break;
case 7: cr_reg = &DMA1_Stream7->CR; break;
}
}
else if (DMAx == DMA2) {
switch (stream) {
case 0: cr_reg = &DMA2_Stream0->CR; break;
case 1: cr_reg = &DMA2_Stream1->CR; break;
case 2: cr_reg = &DMA2_Stream2->CR; break;
case 3: cr_reg = &DMA2_Stream3->CR; break;
case 4: cr_reg = &DMA2_Stream4->CR; break;
case 5: cr_reg = &DMA2_Stream5->CR; break;
case 6: cr_reg = &DMA2_Stream6->CR; break;
case 7: cr_reg = &DMA2_Stream7->CR; break;
}
}
if (cr_reg) {
uint32_t psize = (*cr_reg & DMA_SxCR_PSIZE);
// Определяем размер данных на основе битов PSIZE
switch (psize) {
case DMA_PDATAALIGN_BYTE: // 00: Byte alignment (8-bit)
return 1;
case DMA_PDATAALIGN_HALFWORD: // 01: HalfWord alignment (16-bit)
return 2;
case DMA_PDATAALIGN_WORD: // 10: Word alignment (32-bit)
return 4;
default:
return 1; // По умолчанию байт
}
}
}
#elif defined(STM32F1)
// Для STM32F1 логика может отличаться
if (DMAx == DMA1) {
volatile uint32_t* ccr_reg = NULL;
switch (stream) {
case 0: ccr_reg = &DMA1_Channel1->CCR; break;
case 1: ccr_reg = &DMA1_Channel2->CCR; break;
case 2: ccr_reg = &DMA1_Channel3->CCR; break;
case 3: ccr_reg = &DMA1_Channel4->CCR; break;
case 4: ccr_reg = &DMA1_Channel5->CCR; break;
case 5: ccr_reg = &DMA1_Channel6->CCR; break;
case 6: ccr_reg = &DMA1_Channel7->CCR; break;
}
if (ccr_reg) {
// В STM32F1 размер определяется битами MSIZE[1:0] и PSIZE[1:0]
uint32_t size_bits = (*ccr_reg & (DMA_CCR_MSIZE | DMA_CCR_PSIZE));
// Упрощенная логика - обычно размеры памяти и периферии совпадают
if (size_bits & 0x0200) return 4; // Word (32-bit)
if (size_bits & 0x0100) return 2; // HalfWord (16-bit)
return 1; // Byte (8-bit)
}
}
#endif
return 1; // По умолчанию 1 байт
}
__weak void DMA1_Stream0_IRQHandler(void) {}
__weak void DMA1_Stream1_IRQHandler(void) {}
__weak void DMA1_Stream2_IRQHandler(void) {}
__weak void DMA1_Stream3_IRQHandler(void) {}
__weak void DMA1_Stream4_IRQHandler(void) {}
__weak void DMA1_Stream5_IRQHandler(void) {}
__weak void DMA1_Stream6_IRQHandler(void) {}
__weak void DMA1_Stream7_IRQHandler(void) {}
__weak void DMA2_Stream0_IRQHandler(void) {}
__weak void DMA2_Stream1_IRQHandler(void) {}
__weak void DMA2_Stream2_IRQHandler(void) {}
__weak void DMA2_Stream3_IRQHandler(void) {}
__weak void DMA2_Stream4_IRQHandler(void) {}
__weak void DMA2_Stream5_IRQHandler(void) {}
__weak void DMA2_Stream6_IRQHandler(void) {}
__weak void DMA2_Stream7_IRQHandler(void) {}
void DMA_Call_IRQHandller(DMA_TypeDef* DMAx, uint32_t stream)
{
struct DMA_Stream_Sim* stream_sim = DMA_Get_Stream_Sim(DMAx, stream);
if (stream_sim == NULL) return;
#ifdef STM32F4
// Определяем какой обработчик вызывать на основе DMAx и stream
if (DMAx == DMA1) {
switch (stream) {
case 0: DMA1_Stream0_IRQHandler(); break;
case 1: DMA1_Stream1_IRQHandler(); break;
case 2: DMA1_Stream2_IRQHandler(); break;
case 3: DMA1_Stream3_IRQHandler(); break;
case 4: DMA1_Stream4_IRQHandler(); break;
case 5: DMA1_Stream5_IRQHandler(); break;
case 6: DMA1_Stream6_IRQHandler(); break;
case 7: DMA1_Stream7_IRQHandler(); break;
}
}
else if (DMAx == DMA2) {
switch (stream) {
case 0: DMA2_Stream0_IRQHandler(); break;
case 1: DMA2_Stream1_IRQHandler(); break;
case 2: DMA2_Stream2_IRQHandler(); break;
case 3: DMA2_Stream3_IRQHandler(); break;
case 4: DMA2_Stream4_IRQHandler(); break;
case 5: DMA2_Stream5_IRQHandler(); break;
case 6: DMA2_Stream6_IRQHandler(); break;
case 7: DMA2_Stream7_IRQHandler(); break;
}
}
#elif defined(STM32F1)
if (DMAx == DMA1) {
switch (stream) {
case 0: DMA1_Channel0_IRQHandler(); break;
case 1: DMA1_Channel1_IRQHandler(); break;
case 2: DMA1_Channel2_IRQHandler(); break;
case 3: DMA1_Channel3_IRQHandler(); break;
case 4: DMA1_Channel4_IRQHandler(); break;
case 5: DMA1_Channel5_IRQHandler(); break;
case 6: DMA1_Channel6_IRQHandler(); break;
case 7: DMA1_Channel7_IRQHandler(); break;
}
}
#endif
}
/////////////////////////////---DEINITIALIZATION---/////////////////////////////
void DMA_SIM_DEINIT(void)
{
#ifdef USE_DMA1
memset(&dma1_stream0s, 0, sizeof(dma1_stream0s));
memset(&dma1_stream1s, 0, sizeof(dma1_stream1s));
memset(&dma1_stream2s, 0, sizeof(dma1_stream2s));
memset(&dma1_stream3s, 0, sizeof(dma1_stream3s));
memset(&dma1_stream4s, 0, sizeof(dma1_stream4s));
memset(&dma1_stream5s, 0, sizeof(dma1_stream5s));
memset(&dma1_stream6s, 0, sizeof(dma1_stream6s));
memset(&dma1_stream7s, 0, sizeof(dma1_stream7s));
#endif
#ifdef USE_DMA2
memset(&dma2_stream0s, 0, sizeof(dma2_stream0s));
memset(&dma2_stream1s, 0, sizeof(dma2_stream1s));
memset(&dma2_stream2s, 0, sizeof(dma2_stream2s));
memset(&dma2_stream3s, 0, sizeof(dma2_stream3s));
memset(&dma2_stream4s, 0, sizeof(dma2_stream4s));
memset(&dma2_stream5s, 0, sizeof(dma2_stream5s));
memset(&dma2_stream6s, 0, sizeof(dma2_stream6s));
memset(&dma2_stream7s, 0, sizeof(dma2_stream7s));
#endif
}

View File

@ -0,0 +1,40 @@
#ifndef _MATLAB_DMA_H_
#define _MATLAB_DMA_H_
#include "stm32_matlab_conf.h"
#ifdef DMA1
#define USE_DMA1
#endif
#ifdef DMA2
#define USE_DMA2
#endif
/////////////////////////////---STRUCTURES---///////////////////////////
struct DMA_Stream_Sim
{
uint32_t* peripheral_address;
uint32_t* memory_address;
uint32_t buffer_size;
uint32_t current_index;
uint32_t data_size;
uint8_t circular_mode;
uint8_t transfer_complete;
uint8_t enabled;
uint8_t transfer_enabled;
};
///////////////////////////////////////////////////////////////////////
///////////////////////////---FUNCTIONS---///////////////////////////
void DMA_Sim_Transfer(DMA_TypeDef* DMAx, uint32_t stream);
struct DMA_Stream_Sim* DMA_Get_Stream_Sim(DMA_TypeDef* DMAx, uint32_t stream);
uint8_t DMA_Is_Stream_Enabled(DMA_TypeDef* DMAx, uint32_t stream);
uint32_t* DMA_Get_Peripheral_Address(DMA_TypeDef* DMAx, uint32_t stream);
uint32_t* DMA_Get_Memory_Address(DMA_TypeDef* DMAx, uint32_t stream);
uint32_t DMA_Get_Buffer_Size(DMA_TypeDef* DMAx, uint32_t stream);
uint8_t DMA_Get_Circular_Mode(DMA_TypeDef* DMAx, uint32_t stream);
uint32_t DMA_Get_DataSize(DMA_TypeDef* DMAx, uint32_t stream);
///////////////////////////////////////////////////////////////////////
#endif // _MATLAB_DMA_H_

View File

@ -7,7 +7,7 @@
struct SlaveChannels Slave_Channels; // структура для связи и синхронизации таймеров
void TIM_Call_IRQHandller(TIM_TypeDef* TIMx);
//----------------------TIMER BASE FUNCTIONS-----------------------//
/* Базовая функция для симуляции таймера: она вызывается каждый шаг симуляции */
@ -24,6 +24,7 @@ switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE
case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting
TIMx_Count(TIMx, TIMS);
Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
Write_TRGO(TIMx, TIMS);
break;
@ -32,6 +33,7 @@ switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE
Slave_Mode_Check_Source(TIMx, TIMS);
TIMx_Count(TIMx, TIMS);
Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
Write_TRGO(TIMx, TIMS);
break;
}
@ -48,12 +50,14 @@ void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
/* Проверка на переполнение и дальнейшая его обработка */
void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
{
TIMS->Updated = 0;
// Переполнение таймера: сброс таймера и вызов прерывания
if ((TIMx->CR1 & TIM_CR1_UDIS) == 0) // UPDATE enable
{
if ((TIMx->CR1 & TIM_CR1_ARPE) == 0) TIMS->RELOAD = TIMx->ARR; // PRELOAD disable - update ARR every itteration
if (TIMS->tx_cnt > TIMS->RELOAD || TIMS->tx_cnt < 0) // OVERFLOW
{
TIMS->Updated = 1;
TIMS->RELOAD = TIMx->ARR; // RELOAD ARR
if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER
@ -61,7 +65,7 @@ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
else if (TIMS->tx_cnt < 0)
TIMS->tx_cnt += TIMS->RELOAD+1;
call_IRQHandller(TIMx); // call HANDLER
TIM_Call_IRQHandller(TIMx); // call HANDLER
}
}
}
@ -79,8 +83,6 @@ void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
CC_PWM_Ch4_Simulation(TIMx, TIMS);
Write_OC_to_GPIO(TIMx, TIMS);
Write_OC_to_TRGO(TIMx, TIMS);
}
//-----------------CAPTURE COPMARE & PWM FUNCTIONS------------------//
/* Выбор режима CaptureCompare или PWM и симуляция для каждого канала */
@ -323,26 +325,38 @@ void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
}
}
/* Запись результата compare в глабальную структуру с TRIGGER OUTPUT */
void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
void Write_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
{
// write trigger output from OCxREF pin if need
unsigned temp_trgo;
if ((TIMx->CR2 & TIM_CR2_MMS) == (0b100 << TIM_CR2_MMS_Pos))
if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC1REF))
{
temp_trgo = TIMS->Channels.OC1REF;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b101 << TIM_CR2_MMS_Pos))
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC2REF))
{
temp_trgo = TIMS->Channels.OC2REF;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b110 << TIM_CR2_MMS_Pos))
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC3REF))
{
temp_trgo = TIMS->Channels.OC3REF;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b111 << TIM_CR2_MMS_Pos))
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC4REF))
{
temp_trgo = TIMS->Channels.OC4REF;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_UPDATE))
{
temp_trgo = TIMS->Updated;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_ENABLE))
{
temp_trgo = (TIMx->CR1 & TIM_CR1_CEN) ? 1: 0;
}
else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_RESET))
{
temp_trgo = 0;
}
// select TIMx TRGO
@ -585,7 +599,7 @@ void TIM_SIM_DEINIT(void)
//#endif
/* Вызов прерывания */
void call_IRQHandller(TIM_TypeDef* TIMx)
void TIM_Call_IRQHandller(TIM_TypeDef* TIMx)
{ // calling HANDLER
//if (TIMx == TIM1)
// TIM1_UP_IRQHandler();

View File

@ -42,7 +42,7 @@ struct SlaveChannels
unsigned TIM8_TRGO : 1;
};
extern struct SlaveChannels Slave_Channels; // структура для связи и синхронизации таймеров
/* Структура для моделирования каналов таймера */
struct Channels_Sim
{
@ -69,6 +69,7 @@ struct Channels_Sim
/* Структура для моделирования таймера */
struct TIM_Sim
{
int Updated; // счетчик таймера
double tx_cnt; // счетчик таймера
double tx_step; // шаг счета за один шаг симуляции
int RELOAD; // буфер, если PRELOAD = 1
@ -87,8 +88,6 @@ void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
/* Проверка на переполнение и дальнейшая его обработка */
void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
/* Вызов прерывания */
void call_IRQHandller(TIM_TypeDef *TIMx);
//-----------------------------------------------------------------//
@ -104,7 +103,7 @@ void CC_PWM_Ch4_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
/* Запись каналов таймера в порты GPIO */
void Write_OC_to_GPIO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
/* Запись результата compare в глабальную структуру с TRIGGER OUTPUT */
void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
void Write_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
//------------------------------------------------------------------//

View File

@ -5,6 +5,7 @@
**************************************************************************/
#include "stm32_matlab_conf.h"
#include "mcu_wrapper_conf.h"
#include "app_includes.h"
MCU_MemoryTypeDef MCU_MEM;
DBGMCU_TypeDef DEBUG_MCU;
@ -40,6 +41,17 @@ void deInitialize_MCU(void)
// обнуление структур, симулирующих память МК
memset(&MCU_MEM, 0, sizeof(MCU_MEM));
memset(&MCU_CORTEX_MEM, 0, sizeof(MCU_CORTEX_MEM));
memset(&htim1, 0, sizeof(htim1));
ClearStruct(htim1);
ClearStruct(htim3);
ClearStruct(htim8);
ClearStruct(htim11);
ClearStruct(htim12);
ClearStruct(htim13);
ClearStruct(hadc3);
ClearStruct(hdma_adc3);
}
/*------------------------------FUNCTIONS--------------------------------*/
@ -164,9 +176,9 @@ void Init_TIM_SIM(void)
tim5s.Channels.OC4_GPIOx = GPIOA;
tim5s.Channels.OC4_PIN_SHIFT = 3;
#endif
#ifdef USE_TIMx
#ifdef USE_TIM6
memset(&tim6s, 0, sizeof(tim6s));
tim6s.tx_cnt = TIMx->CNT;
tim6s.tx_cnt = TIM6->CNT;
tim6s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value;
tim6s.Channels.OC1_GPIOx = GPIOA;
@ -178,6 +190,118 @@ void Init_TIM_SIM(void)
tim6s.Channels.OC4_GPIOx = GPIOA;
tim6s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM7
memset(&tim7s, 0, sizeof(tim7s));
tim7s.tx_cnt = TIM7->CNT;
tim7s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value;
tim7s.Channels.OC1_GPIOx = GPIOA;
tim7s.Channels.OC1_PIN_SHIFT = 0;
tim7s.Channels.OC2_GPIOx = GPIOA;
tim7s.Channels.OC2_PIN_SHIFT = 0;
tim7s.Channels.OC3_GPIOx = GPIOA;
tim7s.Channels.OC3_PIN_SHIFT = 0;
tim7s.Channels.OC4_GPIOx = GPIOA;
tim7s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM8
memset(&tim8s, 0, sizeof(tim8s));
tim8s.tx_cnt = TIM8->CNT;
tim8s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value;
tim8s.Channels.OC1_GPIOx = GPIOA;
tim8s.Channels.OC1_PIN_SHIFT = 0;
tim8s.Channels.OC2_GPIOx = GPIOA;
tim8s.Channels.OC2_PIN_SHIFT = 0;
tim8s.Channels.OC3_GPIOx = GPIOA;
tim8s.Channels.OC3_PIN_SHIFT = 0;
tim8s.Channels.OC4_GPIOx = GPIOA;
tim8s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM9
memset(&tim9s, 0, sizeof(tim9s));
tim9s.tx_cnt = TIM9->CNT;
tim9s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value;
tim9s.Channels.OC1_GPIOx = GPIOA;
tim9s.Channels.OC1_PIN_SHIFT = 0;
tim9s.Channels.OC2_GPIOx = GPIOA;
tim9s.Channels.OC2_PIN_SHIFT = 0;
tim9s.Channels.OC3_GPIOx = GPIOA;
tim9s.Channels.OC3_PIN_SHIFT = 0;
tim9s.Channels.OC4_GPIOx = GPIOA;
tim9s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM10
memset(&tim10s, 0, sizeof(tim10s));
tim10s.tx_cnt = TIM10->CNT;
tim10s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value;
tim10s.Channels.OC1_GPIOx = GPIOA;
tim10s.Channels.OC1_PIN_SHIFT = 0;
tim10s.Channels.OC2_GPIOx = GPIOA;
tim10s.Channels.OC2_PIN_SHIFT = 0;
tim10s.Channels.OC3_GPIOx = GPIOA;
tim10s.Channels.OC3_PIN_SHIFT = 0;
tim10s.Channels.OC4_GPIOx = GPIOA;
tim10s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM11
memset(&tim11s, 0, sizeof(tim11s));
tim11s.tx_cnt = TIM11->CNT;
tim11s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value;
tim11s.Channels.OC1_GPIOx = GPIOA;
tim11s.Channels.OC1_PIN_SHIFT = 0;
tim11s.Channels.OC2_GPIOx = GPIOA;
tim11s.Channels.OC2_PIN_SHIFT = 0;
tim11s.Channels.OC3_GPIOx = GPIOA;
tim11s.Channels.OC3_PIN_SHIFT = 0;
tim11s.Channels.OC4_GPIOx = GPIOA;
tim11s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM12
memset(&tim12s, 0, sizeof(tim12s));
tim12s.tx_cnt = TIM12->CNT;
tim12s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value;
tim12s.Channels.OC1_GPIOx = GPIOA;
tim12s.Channels.OC1_PIN_SHIFT = 0;
tim12s.Channels.OC2_GPIOx = GPIOA;
tim12s.Channels.OC2_PIN_SHIFT = 0;
tim12s.Channels.OC3_GPIOx = GPIOA;
tim12s.Channels.OC3_PIN_SHIFT = 0;
tim12s.Channels.OC4_GPIOx = GPIOA;
tim12s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM13
memset(&tim13s, 0, sizeof(tim13s));
tim13s.tx_cnt = TIM13->CNT;
tim13s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value;
tim13s.Channels.OC1_GPIOx = GPIOA;
tim13s.Channels.OC1_PIN_SHIFT = 0;
tim13s.Channels.OC2_GPIOx = GPIOA;
tim13s.Channels.OC2_PIN_SHIFT = 0;
tim13s.Channels.OC3_GPIOx = GPIOA;
tim13s.Channels.OC3_PIN_SHIFT = 0;
tim13s.Channels.OC4_GPIOx = GPIOA;
tim13s.Channels.OC4_PIN_SHIFT = 0;
#endif
#ifdef USE_TIM14
memset(&tim14s, 0, sizeof(tim14s));
tim14s.tx_cnt = TIM14->CNT;
tim14s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value;
tim14s.Channels.OC1_GPIOx = GPIOA;
tim14s.Channels.OC1_PIN_SHIFT = 0;
tim14s.Channels.OC2_GPIOx = GPIOA;
tim14s.Channels.OC2_PIN_SHIFT = 0;
tim14s.Channels.OC3_GPIOx = GPIOA;
tim14s.Channels.OC3_PIN_SHIFT = 0;
tim14s.Channels.OC4_GPIOx = GPIOA;
tim14s.Channels.OC4_PIN_SHIFT = 0;
#endif
}
/*-------------------------------TIMERS----------------------------------*/
//-----------------------------------------------------------------------//

View File

@ -60,16 +60,15 @@ void Initialize_Periph_Sim(void);
#include "stm32_matlab_rcc.h"
#include "stm32_matlab_gpio.h"
#include "stm32_matlab_dma.h"
//-----------------------------------------------------------------------//
/*-------------------------------TIMERS----------------------------------*/
//#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \
// defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \
// defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14)
#include "stm32_matlab_tim.h"
// CODE
void Init_TIM_SIM(void);
#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \
defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \
defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14)
#include "stm32_matlab_tim.h"
#ifdef USE_TIM1
extern struct TIM_Sim tim1s;
@ -113,13 +112,22 @@ extern struct TIM_Sim tim13s;
#ifdef USE_TIM14
extern struct TIM_Sim tim14s;
#endif
#endif
#ifndef TIM_ENABLE
static void Simulate_TIMs() {}
static void TIM_SIM_DEINIT() {}
#endif
/*-------------------------------TIMERS----------------------------------*/
//-----------------------------------------------------------------------//
//-----------------------------------------------------------------------//
/*---------------------------------ADC-----------------------------------*/
void Init_ADC_SIM(void);
#if defined(USE_ADC1) || defined(USE_ADC2) || defined(USE_ADC3)
#include "stm32_matlab_adc.h"
#ifdef USE_ADC1
extern struct ADC_Sim adc1s;
#endif
@ -129,7 +137,12 @@ extern struct ADC_Sim adc2s;
#ifdef USE_ADC3
extern struct ADC_Sim adc3s;
#endif
#endif
#ifndef ADC_ENABLE
static void Simulate_ADCs() {}
static void ADC_SIM_DEINIT() {}
#endif
/*---------------------------------ADC-----------------------------------*/
//-----------------------------------------------------------------------//

View File

@ -27,6 +27,7 @@
"Sources": [
"stm32_matlab_conf.c",
"Drivers/STM32_SIMULINK/stm32_matlab_gpio.c",
"Drivers/STM32_SIMULINK/stm32_matlab_dma.c",
"Drivers/STM32_SIMULINK/stm32_periph_registers.c"
],
"Defines": {
@ -48,14 +49,16 @@
},
"Tab_TIM_Enable": {
"Prompt": "Enable TIMs",
"Def": "TIM_ENABLE",
"Type": "checkbox",
"Default": true,
"NewRow": true
},
"Tab_ADC_Enable": {
"Prompt": "Enable ADCs",
"Def": "ADC_ENABLE",
"Type": "checkbox",
"Default": true,
"Default": false,
"NewRow": true
}
}
@ -69,7 +72,7 @@
"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c"
],
"Type": "checkbox",
"Default": true,
"Default": false,
"NewRow": true
},
"HAL_ADC": {
@ -499,7 +502,7 @@
"Prompt": "TIM8 Enable",
"Def": "USE_TIM8",
"Type": "checkbox",
"Default": false,
"Default": true,
"NewRow": true
},
"TIM6_Handler": {
@ -590,7 +593,7 @@
"Prompt": "ADC1 Enable",
"Def": "USE_ADC1",
"Type": "checkbox",
"Default": true,
"Default": false,
"NewRow": true
},
"ADC2_Enable": {
@ -604,7 +607,7 @@
"Prompt": "ADC3 Enable",
"Def": "USE_ADC3",
"Type": "checkbox",
"Default": false,
"Default": true,
"NewRow": true
},
"Sample_Rate": {

View File

@ -55,7 +55,7 @@
#define OUT_PORT_NUMB 2
#define THYR_PORT_1_WIDTH 6
#define OUT_PORT_2_WIDTH 1
#define OUT_PORT_2_WIDTH 6
// INPUT/OUTPUTS PARAMS END
/** WRAPPER_CONF

View File

@ -0,0 +1,156 @@
@echo off
:: Получаем аргументы из командной строки
:: %1 - includes_USER
:: %2 - code_USER
:: %3 - режим (например, debug)
:: Аргументы:
:: %1 — includes строка (в кавычках)
:: %2 — sources строка
:: %3 — defines строка
:: %4 — режим компиляции (debug/release)
:: Сохраняем как переменные
set filename=%~1
set includes_USER=%~2
set code_USER=%~3
set defines_USER=%~4
set defines_CONFIG=%~5
set compil_mode=%~6
:: Заменяем __EQ__ на =
set defines_USER=%defines_USER:__EQ__==%
set defines_CONFIG=%defines_CONFIG:__EQ__==%
set defines_WRAPPER=-D"MATLAB"^ -D"__sizeof_ptr=8"
:: -------------------------USERS PATHS AND CODE---------------------------
::-------------------------------------------------------------------------
:: -------------------------WRAPPER PATHS AND CODE---------------------------
:: оболочка, которая будет моделировать работу МК в симулинке
:: WRAPPER BAT START
set code_WRAPPER=.\MCU_Wrapper\MCU.c^
.\MCU_Wrapper\mcu_wrapper.c
set includes_WRAPPER= -I".\MCU_Wrapper\"
:: WRAPPER BAT END
:: APP WRAPPER BAT START
set code_APP_WRAPPER=.\app_wrapper\app_wrapper.c^
.\app_wrapper\app_init.c^
.\app_wrapper\app_io.c
set includes_APP_WRAPPER= -I".\app_wrapper\"
:: APP WRAPPER BAT END
set includes_WRAPPER= %includes_WRAPPER% %includes_APP_WRAPPER%
set code_WRAPPER= %code_WRAPPER% %code_APP_WRAPPER%
:: PERIPH BAT START
set code_PERIPH=.\MCU_STM32_Matlab\stm32_matlab_conf.c^
.\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_gpio.c^
.\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_dma.c^
.\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_periph_registers.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c^
.\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c^
.\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_tim.c^
.\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_adc.c
set includes_PERIPH=-I".\MCU_STM32_Matlab\."^
-I".\MCU_STM32_Matlab\Drivers\STM32_SIMULINK"^
-I".\MCU_STM32_Matlab\Drivers\CMSIS"^
-I".\MCU_STM32_Matlab\Drivers\CMSIS\Device\STM32F4xx"^
-I".\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc"^
-I".\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy"
:: PERIPH BAT END
::-------------------------------------------------------------------------
:: ---------------------SET PARAMS FOR MEX COMPILING-----------------------
:: -------------ALL------------
set includes= %includes_WRAPPER% %includes_PERIPH% %includes_USER%
set codes= %code_USER% %code_WRAPPER% %code_PERIPH%
set defines= %defines_WRAPPER% %defines_CONFIG% %defines_USER%
:: -------OUTPUT FOLDER--------
set output= -outdir "." -output %filename%
:: если нужен дебаг, до запускаем run_mex с припиской debug
IF %compil_mode%==debug (set debug= -g)
::-------------------------------------------------------------------------
::------START COMPILING-------
if "%7"=="echo_enable" (
echo Compiling...
echo ===========================
echo =========INCLUDES==========
echo USER:
for %%f in (%includes_USER%) do (
echo %%f
)
echo INTERNAL:
for %%f in (%includes_WRAPPER%) do (
echo %%f
)
echo PERIPH:
for %%f in (%includes_PERIPH%) do (
echo %%f
)
echo ===========================
echo ==========SOURCES==========
echo USER:
for %%f in (%code_USER%) do (
echo %%f
)
echo INTERNAL:
for %%f in (%code_WRAPPER%) do (
echo %%f
)
echo PERIPH:
for %%f in (%code_PERIPH%) do (
echo %%f
)
echo ===========================
echo ==========DEFINES==========
echo USER:
for %%d in (%defines_USER%) do (
echo %%d
)
echo CONFIG:
for %%f in (%defines_CONFIG%) do (
echo %%f
)
echo INTERNAL:
for %%f in (%defines_WRAPPER%) do (
echo %%f
)
)
echo ===========================
echo MODE: %compil_mode%
echo ===========================
:: 1. ПРЕЖДЕ ЧЕМ КОМПИЛИРОВАТЬ - ВЫГРУЗИТЬ СТАРЫЙ ФАЙЛ
:: 2. Компиляция с флагами для MSVC
:: set LINK_EMBEDDED=/BASE:0x10000000 /FIXED:NO /FILEALIGN:0x1000 /FORCE:MULTIPLE /DYNAMICBASE:NO
set C_EMBEDDED="-w"
mex %output% %defines% %includes% %codes% %debug% CFLAGS="$CFLAGS %C_EMBEDDED%" LINKFLAGS="$LINKFLAGS %LINK_EMBEDDED%"
echo %DATE% %TIME%
exit /b %ERRORLEVEL%

View File

@ -10,10 +10,11 @@
// INCLUDES START
// Инклюды для доступа к коду МК в коде оболочке
//#include "stm32_matlab_conf.h"
#include "main.h"
#include "tim.h"
#include "adc.h"
#include "upp_main.h"
#include "adc_tools.h"
// INCLUDES END
#endif //_APP_INCLUDES_H_

View File

@ -17,12 +17,14 @@ void app_init(void) {
// Вызов разных функций в случае,
// если не используется отдельный поток для main().
HAL_Init();
MX_DMA_Init();
MX_TIM1_Init();
MX_TIM3_Init();
__HAL_TIM_SET_COMPARE(&hpwm1, PWM_CHANNEL_1, __HAL_TIM_GET_AUTORELOAD(&hpwm1)/2);
HAL_TIM_PWM_Start(&hpwm1, PWM_CHANNEL_1);
MX_ADC1_Init();
HAL_ADC_Start(&hadc1);
MX_TIM8_Init();
MX_ADC3_Init();
UPP_Init();
UPP_PreWhile();
// USER APP INIT END
}

View File

@ -32,7 +32,12 @@ void ThyristorWrite(real_T* Buffer)
*/
void app_readInputs(const real_T* Buffer) {
// USER APP INPUT START
ADC_Set_Channel_Value(ADC1, 0, ReadInputArray(1,0));
ADC_Set_Channel_Value(ADC3, 4, ReadInputArray(0,0));
ADC_Set_Channel_Value(ADC3, 5, ReadInputArray(0,1));
ADC_Set_Channel_Value(ADC3, 6, ReadInputArray(0,2));
ADC_Set_Channel_Value(ADC3, 7, ReadInputArray(0,3));
ADC_Set_Channel_Value(ADC3, 8, ReadInputArray(0,4));
ADC_Set_Channel_Value(ADC3, 10, ReadInputArray(0,5));
// USER APP INPUT END
}
@ -44,6 +49,10 @@ ADC_Set_Channel_Value(ADC1, 0, ReadInputArray(1,0));
void app_writeOutputBuffer(real_T* Buffer) {
// USER APP OUTPUT START
ThyristorWrite(Buffer);
WriteOutputArray(ADC1->DR, 1, 0);
extern ADC_Period_t adc;
for(int i = 0; i < 6; i++)
{
WriteOutputArray(adc.Data[i], 1, i);
}
// USER APP OUTPUT END
}

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@ -1 +1 @@
Subproject commit eff64709bccb8f8fa7297f4042f4ebb7c71a5a21
Subproject commit 60629aaa3bb3a068cbfe5a93f43f676bd154e85b

View File

@ -32,15 +32,12 @@ extern "C" {
/* USER CODE END Includes */
extern ADC_HandleTypeDef hadc1;
extern ADC_HandleTypeDef hadc3;
/* USER CODE BEGIN Private defines */
extern DMA_HandleTypeDef hdma_adc3;
/* USER CODE END Private defines */
void MX_ADC1_Init(void);
void MX_ADC3_Init(void);
/* USER CODE BEGIN Prototypes */

52
UPP/Core/Inc/dma.h Normal file
View File

@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file dma.h
* @brief This file contains all the function prototypes for
* the dma.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DMA_H__
#define __DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* DMA memory to memory transfer handles -------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_DMA_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_H__ */

View File

@ -75,6 +75,7 @@ void Error_Handler(void);
#define PWM_CHANNEL_4 TIM_CHANNEL_4
#define PWM_CHANNEL_5 TIM_CHANNEL_3
#define PWM_CHANNEL_6 TIM_CHANNEL_4
#define adc_tim htim8
#define UM_LED_GREEN2_Pin GPIO_PIN_2
#define UM_LED_GREEN2_GPIO_Port GPIOE
#define CEN_O_Pin GPIO_PIN_3

View File

@ -56,6 +56,7 @@ void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void TIM8_TRG_COM_TIM14_IRQHandler(void);
void DMA2_Stream0_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */

View File

@ -36,6 +36,8 @@ extern TIM_HandleTypeDef htim1;
extern TIM_HandleTypeDef htim3;
extern TIM_HandleTypeDef htim8;
extern TIM_HandleTypeDef htim11;
extern TIM_HandleTypeDef htim12;
@ -48,6 +50,7 @@ extern TIM_HandleTypeDef htim13;
void MX_TIM1_Init(void);
void MX_TIM3_Init(void);
void MX_TIM8_Init(void);
void MX_TIM11_Init(void);
void MX_TIM12_Init(void);
void MX_TIM13_Init(void);

View File

@ -0,0 +1,130 @@
/**
******************************************************************************
* @file adc_tools.c
* @brief Функции доступа к данным Modbus
******************************************************************************
* @details
******************************************************************************/
#include "adc_tools.h"
// Проверка корректности структуры АЦП
#define assert_adc(_adc_) check_null_ptr_2(_adc_, (_adc_)->f.Initialized)
/**
* @brief Инициализация периодического АЦП.
* @param adc Указатель на кастомный хендл АЦП
* @param htim Указатель на HAL хендл таймера
* @param hadc Указатель на HAL хендл АЦП
* @return HAL Status.
*/
HAL_StatusTypeDef ADC_Init(ADC_Period_t *adc, TIM_HandleTypeDef *htim, ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef res;
if(check_null_ptr_2(htim, hadc))
return HAL_ERROR;
adc->htim = htim;
adc->hadc = hadc;
adc->f.AdcRunning = 0;
adc->f.DataReady = 0;
adc->f.Initialized = 1;
return HAL_OK;
}
/**
* @brief Конфигуарция канала АЦП.
* @param adc Указатель на кастомный хендл АЦП
* @param ChNumb Номер канала для конфигурации
* @param levelZero Нулевой уровень (в квантах АЦП)
* @param valueMax Максимальный уровень Единиц Измерения (в Вольтах/Амперах/Градусах)
* @param levelMax Максимальный уровень АЦП (в квантах АЦП)
* @return HAL Status.
*/
HAL_StatusTypeDef ADC_ConfigChannel(ADC_Period_t *adc, int ChNumb, uint16_t levelZero, float valueMax, uint16_t levelMax)
{
HAL_StatusTypeDef res;
if(assert_adc(adc))
return HAL_ERROR;
if((valueMax == 0) || (levelMax == 0))
return HAL_ERROR;
adc->Coefs[ChNumb].lMax = levelMax;
adc->Coefs[ChNumb].vMax = valueMax;
adc->Coefs[ChNumb].lZero = levelZero;
return HAL_OK;
}
/**
* @brief Запуск АЦП.
* @param adc Указатель на кастомный хендл АЦП
* @param Period Период таймера с какой частотой будет работать АЦП
* @return HAL Status.
* @details Запускает АЦП с частотой дискретизации на которую настроен таймер adc_tim.
*/
HAL_StatusTypeDef ADC_Start(ADC_Period_t *adc, uint16_t Period)
{
HAL_StatusTypeDef res;
if(assert_adc(adc))
return HAL_ERROR;
if(Period == 0)
return HAL_ERROR;
// Запускаем таймер который будет запускать опрос АЦП с заданным периодом
__HAL_TIM_SET_AUTORELOAD(adc->htim, Period);
res = HAL_TIM_Base_Start(adc->htim);
if(res != HAL_OK)
{
return res;
}
// Запускаем АЦП который будет перекидывать данные в ADC_DMA_Buffer
res = HAL_ADC_Start_DMA(adc->hadc, (uint32_t*)adc->RawData, 6); // Затем АЦП с DMA
if(res != HAL_OK)
{
return res;
}
return res;
}
/**
* @brief Остановка АЦП .
* @param adc Указатель на кастомный хендл АЦП
* @return HAL Status.
* @details По факту остановка таймера, который запускает АЦП. Сам АЦП продолжает работу.
*/
HAL_StatusTypeDef ADC_Stop(ADC_Period_t *adc)
{
if(assert_adc(adc))
return HAL_ERROR;
// Запускаем таймер который будет запускать опрос АЦП
return HAL_TIM_Base_Stop(adc->htim);
}
/**
* @brief Остановка АЦП .
* @return HAL Status.
* @details По факту остановка таймера, который запускает АЦП. Сам АЦП продолжает работу.
* @note Вызывается в .
*/
HAL_StatusTypeDef ADC_Handle(ADC_Period_t *adc)
{
if(assert_adc(adc))
return HAL_ERROR;
ADC_Coefs_t *coefs = adc->Coefs;
uint16_t *raw = adc->RawData;
float *data = adc->Data;
for(int i = 0; i < ADC_NUMB_OF_CHANNELS; i++)
{
ADC_Coefs_t *coefs = &adc->Coefs[i];
data[i] = ((float)(raw[i])-coefs->lZero) * coefs->vMax / (coefs->lMax-coefs->lZero);
}
adc->f.DataReady = 1;
return HAL_OK;
}

View File

@ -0,0 +1,62 @@
/**
******************************************************************************
* @file adc_tools.h
* @brief Определения структур данных Modbus устройства
******************************************************************************
* @details
******************************************************************************/
#ifndef _ADC_TOOLS_H_
#define _ADC_TOOLS_H_
#include "main.h"
#define ADC_NUMB_OF_CHANNELS 6
/**
* @brief Коэфициенты канала АЦП для пересчета в единицы измерения
*/
typedef struct
{
uint16_t lZero; ///< Нулевой уровень (в квантах АЦП)
float vMax; ///< Максимальный уровень Единиц Измерения (в Вольтах/Амперах/Градусах)
uint16_t lMax; ///< Максимальный уровень АЦП (в квантах АЦП)
}ADC_Coefs_t;
/**
* @brief Хендл АЦП
*/
typedef struct
{
// Handles
TIM_HandleTypeDef *htim; ///< Хендл таймера, который запускает АЦП
ADC_HandleTypeDef *hadc; ///< Хендл АЦП
// Data and calculation
uint16_t RawData[ADC_NUMB_OF_CHANNELS]; ///< Сырые значения АЦП
ADC_Coefs_t Coefs[ADC_NUMB_OF_CHANNELS]; ///< Коэффициенты @ref ADC_Coefs_t
float Data[ADC_NUMB_OF_CHANNELS]; ///< Пересчитанные значения АЦП (в Вольтах/Амперах/Градусах)
struct
{
unsigned Initialized:1;
unsigned AdcRunning:1;
unsigned DataReady:1;
}f;
}ADC_Period_t;
/* Инициализация периодического АЦП */
HAL_StatusTypeDef ADC_Init(ADC_Period_t *adc, TIM_HandleTypeDef *htim, ADC_HandleTypeDef *hadc);
/* Конфигуарция канала АЦП. */
HAL_StatusTypeDef ADC_ConfigChannel(ADC_Period_t *adc, int ChNumb, uint16_t levelZero, float valueMax, uint16_t levelMax);
/* Запуск АЦП. */
HAL_StatusTypeDef ADC_Start(ADC_Period_t *adc, uint16_t Period);
/* Остановка АЦП. */
HAL_StatusTypeDef ADC_Stop(ADC_Period_t *adc);
/* Остановка АЦП . */
HAL_StatusTypeDef ADC_Handle(ADC_Period_t *adc);
#endif //_ADC_TOOLS_H_

View File

@ -21,59 +21,12 @@
#include "adc.h"
/* USER CODE BEGIN 0 */
#include "tim.h"
/* USER CODE END 0 */
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc3;
DMA_HandleTypeDef hdma_adc3;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
hadc1.Init.ScanConvMode = DISABLE;
hadc1.Init.ContinuousConvMode = ENABLE;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_0;
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/* ADC3 init function */
void MX_ADC3_Init(void)
{
@ -93,15 +46,15 @@ void MX_ADC3_Init(void)
hadc3.Instance = ADC3;
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
hadc3.Init.ScanConvMode = DISABLE;
hadc3.Init.ScanConvMode = ENABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO;
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.NbrOfConversion = 6;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
Error_Handler();
@ -109,13 +62,58 @@ void MX_ADC3_Init(void)
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_7;
sConfig.Channel = ADC_CHANNEL_4;
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_5;
sConfig.Rank = 2;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_6;
sConfig.Rank = 3;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_7;
sConfig.Rank = 4;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_8;
sConfig.Rank = 5;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_10;
sConfig.Rank = 6;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
@ -126,28 +124,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(adcHandle->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
else if(adcHandle->Instance==ADC3)
if(adcHandle->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspInit 0 */
@ -176,6 +153,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(AI_Temp2_GPIO_Port, &GPIO_InitStruct);
/* ADC3 DMA Init */
/* ADC3 Init */
hdma_adc3.Instance = DMA2_Stream0;
hdma_adc3.Init.Channel = DMA_CHANNEL_2;
hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_adc3.Init.Mode = DMA_NORMAL;
hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc3);
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
@ -185,24 +181,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
{
if(adcHandle->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE();
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
else if(adcHandle->Instance==ADC3)
if(adcHandle->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspDeInit 0 */
@ -223,6 +202,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
HAL_GPIO_DeInit(AI_Temp2_GPIO_Port, AI_Temp2_Pin);
/* ADC3 DMA DeInit */
HAL_DMA_DeInit(adcHandle->DMA_Handle);
/* USER CODE BEGIN ADC3_MspDeInit 1 */
/* USER CODE END ADC3_MspDeInit 1 */

55
UPP/Core/Src/dma.c Normal file
View File

@ -0,0 +1,55 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file dma.c
* @brief This file provides code for the configuration
* of all the requested memory to memory DMA transfers.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "dma.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure DMA */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/**
* Enable DMA controller clock
*/
void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA2_CLK_ENABLE();
/* DMA interrupt init */
/* DMA2_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

View File

@ -20,6 +20,7 @@
#include "main.h"
#include "adc.h"
#include "can.h"
#include "dma.h"
#include "iwdg.h"
#include "rtc.h"
#include "spi.h"
@ -28,7 +29,7 @@
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "upp_main.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -92,6 +93,7 @@ int main(void)
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_DMA_Init();
MX_ADC3_Init();
MX_USART3_UART_Init();
MX_CAN1_Init();
@ -104,26 +106,23 @@ int main(void)
MX_SPI3_Init();
MX_TIM11_Init();
MX_TIM12_Init();
MX_ADC1_Init();
MX_TIM8_Init();
/* USER CODE BEGIN 2 */
#else
MX_TIM1_Init();
MX_TIM3_Init();
#endif
__HAL_TIM_SET_COMPARE(&hpwm1, PWM_CHANNEL_1, __HAL_TIM_GET_AUTORELOAD(&hpwm1)/2);
HAL_TIM_PWM_Start(&hpwm1, PWM_CHANNEL_1);
#else //MATLAB
#endif //MATLAB
UPP_Init();
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
UPP_PreWhile();
while (1)
{
UPP_While();
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
int A = 0;
return A;
/* USER CODE END 3 */
}

View File

@ -55,6 +55,8 @@
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_adc3;
extern TIM_HandleTypeDef htim8;
extern TIM_HandleTypeDef htim14;
/* USER CODE BEGIN EV */
@ -207,12 +209,29 @@ void TIM8_TRG_COM_TIM14_IRQHandler(void)
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */
#ifndef MATLAB
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim8);
HAL_TIM_IRQHandler(&htim14);
/* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */
#endif
/* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream0 global interrupt.
*/
void DMA2_Stream0_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
#include "adc_tools.h"
extern ADC_Period_t adc;
ADC_Handle(&adc);
/* USER CODE END DMA2_Stream0_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc3);
/* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
/* USER CODE END DMA2_Stream0_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

View File

@ -26,6 +26,7 @@
TIM_HandleTypeDef htim1;
TIM_HandleTypeDef htim3;
TIM_HandleTypeDef htim8;
TIM_HandleTypeDef htim11;
TIM_HandleTypeDef htim12;
TIM_HandleTypeDef htim13;
@ -169,6 +170,47 @@ void MX_TIM3_Init(void)
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
}
/* TIM8 init function */
void MX_TIM8_Init(void)
{
/* USER CODE BEGIN TIM8_Init 0 */
/* USER CODE END TIM8_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM8_Init 1 */
/* USER CODE END TIM8_Init 1 */
htim8.Instance = TIM8;
htim8.Init.Prescaler = 180-1;
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
htim8.Init.Period = 1000;
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim8.Init.RepetitionCounter = 0;
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM8_Init 2 */
/* USER CODE END TIM8_Init 2 */
}
/* TIM11 init function */
void MX_TIM11_Init(void)
@ -281,6 +323,21 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
/* USER CODE END TIM3_MspInit 1 */
}
else if(tim_baseHandle->Instance==TIM8)
{
/* USER CODE BEGIN TIM8_MspInit 0 */
/* USER CODE END TIM8_MspInit 0 */
/* TIM8 clock enable */
__HAL_RCC_TIM8_CLK_ENABLE();
/* TIM8 interrupt Init */
HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);
/* USER CODE BEGIN TIM8_MspInit 1 */
/* USER CODE END TIM8_MspInit 1 */
}
else if(tim_baseHandle->Instance==TIM11)
{
/* USER CODE BEGIN TIM11_MspInit 0 */
@ -392,6 +449,20 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
/* USER CODE END TIM3_MspDeInit 1 */
}
else if(tim_baseHandle->Instance==TIM8)
{
/* USER CODE BEGIN TIM8_MspDeInit 0 */
/* USER CODE END TIM8_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM8_CLK_DISABLE();
/* TIM8 interrupt Deinit */
HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn);
/* USER CODE BEGIN TIM8_MspDeInit 1 */
/* USER CODE END TIM8_MspDeInit 1 */
}
else if(tim_baseHandle->Instance==TIM11)
{
/* USER CODE BEGIN TIM11_MspDeInit 0 */

58
UPP/Core/UPP/upp_main.c Normal file
View File

@ -0,0 +1,58 @@
/**
******************************************************************************
* @file upp_main.c
* @brief Инициализация и самые базовые вещи по работе УПП
******************************************************************************
* @details
******************************************************************************/
#include "main.h" // либы из AllLibs и вербальные имена из CubeMX
#include "upp_main.h" // всё остальное по работе с УПП
#include "adc.h"
#include "tim.h"
#include "adc_tools.h"
ADC_Period_t adc;
#define ADC_CHANNEL_UBA 0
#define ADC_CHANNEL_UAC 1
#define ADC_CHANNEL_IC 2
#define ADC_CHANNEL_IA 3
#define ADC_CHANNEL_TEMP1 4
#define ADC_CHANNEL_TEMP2 5
/**
* @brief Инициализация УПП.
* @return 0 - если ОК, >1 если ошибка.
*/
int UPP_Init(void)
{
ADC_Init(&adc, &adc_tim, &hadc3);
ADC_ConfigChannel(&adc, ADC_CHANNEL_UBA, 2048, 1216, 4095);
ADC_ConfigChannel(&adc, ADC_CHANNEL_UAC, 2048, 1216, 4095);
ADC_ConfigChannel(&adc, ADC_CHANNEL_IC, 2048, 53, 4095);
ADC_ConfigChannel(&adc, ADC_CHANNEL_IA, 2048, 53, 4095);
ADC_ConfigChannel(&adc, ADC_CHANNEL_TEMP1, 2554, 90, 4095);
ADC_ConfigChannel(&adc, ADC_CHANNEL_TEMP2, 2554, 90, 4095);
return 0;
}
/**
* @brief Инициализация основного цикла УПП.
* @return 0 - если ОК, >1 если ошибка.
*/
int UPP_PreWhile(void)
{
ADC_Start(&adc, 1000);
return 0;
}
/**
* @brief Основной цикл УПП.
* @return 0 - если ОК, >1 если ошибка.
*/
int UPP_While(void)
{
return 0;
}

21
UPP/Core/UPP/upp_main.h Normal file
View File

@ -0,0 +1,21 @@
/**
******************************************************************************
* @file modbus_data.h
* @brief Определения структур данных Modbus устройства
******************************************************************************
* @details
******************************************************************************/
#ifndef _UPP_MAIN_H
#define _UPP_MAIN_H
#include "upp_config.h"
/* Инициализация УПП */
int UPP_Init(void);
/* Инициализация основного цикла УПП. */
int UPP_PreWhile(void);
/* Основной цикл УПП. */
int UPP_While(void);
#endif //_UPP_MAIN_H

View File

@ -1,4 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
@ -45,7 +45,7 @@
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath />
<ListingPath></ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
@ -104,16 +104,16 @@
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>6</nTsel>
<sDll />
<sDllPa />
<sDlgDll />
<sDlgPa />
<sIfile />
<tDll />
<tDllPa />
<tDlgDll />
<tDlgPa />
<tIfile />
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
@ -128,7 +128,7 @@
<Name>-U-O142 -O2190 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F427ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint />
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
@ -158,19 +158,19 @@
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable />
<LintConfigFile />
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName />
<pszMrule />
<pSingCmds />
<pMultCmds />
<pMisraNamep />
<pszMrulep />
<pSingCmdsp />
<pMultCmdsp />
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
@ -298,7 +298,7 @@
</Group>
<Group>
<GroupName>Application/User/Core</GroupName>
<GroupName>UPP/Main</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
@ -310,14 +310,86 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<PathWithFileName>..\Core\UPP\upp_main.c</PathWithFileName>
<FilenameWithoutPath>upp_main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Core\UPP\upp_main.h</PathWithFileName>
<FilenameWithoutPath>upp_main.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>PowerMonitor</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Core\PowerMonitor\adc_tools.c</PathWithFileName>
<FilenameWithoutPath>adc_tools.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Core\PowerMonitor\adc_tools.h</PathWithFileName>
<FilenameWithoutPath>adc_tools.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Thyristors</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
<Group>
<GroupName>Application/User/Core</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -328,8 +400,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>12</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -340,8 +412,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>13</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -352,8 +424,20 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>14</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/dma.c</PathWithFileName>
<FilenameWithoutPath>dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -364,8 +448,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>15</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -376,8 +460,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>16</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -388,8 +472,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>17</FileNumber>
<GroupNumber>5</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -400,8 +484,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>18</FileNumber>
<GroupNumber>5</GroupNumber>
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@ -412,8 +496,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -424,8 +508,8 @@
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</File>
<File>
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@ -436,8 +520,8 @@
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</File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -451,13 +535,13 @@
<Group>
<GroupName>MyLibs</GroupName>
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<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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@ -468,8 +552,8 @@
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -480,8 +564,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -492,8 +576,8 @@
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</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -504,8 +588,8 @@
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -516,8 +600,8 @@
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bShared>0</bShared>
</File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -572,8 +656,8 @@
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bShared>0</bShared>
</File>
<File>
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<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -596,8 +680,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -608,8 +692,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -620,8 +704,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>35</FileNumber>
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<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -632,8 +716,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>36</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -644,8 +728,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>37</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -656,8 +740,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>38</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -668,8 +752,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>39</FileNumber>
<GroupNumber>7</GroupNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -688,8 +772,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>40</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -700,8 +784,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>41</FileNumber>
<GroupNumber>8</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -720,8 +804,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
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<FileNumber>42</FileNumber>
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<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -732,8 +816,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>43</FileNumber>
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<FileNumber>48</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -744,8 +828,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -756,8 +840,8 @@
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>45</FileNumber>
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<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -768,8 +852,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -788,8 +872,8 @@
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -800,8 +884,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -812,8 +896,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>54</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -824,8 +908,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>50</FileNumber>
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<FileNumber>55</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -836,8 +920,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>56</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -848,8 +932,8 @@
<bShared>0</bShared>
</File>
<File>
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<FileNumber>57</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -860,8 +944,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -872,8 +956,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -884,8 +968,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -896,8 +980,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -908,8 +992,8 @@
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
@ -920,8 +1004,8 @@
<bShared>0</bShared>
</File>
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@ -932,8 +1016,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -944,8 +1028,8 @@
<bShared>0</bShared>
</File>
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@ -956,8 +1040,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -968,8 +1052,8 @@
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</File>
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@ -980,8 +1064,8 @@
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</File>
<File>
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@ -992,8 +1076,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -1004,8 +1088,8 @@
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<File>
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@ -1016,8 +1100,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -1028,8 +1112,8 @@
<bShared>0</bShared>
</File>
<File>
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@ -1040,8 +1124,8 @@
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</File>
<File>
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@ -1052,8 +1136,8 @@
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<File>
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@ -1064,8 +1148,8 @@
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<File>
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@ -1084,8 +1168,8 @@
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<File>
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@ -1104,8 +1188,8 @@
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<File>
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<tvExpOptDlg>0</tvExpOptDlg>

View File

@ -1,7 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" noNamespaceSchemaLocation="project_projx.xsd">
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>UPP</TargetName>
@ -17,28 +20,28 @@
<PackID>Keil.STM32F4xx_DFP.2.16.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") TZ</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll />
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile />
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F427ZGTx$CMSIS\SVD\STM32F427x.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -53,15 +56,15 @@
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath />
<ListingPath></ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -70,8 +73,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
@ -80,15 +83,15 @@
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>1</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString />
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -102,8 +105,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>0</ComprImg>
</CommonProperty>
<DllOption>
@ -136,11 +139,11 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2V8M.DLL</Flash2>
<Flash3 />
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -173,7 +176,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName />
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -308,7 +311,7 @@
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -335,10 +338,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<MiscControls></MiscControls>
<Define>USE_HAL_DRIVER,STM32F427xx</Define>
<Undefine />
<IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../AllLibs/ExtMemory/Inc;../AllLibs/Modbus/Inc;../AllLibs/MyLibs/MyLibs/Inc;../AllLibs/MyLibs/RTT;../AllLibs/PeriphGeneral/Inc;../Core/Configs</IncludePath>
<Undefine></Undefine>
<IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../AllLibs/ExtMemory/Inc;../AllLibs/Modbus/Inc;../AllLibs/MyLibs/MyLibs/Inc;../AllLibs/MyLibs/RTT;../AllLibs/PeriphGeneral/Inc;../Core/Configs;..\Core\PowerMonitor;..\Core\Thyristors;..\Core\UPP</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -353,10 +356,10 @@
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
@ -366,15 +369,15 @@
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange />
<DataAddressRange />
<pXoBase />
<ScatterFile />
<IncludeLibs />
<IncludeLibsPath />
<Misc />
<LinkerInputFile />
<DisabledWarnings />
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
@ -429,6 +432,39 @@
</File>
</Files>
</Group>
<Group>
<GroupName>UPP/Main</GroupName>
<Files>
<File>
<FileName>upp_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\Core\UPP\upp_main.c</FilePath>
</File>
<File>
<FileName>upp_main.h</FileName>
<FileType>5</FileType>
<FilePath>..\Core\UPP\upp_main.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>PowerMonitor</GroupName>
<Files>
<File>
<FileName>adc_tools.c</FileName>
<FileType>1</FileType>
<FilePath>..\Core\PowerMonitor\adc_tools.c</FilePath>
</File>
<File>
<FileName>adc_tools.h</FileName>
<FileType>5</FileType>
<FilePath>..\Core\PowerMonitor\adc_tools.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Thyristors</GroupName>
</Group>
<Group>
<GroupName>Application/User/Core</GroupName>
<Files>
@ -452,6 +488,62 @@
<FileType>1</FileType>
<FilePath>../Core/Src/can.c</FilePath>
</File>
<File>
<FileName>dma.c</FileName>
<FileType>1</FileType>
<FilePath>../Core/Src/dma.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<FileArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
<File>
<FileName>iwdg.c</FileName>
<FileType>1</FileType>
@ -793,24 +885,26 @@
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0" />
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
<targetInfos>
<targetInfo name="UPP" />
<targetInfo name="UPP"/>
</targetInfos>
</component>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="ITM" Cvendor="Keil" Cversion="1.2.0" condition="ARMCC Cortex-M with ITM">
<package name="ARM_Compiler" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="Keil" version="1.7.2" />
<package name="ARM_Compiler" schemaVersion="1.7.7" url="https://www.keil.com/pack/" vendor="Keil" version="1.7.2"/>
<targetInfos>
<targetInfo name="UPP" />
<targetInfo name="UPP"/>
</targetInfos>
</component>
</components>
<files />
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
@ -819,5 +913,5 @@
</Layer>
</Layers>
</LayerInfo>
</Project>
</Project>

View File

@ -1,17 +1,28 @@
#MicroXplorer Configuration settings - do not modify
ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_0
ADC1.ContinuousConvMode=ENABLE
ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode
ADC1.NbrOfConversionFlag=1
ADC1.Rank-1\#ChannelRegularConversion=1
ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC1.master=1
ADC3.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_7
ADC3.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,NbrOfConversionFlag,NbrOfConversion
ADC3.NbrOfConversion=1
ADC3.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_4
ADC3.Channel-16\#ChannelRegularConversion=ADC_CHANNEL_5
ADC3.Channel-17\#ChannelRegularConversion=ADC_CHANNEL_6
ADC3.Channel-18\#ChannelRegularConversion=ADC_CHANNEL_7
ADC3.Channel-19\#ChannelRegularConversion=ADC_CHANNEL_8
ADC3.Channel-20\#ChannelRegularConversion=ADC_CHANNEL_10
ADC3.EOCSelection=ADC_EOC_SEQ_CONV
ADC3.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T8_TRGO
ADC3.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,NbrOfConversionFlag,NbrOfConversion,ScanConvMode,Rank-16\#ChannelRegularConversion,Channel-16\#ChannelRegularConversion,SamplingTime-16\#ChannelRegularConversion,Rank-17\#ChannelRegularConversion,Channel-17\#ChannelRegularConversion,SamplingTime-17\#ChannelRegularConversion,Rank-18\#ChannelRegularConversion,Channel-18\#ChannelRegularConversion,SamplingTime-18\#ChannelRegularConversion,Rank-19\#ChannelRegularConversion,Channel-19\#ChannelRegularConversion,SamplingTime-19\#ChannelRegularConversion,Rank-20\#ChannelRegularConversion,Channel-20\#ChannelRegularConversion,SamplingTime-20\#ChannelRegularConversion,ExternalTrigConv,EOCSelection
ADC3.NbrOfConversion=6
ADC3.NbrOfConversionFlag=1
ADC3.Rank-15\#ChannelRegularConversion=1
ADC3.Rank-16\#ChannelRegularConversion=2
ADC3.Rank-17\#ChannelRegularConversion=3
ADC3.Rank-18\#ChannelRegularConversion=4
ADC3.Rank-19\#ChannelRegularConversion=5
ADC3.Rank-20\#ChannelRegularConversion=6
ADC3.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-16\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-17\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-18\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-19\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-20\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.ScanConvMode=ENABLE
CAD.formats=
CAD.pinconfig=
CAD.provider=
@ -22,6 +33,18 @@ CAN1.CalculateTimeBit=4000
CAN1.CalculateTimeQuantum=222.22222222222223
CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler
CAN1.Prescaler=10
Dma.ADC3.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.ADC3.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.ADC3.0.Instance=DMA2_Stream0
Dma.ADC3.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.ADC3.0.MemInc=DMA_MINC_ENABLE
Dma.ADC3.0.Mode=DMA_NORMAL
Dma.ADC3.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.ADC3.0.PeriphInc=DMA_PINC_DISABLE
Dma.ADC3.0.Priority=DMA_PRIORITY_LOW
Dma.ADC3.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.Request0=ADC3
Dma.RequestsNb=1
File.Version=6
GPIO.groupedBy=Group By Peripherals
IWDG.IPParameters=Prescaler
@ -29,15 +52,16 @@ IWDG.Prescaler=IWDG_PRESCALER_32
KeepUserPlacement=false
Mcu.CPN=STM32F427ZGT6
Mcu.Family=STM32F4
Mcu.IP0=ADC1
Mcu.IP1=ADC3
Mcu.IP0=ADC3
Mcu.IP1=CAN1
Mcu.IP10=TIM3
Mcu.IP11=TIM11
Mcu.IP12=TIM12
Mcu.IP13=TIM13
Mcu.IP14=USART3
Mcu.IP15=USART6
Mcu.IP2=CAN1
Mcu.IP11=TIM8
Mcu.IP12=TIM11
Mcu.IP13=TIM12
Mcu.IP14=TIM13
Mcu.IP15=USART3
Mcu.IP16=USART6
Mcu.IP2=DMA
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=RCC
@ -45,7 +69,7 @@ Mcu.IP6=RTC
Mcu.IP7=SPI3
Mcu.IP8=SYS
Mcu.IP9=TIM1
Mcu.IPNb=16
Mcu.IPNb=17
Mcu.Name=STM32F427Z(G-I)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PE2
@ -56,54 +80,54 @@ Mcu.Pin12=PF10
Mcu.Pin13=PH0/OSC_IN
Mcu.Pin14=PH1/OSC_OUT
Mcu.Pin15=PC0
Mcu.Pin16=PA0/WKUP
Mcu.Pin17=PA4
Mcu.Pin18=PA5
Mcu.Pin19=PA6
Mcu.Pin16=PA4
Mcu.Pin17=PA5
Mcu.Pin18=PA6
Mcu.Pin19=PB0
Mcu.Pin2=PE4
Mcu.Pin20=PB0
Mcu.Pin21=PB1
Mcu.Pin22=PF11
Mcu.Pin23=PB10
Mcu.Pin24=PB11
Mcu.Pin25=PB13
Mcu.Pin26=PG6
Mcu.Pin27=PC6
Mcu.Pin28=PC7
Mcu.Pin29=PC8
Mcu.Pin20=PB1
Mcu.Pin21=PF11
Mcu.Pin22=PB10
Mcu.Pin23=PB11
Mcu.Pin24=PB13
Mcu.Pin25=PG6
Mcu.Pin26=PC6
Mcu.Pin27=PC7
Mcu.Pin28=PC8
Mcu.Pin29=PC9
Mcu.Pin3=PE5
Mcu.Pin30=PC9
Mcu.Pin31=PA8
Mcu.Pin32=PA9
Mcu.Pin33=PA10
Mcu.Pin34=PA11
Mcu.Pin35=PA12
Mcu.Pin36=PA13
Mcu.Pin37=PA14
Mcu.Pin38=PA15
Mcu.Pin39=PC10
Mcu.Pin30=PA8
Mcu.Pin31=PA9
Mcu.Pin32=PA10
Mcu.Pin33=PA11
Mcu.Pin34=PA12
Mcu.Pin35=PA13
Mcu.Pin36=PA14
Mcu.Pin37=PA15
Mcu.Pin38=PC10
Mcu.Pin39=PC11
Mcu.Pin4=PE6
Mcu.Pin40=PC11
Mcu.Pin41=PC12
Mcu.Pin42=PD2
Mcu.Pin43=PD3
Mcu.Pin44=PD6
Mcu.Pin45=PG12
Mcu.Pin46=PG15
Mcu.Pin47=PB3
Mcu.Pin48=PB6
Mcu.Pin49=PB7
Mcu.Pin40=PC12
Mcu.Pin41=PD2
Mcu.Pin42=PD3
Mcu.Pin43=PD6
Mcu.Pin44=PG12
Mcu.Pin45=PG15
Mcu.Pin46=PB3
Mcu.Pin47=PB6
Mcu.Pin48=PB7
Mcu.Pin49=PB8
Mcu.Pin5=PC13
Mcu.Pin50=PB8
Mcu.Pin51=PB9
Mcu.Pin52=PE0
Mcu.Pin53=PE1
Mcu.Pin54=VP_IWDG_VS_IWDG
Mcu.Pin55=VP_RTC_VS_RTC_Activate
Mcu.Pin56=VP_RTC_VS_RTC_Calendar
Mcu.Pin57=VP_SYS_VS_tim14
Mcu.Pin58=VP_TIM1_VS_ClockSourceINT
Mcu.Pin59=VP_TIM3_VS_ClockSourceINT
Mcu.Pin50=PB9
Mcu.Pin51=PE0
Mcu.Pin52=PE1
Mcu.Pin53=VP_IWDG_VS_IWDG
Mcu.Pin54=VP_RTC_VS_RTC_Activate
Mcu.Pin55=VP_RTC_VS_RTC_Calendar
Mcu.Pin56=VP_SYS_VS_tim14
Mcu.Pin57=VP_TIM1_VS_ClockSourceINT
Mcu.Pin58=VP_TIM3_VS_ClockSourceINT
Mcu.Pin59=VP_TIM8_VS_ClockSourceINT
Mcu.Pin6=PC14/OSC32_IN
Mcu.Pin60=VP_TIM11_VS_ClockSourceINT
Mcu.Pin61=VP_TIM12_VS_ClockSourceINT
@ -113,11 +137,12 @@ Mcu.Pin8=PF6
Mcu.Pin9=PF7
Mcu.PinsNb=63
Mcu.ThirdPartyNb=0
Mcu.UserConstants=mb_huart,huart3;mbdbg_htim,htim11;mb_htim,htim12;mb_dbg_huart,huart6;ustim,htim13;mem_hspi,hspi3;hpwm1,htim1;hpwm2,htim2;PWM_CHANNEL_1,TIM_CHANNEL_1;PWM_CHANNEL_2,TIM_CHANNEL_2;PWM_CHANNEL_3,TIM_CHANNEL_3;PWM_CHANNEL_4,TIM_CHANNEL_4;PWM_CHANNEL_5,TIM_CHANNEL_3;PWM_CHANNEL_6,TIM_CHANNEL_4
Mcu.UserConstants=mb_huart,huart3;mbdbg_htim,htim11;mb_htim,htim12;mb_dbg_huart,huart6;ustim,htim13;mem_hspi,hspi3;hpwm1,htim1;hpwm2,htim2;PWM_CHANNEL_1,TIM_CHANNEL_1;PWM_CHANNEL_2,TIM_CHANNEL_2;PWM_CHANNEL_3,TIM_CHANNEL_3;PWM_CHANNEL_4,TIM_CHANNEL_4;PWM_CHANNEL_5,TIM_CHANNEL_3;PWM_CHANNEL_6,TIM_CHANNEL_4;adc_tim,htim8
Mcu.UserName=STM32F427ZGTx
MxCube.Version=6.12.1
MxDb.Version=DB.6.0.121
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
@ -131,7 +156,6 @@ NVIC.TIM8_TRG_COM_TIM14_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
NVIC.TimeBase=TIM8_TRG_COM_TIM14_IRQn
NVIC.TimeBaseIP=TIM14
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA0/WKUP.Signal=ADCx_IN0
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=PWM3
PA10.Locked=true
@ -370,7 +394,7 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-true-HAL-true,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_TIM13_Init-TIM13-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_TIM1_Init-TIM1-false-HAL-true,10-MX_TIM3_Init-TIM3-false-HAL-true,11-MX_USART6_UART_Init-USART6-false-HAL-true,12-MX_SPI3_Init-SPI3-false-HAL-true,13-MX_TIM11_Init-TIM11-false-HAL-true,14-MX_TIM12_Init-TIM12-false-HAL-true
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-true-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC3_Init-ADC3-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,6-MX_CAN1_Init-CAN1-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_TIM13_Init-TIM13-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_TIM1_Init-TIM1-false-HAL-true,11-MX_TIM3_Init-TIM3-false-HAL-true,12-MX_USART6_UART_Init-USART6-false-HAL-true,13-MX_SPI3_Init-SPI3-false-HAL-true,14-MX_TIM11_Init-TIM11-false-HAL-true,15-MX_TIM12_Init-TIM12-false-HAL-true,16-MX_TIM8_Init-TIM8-false-HAL-true
RCC.48MHZClocksFreq_Value=90000000
RCC.AHBFreq_Value=180000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
@ -415,8 +439,6 @@ RTC.IPParameters=WeekDay,Year,Date,Month,Hours
RTC.Month=RTC_MONTH_JANUARY
RTC.WeekDay=RTC_WEEKDAY_MONDAY
RTC.Year=25
SH.ADCx_IN0.0=ADC1_IN0,IN0
SH.ADCx_IN0.ConfNb=1
SH.ADCx_IN10.0=ADC3_IN10,IN10
SH.ADCx_IN10.ConfNb=1
SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
@ -451,6 +473,11 @@ TIM13.Prescaler=90-1
TIM3.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
TIM3.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
TIM8.IPParameters=Prescaler,Period,TIM_MasterSlaveMode,TIM_MasterOutputTrigger
TIM8.Period=1000
TIM8.Prescaler=180-1
TIM8.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
TIM8.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
USART6.IPParameters=VirtualMode
@ -473,4 +500,6 @@ VP_TIM1_VS_ClockSourceINT.Mode=Internal
VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
VP_TIM3_VS_ClockSourceINT.Mode=Internal
VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
VP_TIM8_VS_ClockSourceINT.Mode=Internal
VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
board=custom