diff --git a/.gitignore b/.gitignore index cf821df..76eefbb 100644 --- a/.gitignore +++ b/.gitignore @@ -58,3 +58,6 @@ JLinkLog.txt # VS Code Generated Files /.vs/ +/MATLAB/MCU.exp +/MATLAB/MCU.lib +/MATLAB/MCU.mexw64.manifest diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xb_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xb_matlab.h index dbb699e..60f20d2 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xb_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xb_matlab.h @@ -262,8 +262,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xe_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xe_matlab.h index 9a937a0..7237b71 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xe_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f100xe_matlab.h @@ -310,8 +310,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101x6_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101x6_matlab.h index bf9d0e0..8d03ab6 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101x6_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101x6_matlab.h @@ -215,8 +215,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xb_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xb_matlab.h index 6c67d89..ca0107b 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xb_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xb_matlab.h @@ -220,8 +220,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xe_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xe_matlab.h index cab9bb7..e857442 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xe_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xe_matlab.h @@ -284,8 +284,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xg_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xg_matlab.h index abc990b..739da2c 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xg_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f101xg_matlab.h @@ -290,8 +290,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102x6_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102x6_matlab.h index b4d7d24..eb5752f 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102x6_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102x6_matlab.h @@ -218,8 +218,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102xb_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102xb_matlab.h index 888c1c8..e392d84 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102xb_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f102xb_matlab.h @@ -223,8 +223,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103x6_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103x6_matlab.h index 47f7488..21da38d 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103x6_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103x6_matlab.h @@ -287,8 +287,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xb_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xb_matlab.h index 394c977..550f4a4 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xb_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xb_matlab.h @@ -293,8 +293,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct @@ -592,7 +592,7 @@ typedef struct _memory { //uint8_t RESERVED[FLASH_BASE_SHIFT]; - uint8_t FLASH_BASE[FLASH_SIZE]; + uint8_t FLASH_BASE[10]; uint8_t FLASH_BANK1_END[10]; uint8_t SRAM_BASE[SRAM_SIZE]; uint8_t SRAM_BB_BASE[SRAM_SIZE]; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xe_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xe_matlab.h index 292c86b..a860faf 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xe_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xe_matlab.h @@ -362,8 +362,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xg_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xg_matlab.h index bd073d8..426dd75 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xg_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f103xg_matlab.h @@ -362,8 +362,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f105xc_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f105xc_matlab.h index 724c495..9b48c43 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f105xc_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f105xc_matlab.h @@ -361,8 +361,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f107xc_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f107xc_matlab.h index 9947728..81e6dc3 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f107xc_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F1xx/stm32f107xc_matlab.h @@ -363,8 +363,8 @@ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; + __IO uint64_t CPAR; + __IO uint64_t CMAR; } DMA_Channel_TypeDef; typedef struct diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xc_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xc_matlab.h index 610ab3a..3b4a041 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xc_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xc_matlab.h @@ -223,9 +223,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xe_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xe_matlab.h index 6549a19..a42d2af 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xe_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f401xe_matlab.h @@ -223,9 +223,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f405xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f405xx_matlab.h index eaaca4b..1b3fc71 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f405xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f405xx_matlab.h @@ -334,9 +334,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f407xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f407xx_matlab.h index 9609c9a..514f98b 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f407xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f407xx_matlab.h @@ -358,9 +358,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410cx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410cx_matlab.h index d0004fd..12d46ce 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410cx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410cx_matlab.h @@ -241,9 +241,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410rx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410rx_matlab.h index ee99544..9343b21 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410rx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410rx_matlab.h @@ -241,9 +241,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410tx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410tx_matlab.h index 04dbe52..1afbac8 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410tx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f410tx_matlab.h @@ -238,9 +238,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f411xe_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f411xe_matlab.h index 0a6b5ee..b16a15a 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f411xe_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f411xe_matlab.h @@ -224,9 +224,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412cx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412cx_matlab.h index 8a24b1c..08218f2 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412cx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412cx_matlab.h @@ -344,9 +344,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412rx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412rx_matlab.h index 2c65b22..97c1830 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412rx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412rx_matlab.h @@ -345,9 +345,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412vx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412vx_matlab.h index c5300cd..d472ba7 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412vx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412vx_matlab.h @@ -345,9 +345,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412zx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412zx_matlab.h index cc609ec..8aa9e5e 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412zx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f412zx_matlab.h @@ -345,9 +345,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f413xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f413xx_matlab.h index 62dd13f..6308d3f 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f413xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f413xx_matlab.h @@ -383,9 +383,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f415xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f415xx_matlab.h index 6538086..8a6508c 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f415xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f415xx_matlab.h @@ -333,9 +333,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f417xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f417xx_matlab.h index 8617ba8..fd8fe93 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f417xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f417xx_matlab.h @@ -354,9 +354,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f423xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f423xx_matlab.h index bd926b4..2e0f5fa 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f423xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f423xx_matlab.h @@ -384,9 +384,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f427xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f427xx_matlab.h index be49cd9..f63f572 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f427xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f427xx_matlab.h @@ -360,9 +360,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f429xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f429xx_matlab.h index 865f23c..4a1a4bd 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f429xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f429xx_matlab.h @@ -362,9 +362,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f437xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f437xx_matlab.h index b26ff5e..8fc92ef 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f437xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f437xx_matlab.h @@ -361,9 +361,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f439xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f439xx_matlab.h index 5c412e4..f9ddae2 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f439xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f439xx_matlab.h @@ -363,9 +363,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f446xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f446xx_matlab.h index 12383be..9d330d6 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f446xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f446xx_matlab.h @@ -372,9 +372,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f469xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f469xx_matlab.h index a006ccd..8b3975f 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f469xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f469xx_matlab.h @@ -364,9 +364,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f479xx_matlab.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f479xx_matlab.h index 97f7620..8b5431e 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f479xx_matlab.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/Device/STM32F4xx/stm32f479xx_matlab.h @@ -365,9 +365,9 @@ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint64_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint64_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint64_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/arm_defines.h b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/arm_defines.h index 8604f58..e31109d 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/arm_defines.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/CMSIS/arm_defines.h @@ -91,10 +91,15 @@ #define __CLZ #define __CTZ #define __RBIT - +#ifdef __MINGW64__ #ifndef __weak #define __weak __attribute__((weak)) #endif +#else +#ifndef __weak +#define __weak +#endif +#endif #define __DSB() #define __ISB() #define __NOP() diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.c b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.c index e7fa495..d199507 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.c +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.c @@ -1,4 +1,5 @@ #include "stm32_matlab_adc.h" +#include "stm32_matlab_dma.h" #include @@ -22,19 +23,26 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) { if (!(ADCx->CR2 & ADC_CR2_ADON)) return; - // Start conversion on SWSTART + // ПЕРВОЕ: Проверка внешнего триггера (для режима по триггеру) + if (!(ADCx->CR2 & ADC_CR2_CONT)) { // Только если не continuous mode + ADC_Check_External_Trigger(ADCx, ADCS); + } + + // ВТОРОЕ: Software trigger if (ADCx->CR2 & ADC_CR2_SWSTART) { ADC_Start_Conversion(ADCx, ADCS); ADCx->CR2 &= ~ADC_CR2_SWSTART; } - // Handle ongoing conversion - + // ТРЕТЬЕ: Обработка текущего преобразования if (ADCS->conversion_time_elapsed >= 0) { ADCS->conversion_time_elapsed += ADCS->simulation_step; - double total_time = ADC_Get_Total_Conversion_Time(ADCx, ADCS); + + // ИСПОЛЬЗУЕМ ОБЩЕЕ ВРЕМЯ ДЛЯ ВСЕЙ ПОСЛЕДОВАТЕЛЬНОСТИ + double total_time = ADC_Get_Total_Sequence_Time(ADCx, ADCS); if (ADCS->conversion_time_elapsed >= total_time) { - ADC_Complete_Conversion(ADCx, ADCS); + ADC_Complete_Conversion(ADCx, ADCS); // Обрабатываем ВСЕ каналы // Continuous mode auto-restart if (ADCx->CR2 & ADC_CR2_CONT) { @@ -42,19 +50,18 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) } } } - } void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) { - // + // Определяем канал для конверсии if (ADCx->CR1 & ADC_CR1_SCAN) { - // + // Режим сканирования ADCS->current_rank = 0; ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, 0); } else { - // + // Одиночный канал ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, 0); } @@ -63,81 +70,210 @@ void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) void ADC_Complete_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) { - // - double analog_val = 0; - if (ADCS->channel_connected[ADCS->current_channel]) { - analog_val = ADCS->channel_values[ADCS->current_channel]; + uint32_t seq_len = ADC_Get_Sequence_Length(ADCx); + + // Обрабатываем ВСЕ каналы последовательности за один вызов + for (uint32_t rank = 0; rank < seq_len; rank++) { + uint32_t channel = ADC_Get_Sequence_Channel(ADCx, rank); + + // 1. Конвертируем один канал + double analog_val = 0; + if (ADCS->channel_connected[channel]) { + analog_val = ADCS->channel_values[channel]; + } + + if (analog_val < 0) analog_val = 0; + if (analog_val > 3.3) analog_val = 3.3; + + // Вычисляем значение АЦП + ADCS->last_conversion_value = (uint16_t)((analog_val / 3.3) * 4095.0); + + // Добавляем шум + int32_t noisy_value = (int32_t)ADCS->last_conversion_value + (rand() % (2 * ADC_NOISE_LSB + 1)) - ADC_NOISE_LSB; + if (noisy_value < 0) noisy_value = 0; + if (noisy_value > 4095) noisy_value = 4095; + + ADCS->last_conversion_value = (uint16_t)noisy_value; + + // 2. Записываем в DR + ADCx->DR = ADCS->last_conversion_value; + + // 3. Устанавливаем флаг EOC + ADCx->SR |= ADC_SR_EOC; + + // 4. СРАЗУ вызываем DMA для этой конверсии + if (ADCx->CR2 & ADC_CR2_DMA) { + if (ADCx == ADC3) { + DMA_Sim_Transfer(DMA2, 0); // Выполняем одну передачу + } + else if (ADCx == ADC1) { + DMA_Sim_Transfer(DMA2, 4); // Для ADC1 + } + } } - if (analog_val < 0) - analog_val = 0; - if (analog_val > 3.3) - analog_val = 3.3; - - - // - ADCS->last_conversion_value = (uint16_t)((analog_val / 3.3) * 4095.0); - - // LSB - int32_t noisy_value = (int32_t)ADCS->last_conversion_value + (rand() % (2 * ADC_NOISE_LSB + 1)) - ADC_NOISE_LSB; - - // - if (noisy_value < 0) noisy_value = 0; - if (noisy_value > 4095) noisy_value = 4095; - - ADCS->last_conversion_value = (uint16_t)noisy_value; - - // DR - ADCx->DR = ADCS->last_conversion_value; - - // EOC + // Устанавливаем EOS в конце последовательности ADCx->SR |= ADC_SR_EOC; - // DMA - if (ADCx->CR2 & ADC_CR2_DMA) { - ADC_DMA_Transfer(ADCx, ADCS); - } - - // - if (ADCx->CR1 & ADC_CR1_SCAN) { - ADCS->current_rank++; - uint32_t seq_len = ADC_Get_Sequence_Length(ADCx); - - if (ADCS->current_rank < seq_len) { - // - ADCS->current_channel = ADC_Get_Sequence_Channel(ADCx, ADCS->current_rank); - ADCS->conversion_time_elapsed = 0; - return; - } - else { - // -#ifdef ADC_SR_EOS - ADCx->SR |= ADC_SR_EOS; -#endif - } - } - - ADCS->conversion_time_elapsed = 0; + ADCS->conversion_time_elapsed = -1; } +/////////////////////////////---TIMER TRIGGER SUPPORT---////////////////////////// +uint8_t ADC_Check_Timer_Trigger(ADC_TypeDef* ADCx, uint32_t trigger_source) +{ + // Анализируем источник триггера из регистров ADC + switch (trigger_source) { +#ifdef ADC_EXTERNALTRIGCONV_T2_TRGO + case ADC_EXTERNALTRIGCONV_T2_TRGO: + return Slave_Channels.TIM2_TRGO; +#endif + +#ifdef ADC_EXTERNALTRIGCONV_T3_TRGO + case ADC_EXTERNALTRIGCONV_T3_TRGO: + return Slave_Channels.TIM3_TRGO; +#endif + +#ifdef ADC_EXTERNALTRIGCONV_T8_TRGO + case ADC_EXTERNALTRIGCONV_T8_TRGO: + return Slave_Channels.TIM8_TRGO; +#endif + + +#ifdef ADC_EXTERNALTRIGCONV_T1_CC1 + case ADC_EXTERNALTRIGCONV_T1_CC1: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T1_CC2 + case ADC_EXTERNALTRIGCONV_T1_CC2: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T1_CC3 + case ADC_EXTERNALTRIGCONV_T1_CC3: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T2_CC2 + case ADC_EXTERNALTRIGCONV_T2_CC2: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T2_CC3 + case ADC_EXTERNALTRIGCONV_T2_CC3: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T2_CC4 + case ADC_EXTERNALTRIGCONV_T2_CC4: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T3_CC1 + case ADC_EXTERNALTRIGCONV_T3_CC1: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T4_CC4 + case ADC_EXTERNALTRIGCONV_T4_CC4: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T5_CC1 + case ADC_EXTERNALTRIGCONV_T5_CC1: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T5_CC2 + case ADC_EXTERNALTRIGCONV_T5_CC2: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T5_CC3 + case ADC_EXTERNALTRIGCONV_T5_CC3: +#endif +#ifdef ADC_EXTERNALTRIGCONV_T8_CC1 + case ADC_EXTERNALTRIGCONV_T8_CC1: +#endif +#ifdef ADC_EXTERNALTRIGCONV_Ext_IT11 + case ADC_EXTERNALTRIGCONV_Ext_IT11: +#endif + default: + return 0; + } +} + +void ADC_Check_External_Trigger(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) +{ +#ifdef STM32F1 + // Для STM32F1 проверяем бит EXTTRIG + if (!(ADCx->CR2 & ADC_CR2_EXTTRIG)) return; + + // Получаем источник триггера и фронт + uint32_t trigger_source = (ADCx->CR2 & ADC_CR2_EXTSEL); // Для F1 EXTSEL[2:0] биты 19:17 + uint32_t trigger_edge = (ADCx->CR2 & ADC_CR2_EXTTRIG) ? 1 : 0; // Для F1 просто включен/выключен + +#elif defined(STM32F4) + // Для STM32F4 проверяем EXTEN и EXTSEL + if (!(ADCx->CR2 & ADC_CR2_EXTEN)) return; // Для F4 проверяем EXTEN + + // Получаем источник триггера и фронт + uint32_t trigger_source = (ADCx->CR2 & ADC_CR2_EXTSEL); + uint32_t trigger_edge = (ADCx->CR2 & ADC_CR2_EXTEN); + +#else + return; // Неподдерживаемая платформа +#endif + + uint8_t current_trigger_state = ADC_Check_Timer_Trigger(ADCx, trigger_source); + uint8_t trigger_occurred = 0; + +#ifdef STM32F1 + // Для F1 - простой rising edge при наличии триггера + if (trigger_edge) { + trigger_occurred = current_trigger_state && !ADCS->last_trigger_state; + } +#endif +#ifdef STM32F4 + switch (trigger_edge) + { + case ADC_EXTERNALTRIGCONVEDGE_RISING: + trigger_occurred = current_trigger_state && !ADCS->last_trigger_state; + break; + + case ADC_EXTERNALTRIGCONVEDGE_FALLING: + trigger_occurred = !current_trigger_state && ADCS->last_trigger_state; + break; + + case ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING: + trigger_occurred = (current_trigger_state && !ADCS->last_trigger_state) || + (!current_trigger_state && ADCS->last_trigger_state); + break; + + default: + break; + } +#endif + + if (trigger_occurred) { + ADC_Start_Conversion(ADCx, ADCS); + } + + ADCS->last_trigger_state = current_trigger_state; +} + + /////////////////////////////---REGISTER-BASED FUNCTIONS---/////////////////// double ADC_Get_Total_Conversion_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) { - // sampling time + // Получаем sampling time из регистров uint32_t sampling_cycles = ADC_Get_Sampling_Cycles(ADCx, ADCS->current_channel); - // Conversion cycles - uint32_t conversion_cycles = 12; // 12-bit + // Conversion cycles фиксированы для разрешения + uint32_t conversion_cycles = 12; // Для 12-bit double total_cycles = sampling_cycles + conversion_cycles; - double adc_clock = ADCS->adc_clock_freq; // + double adc_clock = ADCS->adc_clock_freq; // Частота шины return total_cycles / adc_clock; } +double ADC_Get_Total_Sequence_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) +{ + uint32_t total_cycles = 0; + uint32_t seq_len = ADC_Get_Sequence_Length(ADCx); + + for (uint32_t rank = 0; rank < seq_len; rank++) { + uint32_t channel = ADC_Get_Sequence_Channel(ADCx, rank); + uint32_t sampling_cycles = ADC_Get_Sampling_Cycles(ADCx, channel); + total_cycles += sampling_cycles + 12; // sampling + conversion + } + + return total_cycles / ADCS->adc_clock_freq; +} uint32_t ADC_Get_Sampling_Cycles(ADC_TypeDef* ADCx, uint32_t channel) { - // sampling time SMPR1/SMPR2 + // Получаем sampling time из SMPR1/SMPR2 uint32_t smpr_code; if (channel <= 9) { smpr_code = (ADCx->SMPR2 >> (channel * 3)) & 0x7; @@ -176,7 +312,7 @@ uint32_t ADC_Get_Sequence_Channel(ADC_TypeDef* ADCx, uint32_t rank) } /////////////////////////////---DMA FUNCTIONS---/////////////////////////////// -void ADC_DMA_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) +void ADC_DMA_Sim_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS) { if (!ADCS->dma_buffer || ADCS->dma_buffer_size == 0) return; diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.h b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.h index feea8fe..26d8697 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_adc.h @@ -5,11 +5,11 @@ #ifdef STM32F1 -#define ADC_NOISE_LSB 10 // Шум в LSB (квантах АЦП) +#define ADC_NOISE_LSB 30 // Большой шум STMF103 в LSB (квантах АЦП) #endif #ifdef STM32F4 -#define ADC_NOISE_LSB 2 // Шум в LSB (квантах АЦП) +#define ADC_NOISE_LSB 10 // Шум в LSB (квантах АЦП) #endif /////////////////////////////---STRUCTURES---/////////////////////////// @@ -32,6 +32,11 @@ struct ADC_Sim // Timing double simulation_step; double adc_clock_freq; + + // Добавьте для поддержки триггеров + uint8_t external_trigger_enabled; + uint32_t trigger_source; + uint8_t last_trigger_state; }; /////////////////////////////////////////////////////////////////////// @@ -42,11 +47,13 @@ void ADC_Simulation(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); void ADC_Start_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); void ADC_Complete_Conversion(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); +void ADC_Check_External_Trigger(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); double ADC_Get_Total_Conversion_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); +double ADC_Get_Total_Sequence_Time(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); uint32_t ADC_Get_Sampling_Cycles(ADC_TypeDef* ADCx, uint32_t channel); uint32_t ADC_Get_Sequence_Length(ADC_TypeDef* ADCx); uint32_t ADC_Get_Sequence_Channel(ADC_TypeDef* ADCx, uint32_t rank); -void ADC_DMA_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); +void ADC_DMA_Sim_Transfer(ADC_TypeDef* ADCx, struct ADC_Sim* ADCS); void ADC_Set_Channel_Value(ADC_TypeDef* ADCx, uint32_t channel, double voltage); void ADC_SIM_DEINIT(void); diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.c b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.c new file mode 100644 index 0000000..7a85299 --- /dev/null +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.c @@ -0,0 +1,591 @@ +#include "stm32_matlab_dma.h" +#include + +// DMA stream simulation structures +#ifdef USE_DMA1 +struct DMA_Stream_Sim dma1_stream0s; +struct DMA_Stream_Sim dma1_stream1s; +struct DMA_Stream_Sim dma1_stream2s; +struct DMA_Stream_Sim dma1_stream3s; +struct DMA_Stream_Sim dma1_stream4s; +struct DMA_Stream_Sim dma1_stream5s; +struct DMA_Stream_Sim dma1_stream6s; +struct DMA_Stream_Sim dma1_stream7s; +#endif + +#ifdef USE_DMA2 +struct DMA_Stream_Sim dma2_stream0s; +struct DMA_Stream_Sim dma2_stream1s; +struct DMA_Stream_Sim dma2_stream2s; +struct DMA_Stream_Sim dma2_stream3s; +struct DMA_Stream_Sim dma2_stream4s; +struct DMA_Stream_Sim dma2_stream5s; +struct DMA_Stream_Sim dma2_stream6s; +struct DMA_Stream_Sim dma2_stream7s; +#endif + +void DMA_Call_IRQHandller(DMA_TypeDef* DMAx, uint32_t stream); + +// Модифицируем основную функцию выполнения передачи +void DMA_Sim_Transfer(DMA_TypeDef* DMAx, uint32_t stream) +{ + struct DMA_Stream_Sim* stream_sim = DMA_Get_Stream_Sim(DMAx, stream); + if (!stream_sim) return; + + // Проверяем включен ли stream в регистрах + uint8_t hardware_enabled = DMA_Is_Stream_Enabled(DMAx, stream); + + if (!hardware_enabled) { + // Если аппаратно выключен, сбрасываем состояние + if (stream_sim->enabled) { + memset(stream_sim, 0, sizeof(struct DMA_Stream_Sim)); + } + return; + } + + // Если аппаратно включен, инициализируем если нужно + if (!stream_sim->enabled) { + stream_sim->peripheral_address = DMA_Get_Peripheral_Address(DMAx, stream); + stream_sim->memory_address = DMA_Get_Memory_Address(DMAx, stream); + stream_sim->buffer_size = DMA_Get_Buffer_Size(DMAx, stream); + stream_sim->circular_mode = DMA_Get_Circular_Mode(DMAx, stream); + stream_sim->data_size = DMA_Get_DataSize(DMAx, stream); // Сохраняем размер данных + stream_sim->current_index = 0; + stream_sim->transfer_complete = 0; + stream_sim->enabled = 1; + stream_sim->transfer_enabled = 1; + } + + // Проверяем нужно ли выполнить передачу + if (!stream_sim->transfer_enabled) return; + if (!stream_sim->peripheral_address || !stream_sim->memory_address) return; + + + // ВЫПОЛНЯЕМ ПЕРЕДАЧУ С УЧЕТОМ РАЗМЕРА ДАННЫХ + switch (stream_sim->data_size) { + case 1: // 8-bit data + { + uint8_t current_value = *(uint8_t*)stream_sim->peripheral_address; + ((uint8_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value; + } + break; + + case 2: // 16-bit data + { + uint16_t current_value = *(uint16_t*)stream_sim->peripheral_address; + ((uint16_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value; + } + break; + + case 4: // 32-bit data + { + uint32_t current_value = *(uint32_t*)stream_sim->peripheral_address; + ((uint32_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value; + } + break; + + default: // По умолчанию 8-bit + { + uint8_t current_value = *(uint8_t*)stream_sim->peripheral_address; + ((uint8_t*)stream_sim->memory_address)[stream_sim->current_index] = current_value; + } + break; + } + + stream_sim->current_index++; + + + // Проверяем завершение передачи + if (stream_sim->current_index >= stream_sim->buffer_size) { + stream_sim->transfer_complete = 1; + if (stream_sim->circular_mode) { + stream_sim->current_index = 0; + } else { + stream_sim->transfer_enabled = 0; + stream_sim->enabled = 0; + DMA_Call_IRQHandller(DMAx, stream); + } + } +} + + +/////////////////////////////---HELPER FUNCTIONS---////////////////////////// +struct DMA_Stream_Sim* DMA_Get_Stream_Sim(DMA_TypeDef* DMAx, uint32_t stream) +{ +#ifdef USE_DMA1 + if (DMAx == DMA1) { + switch (stream) { + case 0: return &dma1_stream0s; + case 1: return &dma1_stream1s; + case 2: return &dma1_stream2s; + case 3: return &dma1_stream3s; + case 4: return &dma1_stream4s; + case 5: return &dma1_stream5s; + case 6: return &dma1_stream6s; + case 7: return &dma1_stream7s; + } + } +#endif + +#ifdef USE_DMA2 + if (DMAx == DMA2) { + switch (stream) { + case 0: return &dma2_stream0s; + case 1: return &dma2_stream1s; + case 2: return &dma2_stream2s; + case 3: return &dma2_stream3s; + case 4: return &dma2_stream4s; + case 5: return &dma2_stream5s; + case 6: return &dma2_stream6s; + case 7: return &dma2_stream7s; + } + } +#endif + + return NULL; +} + +uint8_t DMA_Is_Stream_Enabled(DMA_TypeDef* DMAx, uint32_t stream) +{ + // Проверяем регистры DMA чтобы определить включен ли stream +#ifdef STM32F1 + if (DMAx == DMA1) { + volatile uint32_t* cr_reg = NULL; + + switch (stream) { + case 0: cr_reg = &DMA1_Channel1->CCR; break; + case 1: cr_reg = &DMA1_Channel2->CCR; break; + case 2: cr_reg = &DMA1_Channel3->CCR; break; + case 3: cr_reg = &DMA1_Channel4->CCR; break; + case 4: cr_reg = &DMA1_Channel5->CCR; break; + case 5: cr_reg = &DMA1_Channel6->CCR; break; + case 6: cr_reg = &DMA1_Channel7->CCR; break; + } + + if (cr_reg) { + return (*cr_reg & DMA_CCR_EN) != 0; + } + } +#elif defined(STM32F4) + if (DMAx == DMA1) { + volatile uint32_t* cr_reg = NULL; + + switch (stream) { + case 0: cr_reg = &DMA1_Stream0->CR; break; + case 1: cr_reg = &DMA1_Stream1->CR; break; + case 2: cr_reg = &DMA1_Stream2->CR; break; + case 3: cr_reg = &DMA1_Stream3->CR; break; + case 4: cr_reg = &DMA1_Stream4->CR; break; + case 5: cr_reg = &DMA1_Stream5->CR; break; + case 6: cr_reg = &DMA1_Stream6->CR; break; + case 7: cr_reg = &DMA1_Stream7->CR; break; + } + + if (cr_reg) { + return (*cr_reg & DMA_SxCR_EN) != 0; + } + } + else if (DMAx == DMA2) { + volatile uint32_t* cr_reg = NULL; + + switch (stream) { + case 0: cr_reg = &DMA2_Stream0->CR; break; + case 1: cr_reg = &DMA2_Stream1->CR; break; + case 2: cr_reg = &DMA2_Stream2->CR; break; + case 3: cr_reg = &DMA2_Stream3->CR; break; + case 4: cr_reg = &DMA2_Stream4->CR; break; + case 5: cr_reg = &DMA2_Stream5->CR; break; + case 6: cr_reg = &DMA2_Stream6->CR; break; + case 7: cr_reg = &DMA2_Stream7->CR; break; + } + + if (cr_reg) { + return (*cr_reg & DMA_SxCR_EN) != 0; + } + } +#endif + return 0; +} + +uint32_t* DMA_Get_Peripheral_Address(DMA_TypeDef* DMAx, uint32_t stream) +{ + // Получаем адрес периферии из регистров DMA +#ifdef STM32F1 + if (DMAx == DMA1) { + switch (stream) { + case 0: return (uint64_t*)DMA1_Channel1->CPAR; + case 1: return (uint64_t*)DMA1_Channel2->CPAR; + case 2: return (uint64_t*)DMA1_Channel3->CPAR; + case 3: return (uint64_t*)DMA1_Channel4->CPAR; + case 4: return (uint64_t*)DMA1_Channel5->CPAR; + case 5: return (uint64_t*)DMA1_Channel6->CPAR; + case 6: return (uint64_t*)DMA1_Channel7->CPAR; + } + } +#elif defined(STM32F4) + if (DMAx == DMA1) { + volatile uint64_t* par_reg = NULL; + + switch (stream) { + case 0: par_reg = &DMA1_Stream0->PAR; break; + case 1: par_reg = &DMA1_Stream1->PAR; break; + case 2: par_reg = &DMA1_Stream2->PAR; break; + case 3: par_reg = &DMA1_Stream3->PAR; break; + case 4: par_reg = &DMA1_Stream4->PAR; break; + case 5: par_reg = &DMA1_Stream5->PAR; break; + case 6: par_reg = &DMA1_Stream6->PAR; break; + case 7: par_reg = &DMA1_Stream7->PAR; break; + } + + if (par_reg) { + return (uint64_t*)*par_reg; + } + } + else if (DMAx == DMA2) { + volatile uint64_t* par_reg = NULL; + + switch (stream) { + case 0: par_reg = &DMA2_Stream0->PAR; break; + case 1: par_reg = &DMA2_Stream1->PAR; break; + case 2: par_reg = &DMA2_Stream2->PAR; break; + case 3: par_reg = &DMA2_Stream3->PAR; break; + case 4: par_reg = &DMA2_Stream4->PAR; break; + case 5: par_reg = &DMA2_Stream5->PAR; break; + case 6: par_reg = &DMA2_Stream6->PAR; break; + case 7: par_reg = &DMA2_Stream7->PAR; break; + } + + if (par_reg) { + return (uint64_t*)*par_reg; + } + } +#endif + return NULL; +} + +uint32_t* DMA_Get_Memory_Address(DMA_TypeDef* DMAx, uint32_t stream) +{ + // Получаем адрес памяти из регистров DMA + +#ifdef STM32F1 + if (DMAx == DMA1) { + switch (stream) { + case 0: return (uint64_t*)DMA1_Channel1->CPAR; + case 1: return (uint64_t*)DMA1_Channel2->CPAR; + case 2: return (uint64_t*)DMA1_Channel3->CPAR; + case 3: return (uint64_t*)DMA1_Channel4->CPAR; + case 4: return (uint64_t*)DMA1_Channel5->CPAR; + case 5: return (uint64_t*)DMA1_Channel6->CPAR; + case 6: return (uint64_t*)DMA1_Channel7->CPAR; + } + } +#elif defined(STM32F4) + if (DMAx == DMA1) { + volatile uint64_t* mar_reg = NULL; + + switch (stream) { + case 0: mar_reg = &DMA1_Stream0->M0AR; break; + case 1: mar_reg = &DMA1_Stream1->M0AR; break; + case 2: mar_reg = &DMA1_Stream2->M0AR; break; + case 3: mar_reg = &DMA1_Stream3->M0AR; break; + case 4: mar_reg = &DMA1_Stream4->M0AR; break; + case 5: mar_reg = &DMA1_Stream5->M0AR; break; + case 6: mar_reg = &DMA1_Stream6->M0AR; break; + case 7: mar_reg = &DMA1_Stream7->M0AR; break; + } + + if (mar_reg) { + return (uint64_t*)*mar_reg; + } + } + else if (DMAx == DMA2) { + volatile uint64_t* mar_reg = NULL; + + switch (stream) { + case 0: mar_reg = &DMA2_Stream0->M0AR; break; + case 1: mar_reg = &DMA2_Stream1->M0AR; break; + case 2: mar_reg = &DMA2_Stream2->M0AR; break; + case 3: mar_reg = &DMA2_Stream3->M0AR; break; + case 4: mar_reg = &DMA2_Stream4->M0AR; break; + case 5: mar_reg = &DMA2_Stream5->M0AR; break; + case 6: mar_reg = &DMA2_Stream6->M0AR; break; + case 7: mar_reg = &DMA2_Stream7->M0AR; break; + } + + if (mar_reg) { + return (uint64_t*)*mar_reg; + } + } +#endif + return NULL; +} + +uint32_t DMA_Get_Buffer_Size(DMA_TypeDef* DMAx, uint32_t stream) +{ + // Получаем размер буфера из регистров DMA +#ifdef STM32F1 + if (DMAx == DMA1) { + switch (stream) { + case 0: return DMA1_Channel1->CNDTR; + case 1: return DMA1_Channel2->CNDTR; + case 2: return DMA1_Channel3->CNDTR; + case 3: return DMA1_Channel4->CNDTR; + case 4: return DMA1_Channel5->CNDTR; + case 5: return DMA1_Channel6->CNDTR; + case 6: return DMA1_Channel7->CNDTR; + } + } +#elif defined(STM32F4) + if (DMAx == DMA1) { + volatile uint64_t* mar_reg = NULL; + + switch (stream) { + case 0: mar_reg = &DMA1_Stream0->NDTR; break; + case 1: mar_reg = &DMA1_Stream1->NDTR; break; + case 2: mar_reg = &DMA1_Stream2->NDTR; break; + case 3: mar_reg = &DMA1_Stream3->NDTR; break; + case 4: mar_reg = &DMA1_Stream4->NDTR; break; + case 5: mar_reg = &DMA1_Stream5->NDTR; break; + case 6: mar_reg = &DMA1_Stream6->NDTR; break; + case 7: mar_reg = &DMA1_Stream7->NDTR; break; + } + + if (mar_reg) { + return (uint64_t*)*mar_reg; + } + } + else if (DMAx == DMA2) { + volatile uint64_t* mar_reg = NULL; + + switch (stream) { + case 0: mar_reg = &DMA2_Stream0->NDTR; break; + case 1: mar_reg = &DMA2_Stream1->NDTR; break; + case 2: mar_reg = &DMA2_Stream2->NDTR; break; + case 3: mar_reg = &DMA2_Stream3->NDTR; break; + case 4: mar_reg = &DMA2_Stream4->NDTR; break; + case 5: mar_reg = &DMA2_Stream5->NDTR; break; + case 6: mar_reg = &DMA2_Stream6->NDTR; break; + case 7: mar_reg = &DMA2_Stream7->NDTR; break; + } + + if (mar_reg) { + return (uint64_t*)*mar_reg; + } + } +#endif + return 0; +} + +uint8_t DMA_Get_Circular_Mode(DMA_TypeDef* DMAx, uint32_t stream) +{ + // Проверяем циклический режим +#ifdef STM32F1 + if (DMAx == DMA1) { + switch (stream) { + case 0: return (DMA1_Channel1->CCR & DMA_CCR_CIRC) != 0; + case 1: return (DMA1_Channel2->CCR & DMA_CCR_CIRC) != 0; + case 2: return (DMA1_Channel3->CCR & DMA_CCR_CIRC) != 0; + case 3: return (DMA1_Channel4->CCR & DMA_CCR_CIRC) != 0; + case 4: return (DMA1_Channel5->CCR & DMA_CCR_CIRC) != 0; + case 5: return (DMA1_Channel6->CCR & DMA_CCR_CIRC) != 0; + case 6: return (DMA1_Channel7->CCR & DMA_CCR_CIRC) != 0; + } + } + if (DMAx == DMA1) { + switch (stream) { + case 0: return (DMA1_Stream1->CR & DMA_SxCR_CIRC) != 0; + case 1: return (DMA1_Stream11->CR & DMA_SxCR_CIRC) != 0; + case 2: return (DMA1_Stream13->CR & DMA_SxCR_CIRC) != 0; + case 3: return (DMA1_Stream14->CR & DMA_SxCR_CIRC) != 0; + case 4: return (DMA1_Stream15->CR & DMA_SxCR_CIRC) != 0; + case 5: return (DMA1_Stream16->CR & DMA_SxCR_CIRC) != 0; + case 6: return (DMA1_Stream17->CR & DMA_SxCR_CIRC) != 0; + } + } +#elif defined(STM32F4) + if (DMAx == DMA1 || DMAx == DMA2) { + volatile uint32_t* cr_reg = NULL; + + switch (stream) { + case 0: return (DMA2_Stream1->CR & DMA_SxCR_CIRC) != 0; + case 1: return (DMA2_Stream1->CR & DMA_SxCR_CIRC) != 0; + case 2: return (DMA2_Stream3->CR & DMA_SxCR_CIRC) != 0; + case 3: return (DMA2_Stream4->CR & DMA_SxCR_CIRC) != 0; + case 4: return (DMA2_Stream5->CR & DMA_SxCR_CIRC) != 0; + case 5: return (DMA2_Stream6->CR & DMA_SxCR_CIRC) != 0; + case 6: return (DMA2_Stream7->CR & DMA_SxCR_CIRC) != 0; + } + } +#endif + return 0; +} +// функцию для определения размера данных DMA +uint32_t DMA_Get_DataSize(DMA_TypeDef* DMAx, uint32_t stream) +{ +#ifdef STM32F4 + if (DMAx == DMA1 || DMAx == DMA2) { + volatile uint32_t* cr_reg = NULL; + + // Получаем регистр CR для соответствующего потока + if (DMAx == DMA1) { + switch (stream) { + case 0: cr_reg = &DMA1_Stream0->CR; break; + case 1: cr_reg = &DMA1_Stream1->CR; break; + case 2: cr_reg = &DMA1_Stream2->CR; break; + case 3: cr_reg = &DMA1_Stream3->CR; break; + case 4: cr_reg = &DMA1_Stream4->CR; break; + case 5: cr_reg = &DMA1_Stream5->CR; break; + case 6: cr_reg = &DMA1_Stream6->CR; break; + case 7: cr_reg = &DMA1_Stream7->CR; break; + } + } + else if (DMAx == DMA2) { + switch (stream) { + case 0: cr_reg = &DMA2_Stream0->CR; break; + case 1: cr_reg = &DMA2_Stream1->CR; break; + case 2: cr_reg = &DMA2_Stream2->CR; break; + case 3: cr_reg = &DMA2_Stream3->CR; break; + case 4: cr_reg = &DMA2_Stream4->CR; break; + case 5: cr_reg = &DMA2_Stream5->CR; break; + case 6: cr_reg = &DMA2_Stream6->CR; break; + case 7: cr_reg = &DMA2_Stream7->CR; break; + } + } + + if (cr_reg) { + uint32_t psize = (*cr_reg & DMA_SxCR_PSIZE); + + // Определяем размер данных на основе битов PSIZE + switch (psize) { + case DMA_PDATAALIGN_BYTE: // 00: Byte alignment (8-bit) + return 1; + case DMA_PDATAALIGN_HALFWORD: // 01: HalfWord alignment (16-bit) + return 2; + case DMA_PDATAALIGN_WORD: // 10: Word alignment (32-bit) + return 4; + default: + return 1; // По умолчанию байт + } + } + } +#elif defined(STM32F1) + // Для STM32F1 логика может отличаться + if (DMAx == DMA1) { + volatile uint32_t* ccr_reg = NULL; + + switch (stream) { + case 0: ccr_reg = &DMA1_Channel1->CCR; break; + case 1: ccr_reg = &DMA1_Channel2->CCR; break; + case 2: ccr_reg = &DMA1_Channel3->CCR; break; + case 3: ccr_reg = &DMA1_Channel4->CCR; break; + case 4: ccr_reg = &DMA1_Channel5->CCR; break; + case 5: ccr_reg = &DMA1_Channel6->CCR; break; + case 6: ccr_reg = &DMA1_Channel7->CCR; break; + } + + if (ccr_reg) { + // В STM32F1 размер определяется битами MSIZE[1:0] и PSIZE[1:0] + uint32_t size_bits = (*ccr_reg & (DMA_CCR_MSIZE | DMA_CCR_PSIZE)); + // Упрощенная логика - обычно размеры памяти и периферии совпадают + if (size_bits & 0x0200) return 4; // Word (32-bit) + if (size_bits & 0x0100) return 2; // HalfWord (16-bit) + return 1; // Byte (8-bit) + } + } +#endif + return 1; // По умолчанию 1 байт +} + + + + +__weak void DMA1_Stream0_IRQHandler(void) {} +__weak void DMA1_Stream1_IRQHandler(void) {} +__weak void DMA1_Stream2_IRQHandler(void) {} +__weak void DMA1_Stream3_IRQHandler(void) {} +__weak void DMA1_Stream4_IRQHandler(void) {} +__weak void DMA1_Stream5_IRQHandler(void) {} +__weak void DMA1_Stream6_IRQHandler(void) {} +__weak void DMA1_Stream7_IRQHandler(void) {} +__weak void DMA2_Stream0_IRQHandler(void) {} +__weak void DMA2_Stream1_IRQHandler(void) {} +__weak void DMA2_Stream2_IRQHandler(void) {} +__weak void DMA2_Stream3_IRQHandler(void) {} +__weak void DMA2_Stream4_IRQHandler(void) {} +__weak void DMA2_Stream5_IRQHandler(void) {} +__weak void DMA2_Stream6_IRQHandler(void) {} +__weak void DMA2_Stream7_IRQHandler(void) {} + +void DMA_Call_IRQHandller(DMA_TypeDef* DMAx, uint32_t stream) +{ + struct DMA_Stream_Sim* stream_sim = DMA_Get_Stream_Sim(DMAx, stream); + + if (stream_sim == NULL) return; + +#ifdef STM32F4 + // Определяем какой обработчик вызывать на основе DMAx и stream + if (DMAx == DMA1) { + switch (stream) { + case 0: DMA1_Stream0_IRQHandler(); break; + case 1: DMA1_Stream1_IRQHandler(); break; + case 2: DMA1_Stream2_IRQHandler(); break; + case 3: DMA1_Stream3_IRQHandler(); break; + case 4: DMA1_Stream4_IRQHandler(); break; + case 5: DMA1_Stream5_IRQHandler(); break; + case 6: DMA1_Stream6_IRQHandler(); break; + case 7: DMA1_Stream7_IRQHandler(); break; + } + } + else if (DMAx == DMA2) { + switch (stream) { + case 0: DMA2_Stream0_IRQHandler(); break; + case 1: DMA2_Stream1_IRQHandler(); break; + case 2: DMA2_Stream2_IRQHandler(); break; + case 3: DMA2_Stream3_IRQHandler(); break; + case 4: DMA2_Stream4_IRQHandler(); break; + case 5: DMA2_Stream5_IRQHandler(); break; + case 6: DMA2_Stream6_IRQHandler(); break; + case 7: DMA2_Stream7_IRQHandler(); break; + } + } +#elif defined(STM32F1) + if (DMAx == DMA1) { + switch (stream) { + case 0: DMA1_Channel0_IRQHandler(); break; + case 1: DMA1_Channel1_IRQHandler(); break; + case 2: DMA1_Channel2_IRQHandler(); break; + case 3: DMA1_Channel3_IRQHandler(); break; + case 4: DMA1_Channel4_IRQHandler(); break; + case 5: DMA1_Channel5_IRQHandler(); break; + case 6: DMA1_Channel6_IRQHandler(); break; + case 7: DMA1_Channel7_IRQHandler(); break; + } + } +#endif +} + +/////////////////////////////---DEINITIALIZATION---///////////////////////////// +void DMA_SIM_DEINIT(void) +{ +#ifdef USE_DMA1 + memset(&dma1_stream0s, 0, sizeof(dma1_stream0s)); + memset(&dma1_stream1s, 0, sizeof(dma1_stream1s)); + memset(&dma1_stream2s, 0, sizeof(dma1_stream2s)); + memset(&dma1_stream3s, 0, sizeof(dma1_stream3s)); + memset(&dma1_stream4s, 0, sizeof(dma1_stream4s)); + memset(&dma1_stream5s, 0, sizeof(dma1_stream5s)); + memset(&dma1_stream6s, 0, sizeof(dma1_stream6s)); + memset(&dma1_stream7s, 0, sizeof(dma1_stream7s)); +#endif + +#ifdef USE_DMA2 + memset(&dma2_stream0s, 0, sizeof(dma2_stream0s)); + memset(&dma2_stream1s, 0, sizeof(dma2_stream1s)); + memset(&dma2_stream2s, 0, sizeof(dma2_stream2s)); + memset(&dma2_stream3s, 0, sizeof(dma2_stream3s)); + memset(&dma2_stream4s, 0, sizeof(dma2_stream4s)); + memset(&dma2_stream5s, 0, sizeof(dma2_stream5s)); + memset(&dma2_stream6s, 0, sizeof(dma2_stream6s)); + memset(&dma2_stream7s, 0, sizeof(dma2_stream7s)); +#endif +} \ No newline at end of file diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.h b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.h new file mode 100644 index 0000000..e2e7aaa --- /dev/null +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_dma.h @@ -0,0 +1,40 @@ +#ifndef _MATLAB_DMA_H_ +#define _MATLAB_DMA_H_ + +#include "stm32_matlab_conf.h" + +#ifdef DMA1 +#define USE_DMA1 +#endif +#ifdef DMA2 +#define USE_DMA2 +#endif +/////////////////////////////---STRUCTURES---/////////////////////////// +struct DMA_Stream_Sim +{ + uint32_t* peripheral_address; + uint32_t* memory_address; + uint32_t buffer_size; + uint32_t current_index; + uint32_t data_size; + uint8_t circular_mode; + uint8_t transfer_complete; + uint8_t enabled; + uint8_t transfer_enabled; +}; +/////////////////////////////////////////////////////////////////////// + +///////////////////////////---FUNCTIONS---/////////////////////////// +void DMA_Sim_Transfer(DMA_TypeDef* DMAx, uint32_t stream); + + +struct DMA_Stream_Sim* DMA_Get_Stream_Sim(DMA_TypeDef* DMAx, uint32_t stream); +uint8_t DMA_Is_Stream_Enabled(DMA_TypeDef* DMAx, uint32_t stream); +uint32_t* DMA_Get_Peripheral_Address(DMA_TypeDef* DMAx, uint32_t stream); +uint32_t* DMA_Get_Memory_Address(DMA_TypeDef* DMAx, uint32_t stream); +uint32_t DMA_Get_Buffer_Size(DMA_TypeDef* DMAx, uint32_t stream); +uint8_t DMA_Get_Circular_Mode(DMA_TypeDef* DMAx, uint32_t stream); +uint32_t DMA_Get_DataSize(DMA_TypeDef* DMAx, uint32_t stream); +/////////////////////////////////////////////////////////////////////// + +#endif // _MATLAB_DMA_H_ \ No newline at end of file diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.c b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.c index c4c8dc6..5f24a07 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.c +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.c @@ -7,7 +7,7 @@ struct SlaveChannels Slave_Channels; // структура для связи и синхронизации таймеров - +void TIM_Call_IRQHandller(TIM_TypeDef* TIMx); //----------------------TIMER BASE FUNCTIONS-----------------------// /* Базовая функция для симуляции таймера: она вызывается каждый шаг симуляции */ @@ -24,6 +24,7 @@ switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting TIMx_Count(TIMx, TIMS); Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation + Write_TRGO(TIMx, TIMS); break; @@ -32,6 +33,7 @@ switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE Slave_Mode_Check_Source(TIMx, TIMS); TIMx_Count(TIMx, TIMS); Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation + Write_TRGO(TIMx, TIMS); break; } @@ -48,12 +50,14 @@ void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) /* Проверка на переполнение и дальнейшая его обработка */ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { + TIMS->Updated = 0; // Переполнение таймера: сброс таймера и вызов прерывания if ((TIMx->CR1 & TIM_CR1_UDIS) == 0) // UPDATE enable { if ((TIMx->CR1 & TIM_CR1_ARPE) == 0) TIMS->RELOAD = TIMx->ARR; // PRELOAD disable - update ARR every itteration if (TIMS->tx_cnt > TIMS->RELOAD || TIMS->tx_cnt < 0) // OVERFLOW { + TIMS->Updated = 1; TIMS->RELOAD = TIMx->ARR; // RELOAD ARR if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER @@ -61,7 +65,7 @@ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) else if (TIMS->tx_cnt < 0) TIMS->tx_cnt += TIMS->RELOAD+1; - call_IRQHandller(TIMx); // call HANDLER + TIM_Call_IRQHandller(TIMx); // call HANDLER } } } @@ -79,8 +83,6 @@ void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) CC_PWM_Ch4_Simulation(TIMx, TIMS); Write_OC_to_GPIO(TIMx, TIMS); - - Write_OC_to_TRGO(TIMx, TIMS); } //-----------------CAPTURE COPMARE & PWM FUNCTIONS------------------// /* Выбор режима CaptureCompare или PWM и симуляция для каждого канала */ @@ -323,26 +325,38 @@ void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) } } /* Запись результата compare в глабальную структуру с TRIGGER OUTPUT */ -void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) +void Write_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { // write trigger output from OCxREF pin if need unsigned temp_trgo; - if ((TIMx->CR2 & TIM_CR2_MMS) == (0b100 << TIM_CR2_MMS_Pos)) + if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC1REF)) { temp_trgo = TIMS->Channels.OC1REF; } - else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b101 << TIM_CR2_MMS_Pos)) + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC2REF)) { temp_trgo = TIMS->Channels.OC2REF; } - else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b110 << TIM_CR2_MMS_Pos)) + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC3REF)) { temp_trgo = TIMS->Channels.OC3REF; } - else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b111 << TIM_CR2_MMS_Pos)) + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_OC4REF)) { temp_trgo = TIMS->Channels.OC4REF; } + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_UPDATE)) + { + temp_trgo = TIMS->Updated; + } + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_ENABLE)) + { + temp_trgo = (TIMx->CR1 & TIM_CR1_CEN) ? 1: 0; + } + else if ((TIMx->CR2 & TIM_CR2_MMS) == (TIM_TRGO_RESET)) + { + temp_trgo = 0; + } // select TIMx TRGO @@ -585,7 +599,7 @@ void TIM_SIM_DEINIT(void) //#endif /* Вызов прерывания */ -void call_IRQHandller(TIM_TypeDef* TIMx) +void TIM_Call_IRQHandller(TIM_TypeDef* TIMx) { // calling HANDLER //if (TIMx == TIM1) // TIM1_UP_IRQHandler(); diff --git a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.h b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.h index 6a5478b..15572a8 100644 --- a/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.h +++ b/MATLAB/MCU_STM32_Matlab/Drivers/STM32_SIMULINK/stm32_matlab_tim.h @@ -42,7 +42,7 @@ struct SlaveChannels unsigned TIM8_TRGO : 1; }; - +extern struct SlaveChannels Slave_Channels; // структура для связи и синхронизации таймеров /* Структура для моделирования каналов таймера */ struct Channels_Sim { @@ -69,6 +69,7 @@ struct Channels_Sim /* Структура для моделирования таймера */ struct TIM_Sim { + int Updated; // счетчик таймера double tx_cnt; // счетчик таймера double tx_step; // шаг счета за один шаг симуляции int RELOAD; // буфер, если PRELOAD = 1 @@ -87,8 +88,6 @@ void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS); void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); /* Проверка на переполнение и дальнейшая его обработка */ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); -/* Вызов прерывания */ -void call_IRQHandller(TIM_TypeDef *TIMx); //-----------------------------------------------------------------// @@ -104,7 +103,7 @@ void CC_PWM_Ch4_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); /* Запись каналов таймера в порты GPIO */ void Write_OC_to_GPIO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); /* Запись результата compare в глабальную структуру с TRIGGER OUTPUT */ -void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); +void Write_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); //------------------------------------------------------------------// diff --git a/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.c b/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.c index 2973f9c..bd6379c 100644 --- a/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.c +++ b/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.c @@ -5,6 +5,7 @@ **************************************************************************/ #include "stm32_matlab_conf.h" #include "mcu_wrapper_conf.h" +#include "app_includes.h" MCU_MemoryTypeDef MCU_MEM; DBGMCU_TypeDef DEBUG_MCU; @@ -40,6 +41,17 @@ void deInitialize_MCU(void) // обнуление структур, симулирующих память МК memset(&MCU_MEM, 0, sizeof(MCU_MEM)); memset(&MCU_CORTEX_MEM, 0, sizeof(MCU_CORTEX_MEM)); + memset(&htim1, 0, sizeof(htim1)); + + + ClearStruct(htim1); + ClearStruct(htim3); + ClearStruct(htim8); + ClearStruct(htim11); + ClearStruct(htim12); + ClearStruct(htim13); + ClearStruct(hadc3); + ClearStruct(hdma_adc3); } /*------------------------------FUNCTIONS--------------------------------*/ @@ -164,9 +176,9 @@ void Init_TIM_SIM(void) tim5s.Channels.OC4_GPIOx = GPIOA; tim5s.Channels.OC4_PIN_SHIFT = 3; #endif -#ifdef USE_TIMx +#ifdef USE_TIM6 memset(&tim6s, 0, sizeof(tim6s)); - tim6s.tx_cnt = TIMx->CNT; + tim6s.tx_cnt = TIM6->CNT; tim6s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value; tim6s.Channels.OC1_GPIOx = GPIOA; @@ -178,6 +190,118 @@ void Init_TIM_SIM(void) tim6s.Channels.OC4_GPIOx = GPIOA; tim6s.Channels.OC4_PIN_SHIFT = 0; #endif +#ifdef USE_TIM7 + memset(&tim7s, 0, sizeof(tim7s)); + tim7s.tx_cnt = TIM7->CNT; + tim7s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value; + + tim7s.Channels.OC1_GPIOx = GPIOA; + tim7s.Channels.OC1_PIN_SHIFT = 0; + tim7s.Channels.OC2_GPIOx = GPIOA; + tim7s.Channels.OC2_PIN_SHIFT = 0; + tim7s.Channels.OC3_GPIOx = GPIOA; + tim7s.Channels.OC3_PIN_SHIFT = 0; + tim7s.Channels.OC4_GPIOx = GPIOA; + tim7s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM8 + memset(&tim8s, 0, sizeof(tim8s)); + tim8s.tx_cnt = TIM8->CNT; + tim8s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value; + + tim8s.Channels.OC1_GPIOx = GPIOA; + tim8s.Channels.OC1_PIN_SHIFT = 0; + tim8s.Channels.OC2_GPIOx = GPIOA; + tim8s.Channels.OC2_PIN_SHIFT = 0; + tim8s.Channels.OC3_GPIOx = GPIOA; + tim8s.Channels.OC3_PIN_SHIFT = 0; + tim8s.Channels.OC4_GPIOx = GPIOA; + tim8s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM9 + memset(&tim9s, 0, sizeof(tim9s)); + tim9s.tx_cnt = TIM9->CNT; + tim9s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value; + + tim9s.Channels.OC1_GPIOx = GPIOA; + tim9s.Channels.OC1_PIN_SHIFT = 0; + tim9s.Channels.OC2_GPIOx = GPIOA; + tim9s.Channels.OC2_PIN_SHIFT = 0; + tim9s.Channels.OC3_GPIOx = GPIOA; + tim9s.Channels.OC3_PIN_SHIFT = 0; + tim9s.Channels.OC4_GPIOx = GPIOA; + tim9s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM10 + memset(&tim10s, 0, sizeof(tim10s)); + tim10s.tx_cnt = TIM10->CNT; + tim10s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value; + + tim10s.Channels.OC1_GPIOx = GPIOA; + tim10s.Channels.OC1_PIN_SHIFT = 0; + tim10s.Channels.OC2_GPIOx = GPIOA; + tim10s.Channels.OC2_PIN_SHIFT = 0; + tim10s.Channels.OC3_GPIOx = GPIOA; + tim10s.Channels.OC3_PIN_SHIFT = 0; + tim10s.Channels.OC4_GPIOx = GPIOA; + tim10s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM11 + memset(&tim11s, 0, sizeof(tim11s)); + tim11s.tx_cnt = TIM11->CNT; + tim11s.tx_step = hmcu.sSimSampleTime * ABP2_TIMS_Value; + + tim11s.Channels.OC1_GPIOx = GPIOA; + tim11s.Channels.OC1_PIN_SHIFT = 0; + tim11s.Channels.OC2_GPIOx = GPIOA; + tim11s.Channels.OC2_PIN_SHIFT = 0; + tim11s.Channels.OC3_GPIOx = GPIOA; + tim11s.Channels.OC3_PIN_SHIFT = 0; + tim11s.Channels.OC4_GPIOx = GPIOA; + tim11s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM12 + memset(&tim12s, 0, sizeof(tim12s)); + tim12s.tx_cnt = TIM12->CNT; + tim12s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value; + + tim12s.Channels.OC1_GPIOx = GPIOA; + tim12s.Channels.OC1_PIN_SHIFT = 0; + tim12s.Channels.OC2_GPIOx = GPIOA; + tim12s.Channels.OC2_PIN_SHIFT = 0; + tim12s.Channels.OC3_GPIOx = GPIOA; + tim12s.Channels.OC3_PIN_SHIFT = 0; + tim12s.Channels.OC4_GPIOx = GPIOA; + tim12s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM13 + memset(&tim13s, 0, sizeof(tim13s)); + tim13s.tx_cnt = TIM13->CNT; + tim13s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value; + + tim13s.Channels.OC1_GPIOx = GPIOA; + tim13s.Channels.OC1_PIN_SHIFT = 0; + tim13s.Channels.OC2_GPIOx = GPIOA; + tim13s.Channels.OC2_PIN_SHIFT = 0; + tim13s.Channels.OC3_GPIOx = GPIOA; + tim13s.Channels.OC3_PIN_SHIFT = 0; + tim13s.Channels.OC4_GPIOx = GPIOA; + tim13s.Channels.OC4_PIN_SHIFT = 0; +#endif +#ifdef USE_TIM14 + memset(&tim14s, 0, sizeof(tim14s)); + tim14s.tx_cnt = TIM14->CNT; + tim14s.tx_step = hmcu.sSimSampleTime * ABP1_TIMS_Value; + + tim14s.Channels.OC1_GPIOx = GPIOA; + tim14s.Channels.OC1_PIN_SHIFT = 0; + tim14s.Channels.OC2_GPIOx = GPIOA; + tim14s.Channels.OC2_PIN_SHIFT = 0; + tim14s.Channels.OC3_GPIOx = GPIOA; + tim14s.Channels.OC3_PIN_SHIFT = 0; + tim14s.Channels.OC4_GPIOx = GPIOA; + tim14s.Channels.OC4_PIN_SHIFT = 0; +#endif } /*-------------------------------TIMERS----------------------------------*/ //-----------------------------------------------------------------------// diff --git a/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.h b/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.h index 8b353e6..34e81e8 100644 --- a/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.h +++ b/MATLAB/MCU_STM32_Matlab/stm32_matlab_conf.h @@ -60,16 +60,15 @@ void Initialize_Periph_Sim(void); #include "stm32_matlab_rcc.h" #include "stm32_matlab_gpio.h" +#include "stm32_matlab_dma.h" //-----------------------------------------------------------------------// /*-------------------------------TIMERS----------------------------------*/ -//#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \ -// defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \ -// defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14) -#include "stm32_matlab_tim.h" - -// CODE void Init_TIM_SIM(void); +#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \ + defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \ + defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14) +#include "stm32_matlab_tim.h" #ifdef USE_TIM1 extern struct TIM_Sim tim1s; @@ -113,13 +112,22 @@ extern struct TIM_Sim tim13s; #ifdef USE_TIM14 extern struct TIM_Sim tim14s; #endif +#endif + +#ifndef TIM_ENABLE +static void Simulate_TIMs() {} +static void TIM_SIM_DEINIT() {} +#endif /*-------------------------------TIMERS----------------------------------*/ //-----------------------------------------------------------------------// //-----------------------------------------------------------------------// /*---------------------------------ADC-----------------------------------*/ +void Init_ADC_SIM(void); +#if defined(USE_ADC1) || defined(USE_ADC2) || defined(USE_ADC3) #include "stm32_matlab_adc.h" + #ifdef USE_ADC1 extern struct ADC_Sim adc1s; #endif @@ -129,7 +137,12 @@ extern struct ADC_Sim adc2s; #ifdef USE_ADC3 extern struct ADC_Sim adc3s; #endif +#endif +#ifndef ADC_ENABLE +static void Simulate_ADCs() {} +static void ADC_SIM_DEINIT() {} +#endif /*---------------------------------ADC-----------------------------------*/ //-----------------------------------------------------------------------// diff --git a/MATLAB/MCU_STM32_Matlab/stm32f4xx_matlab_conf.json b/MATLAB/MCU_STM32_Matlab/stm32f4xx_matlab_conf.json index 3c36e56..596d63e 100644 --- a/MATLAB/MCU_STM32_Matlab/stm32f4xx_matlab_conf.json +++ b/MATLAB/MCU_STM32_Matlab/stm32f4xx_matlab_conf.json @@ -27,6 +27,7 @@ "Sources": [ "stm32_matlab_conf.c", "Drivers/STM32_SIMULINK/stm32_matlab_gpio.c", + "Drivers/STM32_SIMULINK/stm32_matlab_dma.c", "Drivers/STM32_SIMULINK/stm32_periph_registers.c" ], "Defines": { @@ -48,14 +49,16 @@ }, "Tab_TIM_Enable": { "Prompt": "Enable TIMs", + "Def": "TIM_ENABLE", "Type": "checkbox", "Default": true, "NewRow": true }, "Tab_ADC_Enable": { "Prompt": "Enable ADCs", + "Def": "ADC_ENABLE", "Type": "checkbox", - "Default": true, + "Default": false, "NewRow": true } } @@ -69,7 +72,7 @@ "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c" ], "Type": "checkbox", - "Default": true, + "Default": false, "NewRow": true }, "HAL_ADC": { @@ -499,7 +502,7 @@ "Prompt": "TIM8 Enable", "Def": "USE_TIM8", "Type": "checkbox", - "Default": false, + "Default": true, "NewRow": true }, "TIM6_Handler": { @@ -590,7 +593,7 @@ "Prompt": "ADC1 Enable", "Def": "USE_ADC1", "Type": "checkbox", - "Default": true, + "Default": false, "NewRow": true }, "ADC2_Enable": { @@ -604,7 +607,7 @@ "Prompt": "ADC3 Enable", "Def": "USE_ADC3", "Type": "checkbox", - "Default": false, + "Default": true, "NewRow": true }, "Sample_Rate": { diff --git a/MATLAB/MCU_Wrapper/mcu_wrapper_conf.h b/MATLAB/MCU_Wrapper/mcu_wrapper_conf.h index fa2864b..93edc3f 100644 --- a/MATLAB/MCU_Wrapper/mcu_wrapper_conf.h +++ b/MATLAB/MCU_Wrapper/mcu_wrapper_conf.h @@ -55,7 +55,7 @@ #define OUT_PORT_NUMB 2 #define THYR_PORT_1_WIDTH 6 -#define OUT_PORT_2_WIDTH 1 +#define OUT_PORT_2_WIDTH 6 // INPUT/OUTPUTS PARAMS END /** WRAPPER_CONF diff --git a/MATLAB/MCU_Wrapper/run_mex.bat b/MATLAB/MCU_Wrapper/run_mex.bat new file mode 100644 index 0000000..8d7bb2c --- /dev/null +++ b/MATLAB/MCU_Wrapper/run_mex.bat @@ -0,0 +1,156 @@ +@echo off +:: Получаем аргументы из командной строки +:: %1 - includes_USER +:: %2 - code_USER +:: %3 - режим (например, debug) + +:: Аргументы: +:: %1 — includes строка (в кавычках) +:: %2 — sources строка +:: %3 — defines строка +:: %4 — режим компиляции (debug/release) + +:: Сохраняем как переменные +set filename=%~1 +set includes_USER=%~2 +set code_USER=%~3 +set defines_USER=%~4 +set defines_CONFIG=%~5 +set compil_mode=%~6 + +:: Заменяем __EQ__ на = +set defines_USER=%defines_USER:__EQ__==% +set defines_CONFIG=%defines_CONFIG:__EQ__==% + + +set defines_WRAPPER=-D"MATLAB"^ -D"__sizeof_ptr=8" +:: -------------------------USERS PATHS AND CODE--------------------------- +::------------------------------------------------------------------------- + + +:: -------------------------WRAPPER PATHS AND CODE--------------------------- +:: оболочка, которая будет моделировать работу МК в симулинке +:: WRAPPER BAT START +set code_WRAPPER=.\MCU_Wrapper\MCU.c^ + .\MCU_Wrapper\mcu_wrapper.c + +set includes_WRAPPER= -I".\MCU_Wrapper\" +:: WRAPPER BAT END + +:: APP WRAPPER BAT START +set code_APP_WRAPPER=.\app_wrapper\app_wrapper.c^ + .\app_wrapper\app_init.c^ + .\app_wrapper\app_io.c + +set includes_APP_WRAPPER= -I".\app_wrapper\" +:: APP WRAPPER BAT END + +set includes_WRAPPER= %includes_WRAPPER% %includes_APP_WRAPPER% +set code_WRAPPER= %code_WRAPPER% %code_APP_WRAPPER% + + +:: PERIPH BAT START +set code_PERIPH=.\MCU_STM32_Matlab\stm32_matlab_conf.c^ + .\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_gpio.c^ + .\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_dma.c^ + .\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_periph_registers.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c^ + .\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c^ + .\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_tim.c^ + .\MCU_STM32_Matlab\Drivers\STM32_SIMULINK\stm32_matlab_adc.c + +set includes_PERIPH=-I".\MCU_STM32_Matlab\."^ + -I".\MCU_STM32_Matlab\Drivers\STM32_SIMULINK"^ + -I".\MCU_STM32_Matlab\Drivers\CMSIS"^ + -I".\MCU_STM32_Matlab\Drivers\CMSIS\Device\STM32F4xx"^ + -I".\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc"^ + -I".\MCU_STM32_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy" +:: PERIPH BAT END +::------------------------------------------------------------------------- + + +:: ---------------------SET PARAMS FOR MEX COMPILING----------------------- +:: -------------ALL------------ +set includes= %includes_WRAPPER% %includes_PERIPH% %includes_USER% +set codes= %code_USER% %code_WRAPPER% %code_PERIPH% +set defines= %defines_WRAPPER% %defines_CONFIG% %defines_USER% +:: -------OUTPUT FOLDER-------- +set output= -outdir "." -output %filename% + +:: если нужен дебаг, до запускаем run_mex с припиской debug +IF %compil_mode%==debug (set debug= -g) +::------------------------------------------------------------------------- + + +::------START COMPILING------- +if "%7"=="echo_enable" ( + echo Compiling... + + echo =========================== + echo =========INCLUDES========== + echo USER: + for %%f in (%includes_USER%) do ( + echo %%f + ) + echo INTERNAL: + for %%f in (%includes_WRAPPER%) do ( + echo %%f + ) + echo PERIPH: + for %%f in (%includes_PERIPH%) do ( + echo %%f + ) + + echo =========================== + echo ==========SOURCES========== + echo USER: + for %%f in (%code_USER%) do ( + echo %%f + ) + echo INTERNAL: + for %%f in (%code_WRAPPER%) do ( + echo %%f + ) + echo PERIPH: + for %%f in (%code_PERIPH%) do ( + echo %%f + ) + + echo =========================== + echo ==========DEFINES========== + echo USER: + for %%d in (%defines_USER%) do ( + echo %%d + ) + echo CONFIG: + for %%f in (%defines_CONFIG%) do ( + echo %%f + ) + echo INTERNAL: + for %%f in (%defines_WRAPPER%) do ( + echo %%f + ) +) +echo =========================== +echo MODE: %compil_mode% +echo =========================== +:: 1. ПРЕЖДЕ ЧЕМ КОМПИЛИРОВАТЬ - ВЫГРУЗИТЬ СТАРЫЙ ФАЙЛ + +:: 2. Компиляция с флагами для MSVC +:: set LINK_EMBEDDED=/BASE:0x10000000 /FIXED:NO /FILEALIGN:0x1000 /FORCE:MULTIPLE /DYNAMICBASE:NO +set C_EMBEDDED="-w" +mex %output% %defines% %includes% %codes% %debug% CFLAGS="$CFLAGS %C_EMBEDDED%" LINKFLAGS="$LINKFLAGS %LINK_EMBEDDED%" +echo %DATE% %TIME% + +exit /b %ERRORLEVEL% \ No newline at end of file diff --git a/MATLAB/app_wrapper/app_includes.h b/MATLAB/app_wrapper/app_includes.h index 1c5648d..fed3040 100644 --- a/MATLAB/app_wrapper/app_includes.h +++ b/MATLAB/app_wrapper/app_includes.h @@ -10,10 +10,11 @@ // INCLUDES START // Инклюды для доступа к коду МК в коде оболочке -//#include "stm32_matlab_conf.h" #include "main.h" #include "tim.h" #include "adc.h" +#include "upp_main.h" +#include "adc_tools.h" // INCLUDES END #endif //_APP_INCLUDES_H_ \ No newline at end of file diff --git a/MATLAB/app_wrapper/app_init.c b/MATLAB/app_wrapper/app_init.c index 515a489..854cc3a 100644 --- a/MATLAB/app_wrapper/app_init.c +++ b/MATLAB/app_wrapper/app_init.c @@ -17,12 +17,14 @@ void app_init(void) { // Вызов разных функций в случае, // если не используется отдельный поток для main(). HAL_Init(); + MX_DMA_Init(); MX_TIM1_Init(); MX_TIM3_Init(); - __HAL_TIM_SET_COMPARE(&hpwm1, PWM_CHANNEL_1, __HAL_TIM_GET_AUTORELOAD(&hpwm1)/2); - HAL_TIM_PWM_Start(&hpwm1, PWM_CHANNEL_1); - MX_ADC1_Init(); - HAL_ADC_Start(&hadc1); + MX_TIM8_Init(); + MX_ADC3_Init(); + UPP_Init(); + UPP_PreWhile(); + // USER APP INIT END } diff --git a/MATLAB/app_wrapper/app_io.c b/MATLAB/app_wrapper/app_io.c index 46f50ea..bbd7a47 100644 --- a/MATLAB/app_wrapper/app_io.c +++ b/MATLAB/app_wrapper/app_io.c @@ -32,7 +32,12 @@ void ThyristorWrite(real_T* Buffer) */ void app_readInputs(const real_T* Buffer) { // USER APP INPUT START -ADC_Set_Channel_Value(ADC1, 0, ReadInputArray(1,0)); +ADC_Set_Channel_Value(ADC3, 4, ReadInputArray(0,0)); +ADC_Set_Channel_Value(ADC3, 5, ReadInputArray(0,1)); +ADC_Set_Channel_Value(ADC3, 6, ReadInputArray(0,2)); +ADC_Set_Channel_Value(ADC3, 7, ReadInputArray(0,3)); +ADC_Set_Channel_Value(ADC3, 8, ReadInputArray(0,4)); +ADC_Set_Channel_Value(ADC3, 10, ReadInputArray(0,5)); // USER APP INPUT END } @@ -44,6 +49,10 @@ ADC_Set_Channel_Value(ADC1, 0, ReadInputArray(1,0)); void app_writeOutputBuffer(real_T* Buffer) { // USER APP OUTPUT START ThyristorWrite(Buffer); - WriteOutputArray(ADC1->DR, 1, 0); + extern ADC_Period_t adc; + for(int i = 0; i < 6; i++) + { + WriteOutputArray(adc.Data[i], 1, i); + } // USER APP OUTPUT END } \ No newline at end of file diff --git a/MATLAB/upp_r2023.slx b/MATLAB/upp_r2023.slx index d991585..1ebf0c0 100644 Binary files a/MATLAB/upp_r2023.slx and b/MATLAB/upp_r2023.slx differ diff --git a/UPP/.mxproject b/UPP/.mxproject index 6a3e639..76a640e 100644 --- a/UPP/.mxproject +++ b/UPP/.mxproject @@ -2,40 +2,42 @@ LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f427xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\adc.c;..\Core\Src\can.c;..\Core\Src\iwdg.c;..\Core\Src\rtc.c;..\Core\Src\spi.c;..\Core\Src\tim.c;..\Core\Src\usart.c;..\Core\Src\stm32f4xx_it.c;..\Core\Src\stm32f4xx_hal_msp.c;..\Core\Src\stm32f4xx_hal_timebase_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;;; +SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\adc.c;..\Core\Src\can.c;..\Core\Src\dma.c;..\Core\Src\iwdg.c;..\Core\Src\rtc.c;..\Core\Src\spi.c;..\Core\Src\tim.c;..\Core\Src\usart.c;..\Core\Src\stm32f4xx_it.c;..\Core\Src\stm32f4xx_hal_msp.c;..\Core\Src\stm32f4xx_hal_timebase_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;;; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; CDefines=USE_HAL_DRIVER;STM32F427xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=11 +HeaderFileListSize=12 HeaderFiles#0=..\Core\Inc\gpio.h HeaderFiles#1=..\Core\Inc\adc.h HeaderFiles#2=..\Core\Inc\can.h -HeaderFiles#3=..\Core\Inc\iwdg.h -HeaderFiles#4=..\Core\Inc\rtc.h -HeaderFiles#5=..\Core\Inc\spi.h -HeaderFiles#6=..\Core\Inc\tim.h -HeaderFiles#7=..\Core\Inc\usart.h -HeaderFiles#8=..\Core\Inc\stm32f4xx_it.h -HeaderFiles#9=..\Core\Inc\stm32f4xx_hal_conf.h -HeaderFiles#10=..\Core\Inc\main.h +HeaderFiles#3=..\Core\Inc\dma.h +HeaderFiles#4=..\Core\Inc\iwdg.h +HeaderFiles#5=..\Core\Inc\rtc.h +HeaderFiles#6=..\Core\Inc\spi.h +HeaderFiles#7=..\Core\Inc\tim.h +HeaderFiles#8=..\Core\Inc\usart.h +HeaderFiles#9=..\Core\Inc\stm32f4xx_it.h +HeaderFiles#10=..\Core\Inc\stm32f4xx_hal_conf.h +HeaderFiles#11=..\Core\Inc\main.h HeaderFolderListSize=1 HeaderPath#0=..\Core\Inc HeaderFiles=; -SourceFileListSize=12 +SourceFileListSize=13 SourceFiles#0=..\Core\Src\gpio.c SourceFiles#1=..\Core\Src\adc.c SourceFiles#2=..\Core\Src\can.c -SourceFiles#3=..\Core\Src\iwdg.c -SourceFiles#4=..\Core\Src\rtc.c -SourceFiles#5=..\Core\Src\spi.c -SourceFiles#6=..\Core\Src\tim.c -SourceFiles#7=..\Core\Src\usart.c -SourceFiles#8=..\Core\Src\stm32f4xx_it.c -SourceFiles#9=..\Core\Src\stm32f4xx_hal_msp.c -SourceFiles#10=..\Core\Src\stm32f4xx_hal_timebase_tim.c -SourceFiles#11=..\Core\Src\main.c +SourceFiles#3=..\Core\Src\dma.c +SourceFiles#4=..\Core\Src\iwdg.c +SourceFiles#5=..\Core\Src\rtc.c +SourceFiles#6=..\Core\Src\spi.c +SourceFiles#7=..\Core\Src\tim.c +SourceFiles#8=..\Core\Src\usart.c +SourceFiles#9=..\Core\Src\stm32f4xx_it.c +SourceFiles#10=..\Core\Src\stm32f4xx_hal_msp.c +SourceFiles#11=..\Core\Src\stm32f4xx_hal_timebase_tim.c +SourceFiles#12=..\Core\Src\main.c SourceFolderListSize=1 SourcePath#0=..\Core\Src SourceFiles=; diff --git a/UPP/AllLibs/MyLibs b/UPP/AllLibs/MyLibs index eff6470..60629aa 160000 --- a/UPP/AllLibs/MyLibs +++ b/UPP/AllLibs/MyLibs @@ -1 +1 @@ -Subproject commit eff64709bccb8f8fa7297f4042f4ebb7c71a5a21 +Subproject commit 60629aaa3bb3a068cbfe5a93f43f676bd154e85b diff --git a/UPP/Core/Inc/adc.h b/UPP/Core/Inc/adc.h index 34c0965..208562f 100644 --- a/UPP/Core/Inc/adc.h +++ b/UPP/Core/Inc/adc.h @@ -32,15 +32,12 @@ extern "C" { /* USER CODE END Includes */ -extern ADC_HandleTypeDef hadc1; - extern ADC_HandleTypeDef hadc3; /* USER CODE BEGIN Private defines */ - +extern DMA_HandleTypeDef hdma_adc3; /* USER CODE END Private defines */ -void MX_ADC1_Init(void); void MX_ADC3_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/UPP/Core/Inc/dma.h b/UPP/Core/Inc/dma.h new file mode 100644 index 0000000..493d98e --- /dev/null +++ b/UPP/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/UPP/Core/Inc/main.h b/UPP/Core/Inc/main.h index 72e8f7e..a705fae 100644 --- a/UPP/Core/Inc/main.h +++ b/UPP/Core/Inc/main.h @@ -75,6 +75,7 @@ void Error_Handler(void); #define PWM_CHANNEL_4 TIM_CHANNEL_4 #define PWM_CHANNEL_5 TIM_CHANNEL_3 #define PWM_CHANNEL_6 TIM_CHANNEL_4 +#define adc_tim htim8 #define UM_LED_GREEN2_Pin GPIO_PIN_2 #define UM_LED_GREEN2_GPIO_Port GPIOE #define CEN_O_Pin GPIO_PIN_3 diff --git a/UPP/Core/Inc/stm32f4xx_it.h b/UPP/Core/Inc/stm32f4xx_it.h index f706d99..52044da 100644 --- a/UPP/Core/Inc/stm32f4xx_it.h +++ b/UPP/Core/Inc/stm32f4xx_it.h @@ -56,6 +56,7 @@ void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void TIM8_TRG_COM_TIM14_IRQHandler(void); +void DMA2_Stream0_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/UPP/Core/Inc/tim.h b/UPP/Core/Inc/tim.h index 48522b1..2dfa292 100644 --- a/UPP/Core/Inc/tim.h +++ b/UPP/Core/Inc/tim.h @@ -36,6 +36,8 @@ extern TIM_HandleTypeDef htim1; extern TIM_HandleTypeDef htim3; +extern TIM_HandleTypeDef htim8; + extern TIM_HandleTypeDef htim11; extern TIM_HandleTypeDef htim12; @@ -48,6 +50,7 @@ extern TIM_HandleTypeDef htim13; void MX_TIM1_Init(void); void MX_TIM3_Init(void); +void MX_TIM8_Init(void); void MX_TIM11_Init(void); void MX_TIM12_Init(void); void MX_TIM13_Init(void); diff --git a/UPP/Core/PowerMonitor/adc_tools.c b/UPP/Core/PowerMonitor/adc_tools.c new file mode 100644 index 0000000..a5ad350 --- /dev/null +++ b/UPP/Core/PowerMonitor/adc_tools.c @@ -0,0 +1,130 @@ +/** +****************************************************************************** +* @file adc_tools.c +* @brief Функции доступа к данным Modbus +****************************************************************************** +* @details +******************************************************************************/ +#include "adc_tools.h" + + +// Проверка корректности структуры АЦП +#define assert_adc(_adc_) check_null_ptr_2(_adc_, (_adc_)->f.Initialized) + + +/** + * @brief Инициализация периодического АЦП. + * @param adc Указатель на кастомный хендл АЦП + * @param htim Указатель на HAL хендл таймера + * @param hadc Указатель на HAL хендл АЦП + * @return HAL Status. + */ +HAL_StatusTypeDef ADC_Init(ADC_Period_t *adc, TIM_HandleTypeDef *htim, ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef res; + if(check_null_ptr_2(htim, hadc)) + return HAL_ERROR; + + adc->htim = htim; + adc->hadc = hadc; + + adc->f.AdcRunning = 0; + adc->f.DataReady = 0; + adc->f.Initialized = 1; + return HAL_OK; +} + +/** + * @brief Конфигуарция канала АЦП. + * @param adc Указатель на кастомный хендл АЦП + * @param ChNumb Номер канала для конфигурации + * @param levelZero Нулевой уровень (в квантах АЦП) + * @param valueMax Максимальный уровень Единиц Измерения (в Вольтах/Амперах/Градусах) + * @param levelMax Максимальный уровень АЦП (в квантах АЦП) + * @return HAL Status. + */ +HAL_StatusTypeDef ADC_ConfigChannel(ADC_Period_t *adc, int ChNumb, uint16_t levelZero, float valueMax, uint16_t levelMax) +{ + HAL_StatusTypeDef res; + if(assert_adc(adc)) + return HAL_ERROR; + if((valueMax == 0) || (levelMax == 0)) + return HAL_ERROR; + + adc->Coefs[ChNumb].lMax = levelMax; + adc->Coefs[ChNumb].vMax = valueMax; + adc->Coefs[ChNumb].lZero = levelZero; + return HAL_OK; +} + +/** + * @brief Запуск АЦП. + * @param adc Указатель на кастомный хендл АЦП + * @param Period Период таймера с какой частотой будет работать АЦП + * @return HAL Status. + * @details Запускает АЦП с частотой дискретизации на которую настроен таймер adc_tim. + */ +HAL_StatusTypeDef ADC_Start(ADC_Period_t *adc, uint16_t Period) +{ + HAL_StatusTypeDef res; + if(assert_adc(adc)) + return HAL_ERROR; + if(Period == 0) + return HAL_ERROR; + + // Запускаем таймер который будет запускать опрос АЦП с заданным периодом + __HAL_TIM_SET_AUTORELOAD(adc->htim, Period); + res = HAL_TIM_Base_Start(adc->htim); + if(res != HAL_OK) + { + return res; + } + // Запускаем АЦП который будет перекидывать данные в ADC_DMA_Buffer + res = HAL_ADC_Start_DMA(adc->hadc, (uint32_t*)adc->RawData, 6); // Затем АЦП с DMA + if(res != HAL_OK) + { + return res; + } + + return res; +} +/** + * @brief Остановка АЦП . + * @param adc Указатель на кастомный хендл АЦП + * @return HAL Status. + * @details По факту остановка таймера, который запускает АЦП. Сам АЦП продолжает работу. + */ +HAL_StatusTypeDef ADC_Stop(ADC_Period_t *adc) +{ + if(assert_adc(adc)) + return HAL_ERROR; + + // Запускаем таймер который будет запускать опрос АЦП + return HAL_TIM_Base_Stop(adc->htim); +} + + +/** + * @brief Остановка АЦП . + * @return HAL Status. + * @details По факту остановка таймера, который запускает АЦП. Сам АЦП продолжает работу. + * @note Вызывается в . + */ +HAL_StatusTypeDef ADC_Handle(ADC_Period_t *adc) +{ + if(assert_adc(adc)) + return HAL_ERROR; + + ADC_Coefs_t *coefs = adc->Coefs; + uint16_t *raw = adc->RawData; + float *data = adc->Data; + + for(int i = 0; i < ADC_NUMB_OF_CHANNELS; i++) + { + ADC_Coefs_t *coefs = &adc->Coefs[i]; + data[i] = ((float)(raw[i])-coefs->lZero) * coefs->vMax / (coefs->lMax-coefs->lZero); + } + adc->f.DataReady = 1; + + return HAL_OK; +} \ No newline at end of file diff --git a/UPP/Core/PowerMonitor/adc_tools.h b/UPP/Core/PowerMonitor/adc_tools.h new file mode 100644 index 0000000..a5923a3 --- /dev/null +++ b/UPP/Core/PowerMonitor/adc_tools.h @@ -0,0 +1,62 @@ +/** +****************************************************************************** +* @file adc_tools.h +* @brief Определения структур данных Modbus устройства +****************************************************************************** +* @details +******************************************************************************/ + +#ifndef _ADC_TOOLS_H_ +#define _ADC_TOOLS_H_ +#include "main.h" + +#define ADC_NUMB_OF_CHANNELS 6 + +/** + * @brief Коэфициенты канала АЦП для пересчета в единицы измерения + */ +typedef struct +{ + uint16_t lZero; ///< Нулевой уровень (в квантах АЦП) + float vMax; ///< Максимальный уровень Единиц Измерения (в Вольтах/Амперах/Градусах) + uint16_t lMax; ///< Максимальный уровень АЦП (в квантах АЦП) +}ADC_Coefs_t; + +/** + * @brief Хендл АЦП + */ +typedef struct +{ + // Handles + TIM_HandleTypeDef *htim; ///< Хендл таймера, который запускает АЦП + ADC_HandleTypeDef *hadc; ///< Хендл АЦП + + // Data and calculation + uint16_t RawData[ADC_NUMB_OF_CHANNELS]; ///< Сырые значения АЦП + ADC_Coefs_t Coefs[ADC_NUMB_OF_CHANNELS]; ///< Коэффициенты @ref ADC_Coefs_t + float Data[ADC_NUMB_OF_CHANNELS]; ///< Пересчитанные значения АЦП (в Вольтах/Амперах/Градусах) + + struct + { + unsigned Initialized:1; + unsigned AdcRunning:1; + unsigned DataReady:1; + }f; +}ADC_Period_t; + + + +/* Инициализация периодического АЦП */ +HAL_StatusTypeDef ADC_Init(ADC_Period_t *adc, TIM_HandleTypeDef *htim, ADC_HandleTypeDef *hadc); +/* Конфигуарция канала АЦП. */ +HAL_StatusTypeDef ADC_ConfigChannel(ADC_Period_t *adc, int ChNumb, uint16_t levelZero, float valueMax, uint16_t levelMax); +/* Запуск АЦП. */ +HAL_StatusTypeDef ADC_Start(ADC_Period_t *adc, uint16_t Period); +/* Остановка АЦП. */ +HAL_StatusTypeDef ADC_Stop(ADC_Period_t *adc); + +/* Остановка АЦП . */ +HAL_StatusTypeDef ADC_Handle(ADC_Period_t *adc); + + +#endif //_ADC_TOOLS_H_ diff --git a/UPP/Core/Src/adc.c b/UPP/Core/Src/adc.c index 87bdb83..603f877 100644 --- a/UPP/Core/Src/adc.c +++ b/UPP/Core/Src/adc.c @@ -21,59 +21,12 @@ #include "adc.h" /* USER CODE BEGIN 0 */ - +#include "tim.h" /* USER CODE END 0 */ -ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc3; +DMA_HandleTypeDef hdma_adc3; -/* ADC1 init function */ -void MX_ADC1_Init(void) -{ - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) - */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.ScanConvMode = DISABLE; - hadc1.Init.ContinuousConvMode = ENABLE; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - if (HAL_ADC_Init(&hadc1) != HAL_OK) - { - Error_Handler(); - } - - /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. - */ - sConfig.Channel = ADC_CHANNEL_0; - sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} /* ADC3 init function */ void MX_ADC3_Init(void) { @@ -93,15 +46,15 @@ void MX_ADC3_Init(void) hadc3.Instance = ADC3; hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc3.Init.Resolution = ADC_RESOLUTION_12B; - hadc3.Init.ScanConvMode = DISABLE; + hadc3.Init.ScanConvMode = ENABLE; hadc3.Init.ContinuousConvMode = DISABLE; hadc3.Init.DiscontinuousConvMode = DISABLE; - hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO; hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc3.Init.NbrOfConversion = 1; + hadc3.Init.NbrOfConversion = 6; hadc3.Init.DMAContinuousRequests = DISABLE; - hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; if (HAL_ADC_Init(&hadc3) != HAL_OK) { Error_Handler(); @@ -109,13 +62,58 @@ void MX_ADC3_Init(void) /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ - sConfig.Channel = ADC_CHANNEL_7; + sConfig.Channel = ADC_CHANNEL_4; sConfig.Rank = 1; sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) { Error_Handler(); } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = 2; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_6; + sConfig.Rank = 3; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_7; + sConfig.Rank = 4; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_8; + sConfig.Rank = 5; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_10; + sConfig.Rank = 6; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } /* USER CODE BEGIN ADC3_Init 2 */ /* USER CODE END ADC3_Init 2 */ @@ -126,28 +124,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(adcHandle->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* ADC1 clock enable */ - __HAL_RCC_ADC1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA0/WKUP ------> ADC1_IN0 - */ - GPIO_InitStruct.Pin = GPIO_PIN_0; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } - else if(adcHandle->Instance==ADC3) + if(adcHandle->Instance==ADC3) { /* USER CODE BEGIN ADC3_MspInit 0 */ @@ -176,6 +153,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(AI_Temp2_GPIO_Port, &GPIO_InitStruct); + /* ADC3 DMA Init */ + /* ADC3 Init */ + hdma_adc3.Instance = DMA2_Stream0; + hdma_adc3.Init.Channel = DMA_CHANNEL_2; + hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc3.Init.Mode = DMA_NORMAL; + hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; + hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc3); + /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ @@ -185,24 +181,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) { - if(adcHandle->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA0/WKUP ------> ADC1_IN0 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); - - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - else if(adcHandle->Instance==ADC3) + if(adcHandle->Instance==ADC3) { /* USER CODE BEGIN ADC3_MspDeInit 0 */ @@ -223,6 +202,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) HAL_GPIO_DeInit(AI_Temp2_GPIO_Port, AI_Temp2_Pin); + /* ADC3 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC3_MspDeInit 1 */ /* USER CODE END ADC3_MspDeInit 1 */ diff --git a/UPP/Core/Src/dma.c b/UPP/Core/Src/dma.c new file mode 100644 index 0000000..3f5fab8 --- /dev/null +++ b/UPP/Core/Src/dma.c @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA2_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/UPP/Core/Src/main.c b/UPP/Core/Src/main.c index ec5e420..0e2747f 100644 --- a/UPP/Core/Src/main.c +++ b/UPP/Core/Src/main.c @@ -20,6 +20,7 @@ #include "main.h" #include "adc.h" #include "can.h" +#include "dma.h" #include "iwdg.h" #include "rtc.h" #include "spi.h" @@ -28,7 +29,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ - +#include "upp_main.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -92,6 +93,7 @@ int main(void) /* USER CODE END SysInit */ /* Initialize all configured peripherals */ + MX_DMA_Init(); MX_ADC3_Init(); MX_USART3_UART_Init(); MX_CAN1_Init(); @@ -104,26 +106,23 @@ int main(void) MX_SPI3_Init(); MX_TIM11_Init(); MX_TIM12_Init(); - MX_ADC1_Init(); + MX_TIM8_Init(); /* USER CODE BEGIN 2 */ -#else - MX_TIM1_Init(); - MX_TIM3_Init(); -#endif - __HAL_TIM_SET_COMPARE(&hpwm1, PWM_CHANNEL_1, __HAL_TIM_GET_AUTORELOAD(&hpwm1)/2); - HAL_TIM_PWM_Start(&hpwm1, PWM_CHANNEL_1); +#else //MATLAB +#endif //MATLAB + UPP_Init(); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ + UPP_PreWhile(); while (1) { + UPP_While(); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } - int A = 0; - return A; /* USER CODE END 3 */ } diff --git a/UPP/Core/Src/stm32f4xx_it.c b/UPP/Core/Src/stm32f4xx_it.c index a7ab8ff..c199d34 100644 --- a/UPP/Core/Src/stm32f4xx_it.c +++ b/UPP/Core/Src/stm32f4xx_it.c @@ -55,6 +55,8 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_adc3; +extern TIM_HandleTypeDef htim8; extern TIM_HandleTypeDef htim14; /* USER CODE BEGIN EV */ @@ -207,12 +209,29 @@ void TIM8_TRG_COM_TIM14_IRQHandler(void) /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */ #ifndef MATLAB /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */ + HAL_TIM_IRQHandler(&htim8); HAL_TIM_IRQHandler(&htim14); /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */ #endif /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */ } +/** + * @brief This function handles DMA2 stream0 global interrupt. + */ +void DMA2_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ +#include "adc_tools.h" + extern ADC_Period_t adc; + ADC_Handle(&adc); + /* USER CODE END DMA2_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc3); + /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ + + /* USER CODE END DMA2_Stream0_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/UPP/Core/Src/tim.c b/UPP/Core/Src/tim.c index fb00a90..04ec18c 100644 --- a/UPP/Core/Src/tim.c +++ b/UPP/Core/Src/tim.c @@ -26,6 +26,7 @@ TIM_HandleTypeDef htim1; TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim8; TIM_HandleTypeDef htim11; TIM_HandleTypeDef htim12; TIM_HandleTypeDef htim13; @@ -169,6 +170,47 @@ void MX_TIM3_Init(void) /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); +} +/* TIM8 init function */ +void MX_TIM8_Init(void) +{ + + /* USER CODE BEGIN TIM8_Init 0 */ + + /* USER CODE END TIM8_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM8_Init 1 */ + + /* USER CODE END TIM8_Init 1 */ + htim8.Instance = TIM8; + htim8.Init.Prescaler = 180-1; + htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + htim8.Init.Period = 1000; + htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim8.Init.RepetitionCounter = 0; + htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM8_Init 2 */ + + /* USER CODE END TIM8_Init 2 */ + } /* TIM11 init function */ void MX_TIM11_Init(void) @@ -281,6 +323,21 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM3_MspInit 1 */ } + else if(tim_baseHandle->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspInit 0 */ + + /* USER CODE END TIM8_MspInit 0 */ + /* TIM8 clock enable */ + __HAL_RCC_TIM8_CLK_ENABLE(); + + /* TIM8 interrupt Init */ + HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 15, 0); + HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn); + /* USER CODE BEGIN TIM8_MspInit 1 */ + + /* USER CODE END TIM8_MspInit 1 */ + } else if(tim_baseHandle->Instance==TIM11) { /* USER CODE BEGIN TIM11_MspInit 0 */ @@ -392,6 +449,20 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM3_MspDeInit 1 */ } + else if(tim_baseHandle->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspDeInit 0 */ + + /* USER CODE END TIM8_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM8_CLK_DISABLE(); + + /* TIM8 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn); + /* USER CODE BEGIN TIM8_MspDeInit 1 */ + + /* USER CODE END TIM8_MspDeInit 1 */ + } else if(tim_baseHandle->Instance==TIM11) { /* USER CODE BEGIN TIM11_MspDeInit 0 */ diff --git a/UPP/Core/UPP/upp_main.c b/UPP/Core/UPP/upp_main.c new file mode 100644 index 0000000..d95628b --- /dev/null +++ b/UPP/Core/UPP/upp_main.c @@ -0,0 +1,58 @@ +/** +****************************************************************************** +* @file upp_main.c +* @brief Инициализация и самые базовые вещи по работе УПП +****************************************************************************** +* @details +******************************************************************************/ +#include "main.h" // либы из AllLibs и вербальные имена из CubeMX +#include "upp_main.h" // всё остальное по работе с УПП +#include "adc.h" +#include "tim.h" + +#include "adc_tools.h" +ADC_Period_t adc; +#define ADC_CHANNEL_UBA 0 +#define ADC_CHANNEL_UAC 1 +#define ADC_CHANNEL_IC 2 +#define ADC_CHANNEL_IA 3 +#define ADC_CHANNEL_TEMP1 4 +#define ADC_CHANNEL_TEMP2 5 + +/** + * @brief Инициализация УПП. + * @return 0 - если ОК, >1 если ошибка. + */ +int UPP_Init(void) +{ + ADC_Init(&adc, &adc_tim, &hadc3); + + ADC_ConfigChannel(&adc, ADC_CHANNEL_UBA, 2048, 1216, 4095); + ADC_ConfigChannel(&adc, ADC_CHANNEL_UAC, 2048, 1216, 4095); + ADC_ConfigChannel(&adc, ADC_CHANNEL_IC, 2048, 53, 4095); + ADC_ConfigChannel(&adc, ADC_CHANNEL_IA, 2048, 53, 4095); + ADC_ConfigChannel(&adc, ADC_CHANNEL_TEMP1, 2554, 90, 4095); + ADC_ConfigChannel(&adc, ADC_CHANNEL_TEMP2, 2554, 90, 4095); + + return 0; +} + +/** + * @brief Инициализация основного цикла УПП. + * @return 0 - если ОК, >1 если ошибка. + */ +int UPP_PreWhile(void) +{ + ADC_Start(&adc, 1000); + return 0; +} + +/** + * @brief Основной цикл УПП. + * @return 0 - если ОК, >1 если ошибка. + */ +int UPP_While(void) +{ + + return 0; +} \ No newline at end of file diff --git a/UPP/Core/UPP/upp_main.h b/UPP/Core/UPP/upp_main.h new file mode 100644 index 0000000..3d72e8b --- /dev/null +++ b/UPP/Core/UPP/upp_main.h @@ -0,0 +1,21 @@ +/** +****************************************************************************** +* @file modbus_data.h +* @brief Определения структур данных Modbus устройства +****************************************************************************** +* @details +******************************************************************************/ + +#ifndef _UPP_MAIN_H +#define _UPP_MAIN_H + +#include "upp_config.h" + +/* Инициализация УПП */ +int UPP_Init(void); +/* Инициализация основного цикла УПП. */ +int UPP_PreWhile(void); +/* Основной цикл УПП. */ +int UPP_While(void); + +#endif //_UPP_MAIN_H \ No newline at end of file diff --git a/UPP/MDK-ARM/UPP.uvoptx b/UPP/MDK-ARM/UPP.uvoptx index 13cdd2d..66f3b96 100644 --- a/UPP/MDK-ARM/UPP.uvoptx +++ b/UPP/MDK-ARM/UPP.uvoptx @@ -1,4 +1,4 @@ - + 1.0 @@ -45,7 +45,7 @@ 79 66 8 - + 1 @@ -104,16 +104,16 @@ 0 0 6 - - - - - - - - - - + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll @@ -128,7 +128,7 @@ -U-O142 -O2190 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F427ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) - + 0 @@ -158,19 +158,19 @@ 0 0 - - + + 0 0 0 - - - - - - - - + + + + + + + + 1 1 @@ -298,7 +298,7 @@ - Application/User/Core + UPP/Main 1 0 0 @@ -310,14 +310,86 @@ 0 0 0 - ../Core/Src/main.c - main.c + ..\Core\UPP\upp_main.c + upp_main.c 0 0 2 11 + 5 + 0 + 0 + 0 + ..\Core\UPP\upp_main.h + upp_main.h + 0 + 0 + + + + + PowerMonitor + 1 + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + ..\Core\PowerMonitor\adc_tools.c + adc_tools.c + 0 + 0 + + + 3 + 13 + 5 + 0 + 0 + 0 + ..\Core\PowerMonitor\adc_tools.h + adc_tools.h + 0 + 0 + + + + + Thyristors + 0 + 0 + 0 + 0 + + + + Application/User/Core + 1 + 0 + 0 + 0 + + 5 + 14 + 1 + 0 + 0 + 0 + ../Core/Src/main.c + main.c + 0 + 0 + + + 5 + 15 1 0 0 @@ -328,8 +400,8 @@ 0 - 2 - 12 + 5 + 16 1 0 0 @@ -340,8 +412,8 @@ 0 - 2 - 13 + 5 + 17 1 0 0 @@ -352,8 +424,20 @@ 0 - 2 - 14 + 5 + 18 + 1 + 0 + 0 + 0 + ../Core/Src/dma.c + dma.c + 0 + 0 + + + 5 + 19 1 0 0 @@ -364,8 +448,8 @@ 0 - 2 - 15 + 5 + 20 1 0 0 @@ -376,8 +460,8 @@ 0 - 2 - 16 + 5 + 21 1 0 0 @@ -388,8 +472,8 @@ 0 - 2 - 17 + 5 + 22 1 0 0 @@ -400,8 +484,8 @@ 0 - 2 - 18 + 5 + 23 1 0 0 @@ -412,8 +496,8 @@ 0 - 2 - 19 + 5 + 24 1 0 0 @@ -424,8 +508,8 @@ 0 - 2 - 20 + 5 + 25 1 0 0 @@ -436,8 +520,8 @@ 0 - 2 - 21 + 5 + 26 1 0 0 @@ -451,13 +535,13 @@ MyLibs - 0 + 1 0 0 0 - 3 - 22 + 6 + 27 5 0 0 @@ -468,8 +552,8 @@ 0 - 3 - 23 + 6 + 28 5 0 0 @@ -480,8 +564,8 @@ 0 - 3 - 24 + 6 + 29 5 0 0 @@ -492,8 +576,8 @@ 0 - 3 - 25 + 6 + 30 5 0 0 @@ -504,8 +588,8 @@ 0 - 3 - 26 + 6 + 31 5 0 0 @@ -516,8 +600,8 @@ 0 - 3 - 27 + 6 + 32 5 0 0 @@ -536,8 +620,8 @@ 0 0 - 4 - 28 + 7 + 33 1 0 0 @@ -548,8 +632,8 @@ 0 - 4 - 29 + 7 + 34 1 0 0 @@ -560,8 +644,8 @@ 0 - 4 - 30 + 7 + 35 1 0 0 @@ -572,8 +656,8 @@ 0 - 4 - 31 + 7 + 36 1 0 0 @@ -584,8 +668,8 @@ 0 - 4 - 32 + 7 + 37 1 0 0 @@ -596,8 +680,8 @@ 0 - 4 - 33 + 7 + 38 1 0 0 @@ -608,8 +692,8 @@ 0 - 4 - 34 + 7 + 39 1 0 0 @@ -620,8 +704,8 @@ 0 - 4 - 35 + 7 + 40 1 0 0 @@ -632,8 +716,8 @@ 0 - 4 - 36 + 7 + 41 1 0 0 @@ -644,8 +728,8 @@ 0 - 4 - 37 + 7 + 42 1 0 0 @@ -656,8 +740,8 @@ 0 - 4 - 38 + 7 + 43 1 0 0 @@ -668,8 +752,8 @@ 0 - 4 - 39 + 7 + 44 1 0 0 @@ -688,8 +772,8 @@ 0 0 - 5 - 40 + 8 + 45 1 0 0 @@ -700,8 +784,8 @@ 0 - 5 - 41 + 8 + 46 1 0 0 @@ -720,8 +804,8 @@ 0 0 - 6 - 42 + 9 + 47 1 0 0 @@ -732,8 +816,8 @@ 0 - 6 - 43 + 9 + 48 1 0 0 @@ -744,8 +828,8 @@ 0 - 6 - 44 + 9 + 49 1 0 0 @@ -756,8 +840,8 @@ 0 - 6 - 45 + 9 + 50 1 0 0 @@ -768,8 +852,8 @@ 0 - 6 - 46 + 9 + 51 1 0 0 @@ -788,8 +872,8 @@ 0 0 - 7 - 47 + 10 + 52 1 0 0 @@ -800,8 +884,8 @@ 0 - 7 - 48 + 10 + 53 1 0 0 @@ -812,8 +896,8 @@ 0 - 7 - 49 + 10 + 54 1 0 0 @@ -824,8 +908,8 @@ 0 - 7 - 50 + 10 + 55 1 0 0 @@ -836,8 +920,8 @@ 0 - 7 - 51 + 10 + 56 1 0 0 @@ -848,8 +932,8 @@ 0 - 7 - 52 + 10 + 57 1 0 0 @@ -860,8 +944,8 @@ 0 - 7 - 53 + 10 + 58 1 0 0 @@ -872,8 +956,8 @@ 0 - 7 - 54 + 10 + 59 1 0 0 @@ -884,8 +968,8 @@ 0 - 7 - 55 + 10 + 60 1 0 0 @@ -896,8 +980,8 @@ 0 - 7 - 56 + 10 + 61 1 0 0 @@ -908,8 +992,8 @@ 0 - 7 - 57 + 10 + 62 1 0 0 @@ -920,8 +1004,8 @@ 0 - 7 - 58 + 10 + 63 1 0 0 @@ -932,8 +1016,8 @@ 0 - 7 - 59 + 10 + 64 1 0 0 @@ -944,8 +1028,8 @@ 0 - 7 - 60 + 10 + 65 1 0 0 @@ -956,8 +1040,8 @@ 0 - 7 - 61 + 10 + 66 1 0 0 @@ -968,8 +1052,8 @@ 0 - 7 - 62 + 10 + 67 1 0 0 @@ -980,8 +1064,8 @@ 0 - 7 - 63 + 10 + 68 1 0 0 @@ -992,8 +1076,8 @@ 0 - 7 - 64 + 10 + 69 1 0 0 @@ -1004,8 +1088,8 @@ 0 - 7 - 65 + 10 + 70 1 0 0 @@ -1016,8 +1100,8 @@ 0 - 7 - 66 + 10 + 71 1 0 0 @@ -1028,8 +1112,8 @@ 0 - 7 - 67 + 10 + 72 1 0 0 @@ -1040,8 +1124,8 @@ 0 - 7 - 68 + 10 + 73 1 0 0 @@ -1052,8 +1136,8 @@ 0 - 7 - 69 + 10 + 74 1 0 0 @@ -1064,8 +1148,8 @@ 0 - 7 - 70 + 10 + 75 1 0 0 @@ -1084,8 +1168,8 @@ 0 0 - 8 - 71 + 11 + 76 1 0 0 @@ -1104,8 +1188,8 @@ 0 0 - 9 - 72 + 12 + 77 2 0 0 diff --git a/UPP/MDK-ARM/UPP.uvprojx b/UPP/MDK-ARM/UPP.uvprojx index 13644f1..b8ac044 100644 --- a/UPP/MDK-ARM/UPP.uvprojx +++ b/UPP/MDK-ARM/UPP.uvprojx @@ -1,7 +1,10 @@ - - + + + 2.1 +
### uVision Project, (C) Keil Software
+ UPP @@ -17,28 +20,28 @@ Keil.STM32F4xx_DFP.2.16.0 http://www.keil.com/pack/ IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") TZ - - - + + + 0 - - - - - - - - - - + + + + + + + + + + $$Device:STM32F427ZGTx$CMSIS\SVD\STM32F427x.svd 0 0 - - - - - + + + + + 0 0 @@ -53,15 +56,15 @@ 1 1 1 - + 1 0 0 0 0 - - + + 0 0 0 @@ -70,8 +73,8 @@ 0 0 - - + + 0 0 0 @@ -80,15 +83,15 @@ 0 1 - - + + 0 0 0 0 1 - + 0 @@ -102,8 +105,8 @@ 0 0 3 - - + + 0 @@ -136,11 +139,11 @@ 1 BIN\UL2V8M.DLL - - - - - + + + + + 0 @@ -173,7 +176,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -308,7 +311,7 @@ 0x10000 - + 1 @@ -335,10 +338,10 @@ 0 0 - + USE_HAL_DRIVER,STM32F427xx - - ../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../AllLibs/ExtMemory/Inc;../AllLibs/Modbus/Inc;../AllLibs/MyLibs/MyLibs/Inc;../AllLibs/MyLibs/RTT;../AllLibs/PeriphGeneral/Inc;../Core/Configs + + ../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../AllLibs/ExtMemory/Inc;../AllLibs/Modbus/Inc;../AllLibs/MyLibs/MyLibs/Inc;../AllLibs/MyLibs/RTT;../AllLibs/PeriphGeneral/Inc;../Core/Configs;..\Core\PowerMonitor;..\Core\Thyristors;..\Core\UPP @@ -353,10 +356,10 @@ 0 1 - - - - + + + + @@ -366,15 +369,15 @@ 0 1 0 - - - - - - - - - + + + + + + + + + @@ -429,6 +432,39 @@ + + UPP/Main + + + upp_main.c + 1 + ..\Core\UPP\upp_main.c + + + upp_main.h + 5 + ..\Core\UPP\upp_main.h + + + + + PowerMonitor + + + adc_tools.c + 1 + ..\Core\PowerMonitor\adc_tools.c + + + adc_tools.h + 5 + ..\Core\PowerMonitor\adc_tools.h + + + + + Thyristors + Application/User/Core @@ -452,6 +488,62 @@ 1 ../Core/Src/can.c + + dma.c + 1 + ../Core/Src/dma.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + iwdg.c 1 @@ -793,24 +885,26 @@ + - + - + - + - + - + - + + @@ -819,5 +913,5 @@ - + diff --git a/UPP/UPP.ioc b/UPP/UPP.ioc index b810d65..817c3bc 100644 --- a/UPP/UPP.ioc +++ b/UPP/UPP.ioc @@ -1,17 +1,28 @@ #MicroXplorer Configuration settings - do not modify -ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_0 -ADC1.ContinuousConvMode=ENABLE -ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode -ADC1.NbrOfConversionFlag=1 -ADC1.Rank-1\#ChannelRegularConversion=1 -ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -ADC1.master=1 -ADC3.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_7 -ADC3.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,NbrOfConversionFlag,NbrOfConversion -ADC3.NbrOfConversion=1 +ADC3.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_4 +ADC3.Channel-16\#ChannelRegularConversion=ADC_CHANNEL_5 +ADC3.Channel-17\#ChannelRegularConversion=ADC_CHANNEL_6 +ADC3.Channel-18\#ChannelRegularConversion=ADC_CHANNEL_7 +ADC3.Channel-19\#ChannelRegularConversion=ADC_CHANNEL_8 +ADC3.Channel-20\#ChannelRegularConversion=ADC_CHANNEL_10 +ADC3.EOCSelection=ADC_EOC_SEQ_CONV +ADC3.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T8_TRGO +ADC3.IPParameters=Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,NbrOfConversionFlag,NbrOfConversion,ScanConvMode,Rank-16\#ChannelRegularConversion,Channel-16\#ChannelRegularConversion,SamplingTime-16\#ChannelRegularConversion,Rank-17\#ChannelRegularConversion,Channel-17\#ChannelRegularConversion,SamplingTime-17\#ChannelRegularConversion,Rank-18\#ChannelRegularConversion,Channel-18\#ChannelRegularConversion,SamplingTime-18\#ChannelRegularConversion,Rank-19\#ChannelRegularConversion,Channel-19\#ChannelRegularConversion,SamplingTime-19\#ChannelRegularConversion,Rank-20\#ChannelRegularConversion,Channel-20\#ChannelRegularConversion,SamplingTime-20\#ChannelRegularConversion,ExternalTrigConv,EOCSelection +ADC3.NbrOfConversion=6 ADC3.NbrOfConversionFlag=1 ADC3.Rank-15\#ChannelRegularConversion=1 +ADC3.Rank-16\#ChannelRegularConversion=2 +ADC3.Rank-17\#ChannelRegularConversion=3 +ADC3.Rank-18\#ChannelRegularConversion=4 +ADC3.Rank-19\#ChannelRegularConversion=5 +ADC3.Rank-20\#ChannelRegularConversion=6 ADC3.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.SamplingTime-16\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.SamplingTime-17\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.SamplingTime-18\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.SamplingTime-19\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.SamplingTime-20\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.ScanConvMode=ENABLE CAD.formats= CAD.pinconfig= CAD.provider= @@ -22,6 +33,18 @@ CAN1.CalculateTimeBit=4000 CAN1.CalculateTimeQuantum=222.22222222222223 CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler CAN1.Prescaler=10 +Dma.ADC3.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC3.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.ADC3.0.Instance=DMA2_Stream0 +Dma.ADC3.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC3.0.MemInc=DMA_MINC_ENABLE +Dma.ADC3.0.Mode=DMA_NORMAL +Dma.ADC3.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC3.0.PeriphInc=DMA_PINC_DISABLE +Dma.ADC3.0.Priority=DMA_PRIORITY_LOW +Dma.ADC3.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.Request0=ADC3 +Dma.RequestsNb=1 File.Version=6 GPIO.groupedBy=Group By Peripherals IWDG.IPParameters=Prescaler @@ -29,15 +52,16 @@ IWDG.Prescaler=IWDG_PRESCALER_32 KeepUserPlacement=false Mcu.CPN=STM32F427ZGT6 Mcu.Family=STM32F4 -Mcu.IP0=ADC1 -Mcu.IP1=ADC3 +Mcu.IP0=ADC3 +Mcu.IP1=CAN1 Mcu.IP10=TIM3 -Mcu.IP11=TIM11 -Mcu.IP12=TIM12 -Mcu.IP13=TIM13 -Mcu.IP14=USART3 -Mcu.IP15=USART6 -Mcu.IP2=CAN1 +Mcu.IP11=TIM8 +Mcu.IP12=TIM11 +Mcu.IP13=TIM12 +Mcu.IP14=TIM13 +Mcu.IP15=USART3 +Mcu.IP16=USART6 +Mcu.IP2=DMA Mcu.IP3=IWDG Mcu.IP4=NVIC Mcu.IP5=RCC @@ -45,7 +69,7 @@ Mcu.IP6=RTC Mcu.IP7=SPI3 Mcu.IP8=SYS Mcu.IP9=TIM1 -Mcu.IPNb=16 +Mcu.IPNb=17 Mcu.Name=STM32F427Z(G-I)Tx Mcu.Package=LQFP144 Mcu.Pin0=PE2 @@ -56,54 +80,54 @@ Mcu.Pin12=PF10 Mcu.Pin13=PH0/OSC_IN Mcu.Pin14=PH1/OSC_OUT Mcu.Pin15=PC0 -Mcu.Pin16=PA0/WKUP -Mcu.Pin17=PA4 -Mcu.Pin18=PA5 -Mcu.Pin19=PA6 +Mcu.Pin16=PA4 +Mcu.Pin17=PA5 +Mcu.Pin18=PA6 +Mcu.Pin19=PB0 Mcu.Pin2=PE4 -Mcu.Pin20=PB0 -Mcu.Pin21=PB1 -Mcu.Pin22=PF11 -Mcu.Pin23=PB10 -Mcu.Pin24=PB11 -Mcu.Pin25=PB13 -Mcu.Pin26=PG6 -Mcu.Pin27=PC6 -Mcu.Pin28=PC7 -Mcu.Pin29=PC8 +Mcu.Pin20=PB1 +Mcu.Pin21=PF11 +Mcu.Pin22=PB10 +Mcu.Pin23=PB11 +Mcu.Pin24=PB13 +Mcu.Pin25=PG6 +Mcu.Pin26=PC6 +Mcu.Pin27=PC7 +Mcu.Pin28=PC8 +Mcu.Pin29=PC9 Mcu.Pin3=PE5 -Mcu.Pin30=PC9 -Mcu.Pin31=PA8 -Mcu.Pin32=PA9 -Mcu.Pin33=PA10 -Mcu.Pin34=PA11 -Mcu.Pin35=PA12 -Mcu.Pin36=PA13 -Mcu.Pin37=PA14 -Mcu.Pin38=PA15 -Mcu.Pin39=PC10 +Mcu.Pin30=PA8 +Mcu.Pin31=PA9 +Mcu.Pin32=PA10 +Mcu.Pin33=PA11 +Mcu.Pin34=PA12 +Mcu.Pin35=PA13 +Mcu.Pin36=PA14 +Mcu.Pin37=PA15 +Mcu.Pin38=PC10 +Mcu.Pin39=PC11 Mcu.Pin4=PE6 -Mcu.Pin40=PC11 -Mcu.Pin41=PC12 -Mcu.Pin42=PD2 -Mcu.Pin43=PD3 -Mcu.Pin44=PD6 -Mcu.Pin45=PG12 -Mcu.Pin46=PG15 -Mcu.Pin47=PB3 -Mcu.Pin48=PB6 -Mcu.Pin49=PB7 +Mcu.Pin40=PC12 +Mcu.Pin41=PD2 +Mcu.Pin42=PD3 +Mcu.Pin43=PD6 +Mcu.Pin44=PG12 +Mcu.Pin45=PG15 +Mcu.Pin46=PB3 +Mcu.Pin47=PB6 +Mcu.Pin48=PB7 +Mcu.Pin49=PB8 Mcu.Pin5=PC13 -Mcu.Pin50=PB8 -Mcu.Pin51=PB9 -Mcu.Pin52=PE0 -Mcu.Pin53=PE1 -Mcu.Pin54=VP_IWDG_VS_IWDG -Mcu.Pin55=VP_RTC_VS_RTC_Activate -Mcu.Pin56=VP_RTC_VS_RTC_Calendar -Mcu.Pin57=VP_SYS_VS_tim14 -Mcu.Pin58=VP_TIM1_VS_ClockSourceINT -Mcu.Pin59=VP_TIM3_VS_ClockSourceINT +Mcu.Pin50=PB9 +Mcu.Pin51=PE0 +Mcu.Pin52=PE1 +Mcu.Pin53=VP_IWDG_VS_IWDG +Mcu.Pin54=VP_RTC_VS_RTC_Activate +Mcu.Pin55=VP_RTC_VS_RTC_Calendar +Mcu.Pin56=VP_SYS_VS_tim14 +Mcu.Pin57=VP_TIM1_VS_ClockSourceINT +Mcu.Pin58=VP_TIM3_VS_ClockSourceINT +Mcu.Pin59=VP_TIM8_VS_ClockSourceINT Mcu.Pin6=PC14/OSC32_IN Mcu.Pin60=VP_TIM11_VS_ClockSourceINT Mcu.Pin61=VP_TIM12_VS_ClockSourceINT @@ -113,11 +137,12 @@ Mcu.Pin8=PF6 Mcu.Pin9=PF7 Mcu.PinsNb=63 Mcu.ThirdPartyNb=0 -Mcu.UserConstants=mb_huart,huart3;mbdbg_htim,htim11;mb_htim,htim12;mb_dbg_huart,huart6;ustim,htim13;mem_hspi,hspi3;hpwm1,htim1;hpwm2,htim2;PWM_CHANNEL_1,TIM_CHANNEL_1;PWM_CHANNEL_2,TIM_CHANNEL_2;PWM_CHANNEL_3,TIM_CHANNEL_3;PWM_CHANNEL_4,TIM_CHANNEL_4;PWM_CHANNEL_5,TIM_CHANNEL_3;PWM_CHANNEL_6,TIM_CHANNEL_4 +Mcu.UserConstants=mb_huart,huart3;mbdbg_htim,htim11;mb_htim,htim12;mb_dbg_huart,huart6;ustim,htim13;mem_hspi,hspi3;hpwm1,htim1;hpwm2,htim2;PWM_CHANNEL_1,TIM_CHANNEL_1;PWM_CHANNEL_2,TIM_CHANNEL_2;PWM_CHANNEL_3,TIM_CHANNEL_3;PWM_CHANNEL_4,TIM_CHANNEL_4;PWM_CHANNEL_5,TIM_CHANNEL_3;PWM_CHANNEL_6,TIM_CHANNEL_4;adc_tim,htim8 Mcu.UserName=STM32F427ZGTx MxCube.Version=6.12.1 MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -131,7 +156,6 @@ NVIC.TIM8_TRG_COM_TIM14_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true NVIC.TimeBase=TIM8_TRG_COM_TIM14_IRQn NVIC.TimeBaseIP=TIM14 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -PA0/WKUP.Signal=ADCx_IN0 PA10.GPIOParameters=GPIO_Label PA10.GPIO_Label=PWM3 PA10.Locked=true @@ -370,7 +394,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-true-HAL-true,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_TIM13_Init-TIM13-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_TIM1_Init-TIM1-false-HAL-true,10-MX_TIM3_Init-TIM3-false-HAL-true,11-MX_USART6_UART_Init-USART6-false-HAL-true,12-MX_SPI3_Init-SPI3-false-HAL-true,13-MX_TIM11_Init-TIM11-false-HAL-true,14-MX_TIM12_Init-TIM12-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-true-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC3_Init-ADC3-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,6-MX_CAN1_Init-CAN1-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_TIM13_Init-TIM13-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_TIM1_Init-TIM1-false-HAL-true,11-MX_TIM3_Init-TIM3-false-HAL-true,12-MX_USART6_UART_Init-USART6-false-HAL-true,13-MX_SPI3_Init-SPI3-false-HAL-true,14-MX_TIM11_Init-TIM11-false-HAL-true,15-MX_TIM12_Init-TIM12-false-HAL-true,16-MX_TIM8_Init-TIM8-false-HAL-true RCC.48MHZClocksFreq_Value=90000000 RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -415,8 +439,6 @@ RTC.IPParameters=WeekDay,Year,Date,Month,Hours RTC.Month=RTC_MONTH_JANUARY RTC.WeekDay=RTC_WEEKDAY_MONDAY RTC.Year=25 -SH.ADCx_IN0.0=ADC1_IN0,IN0 -SH.ADCx_IN0.ConfNb=1 SH.ADCx_IN10.0=ADC3_IN10,IN10 SH.ADCx_IN10.ConfNb=1 SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 @@ -451,6 +473,11 @@ TIM13.Prescaler=90-1 TIM3.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 TIM3.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +TIM8.IPParameters=Prescaler,Period,TIM_MasterSlaveMode,TIM_MasterOutputTrigger +TIM8.Period=1000 +TIM8.Prescaler=180-1 +TIM8.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE +TIM8.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE USART3.IPParameters=VirtualMode USART3.VirtualMode=VM_ASYNC USART6.IPParameters=VirtualMode @@ -473,4 +500,6 @@ VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_TIM8_VS_ClockSourceINT.Mode=Internal +VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT board=custom diff --git a/Информация для программиста (УПП СП СЭД)/Значения температуры в ед АЦП.xlsx b/Информация для программиста (УПП СП СЭД)/Значения температуры в ед АЦП.xlsx index 9ebd825..392e475 100644 Binary files a/Информация для программиста (УПП СП СЭД)/Значения температуры в ед АЦП.xlsx and b/Информация для программиста (УПП СП СЭД)/Значения температуры в ед АЦП.xlsx differ