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Добавил в проект оптическую шину.

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This commit is contained in:
sokolovstanislav 2024-04-04 14:15:38 +03:00
parent 9394bee3c3
commit e0197a05ac
5 changed files with 802 additions and 66 deletions
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383
MainController/MainController.bdf
View File

@ -193,7 +193,7 @@ applicable agreement for further details.
(input)
(rect 368 -288 544 -272)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "HWPdatain[1..0]" (rect 5 0 87 12)(font "Arial" ))
(text "HWPdatain[1..0]" (rect 5 0 86 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 92 12)(pt 117 12))
@ -204,6 +204,7 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 -288 368 -256))
)
(pin
(output)
@ -664,9 +665,41 @@ applicable agreement for further details.
)
(annotation_block (location)(rect 2024 -104 2072 -88))
)
(pin
(output)
(rect 1856 1920 2032 1936)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "OBclk" (rect 90 0 119 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 1856 1936 2032 1952)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "OBdata" (rect 90 0 126 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(bidir)
(rect 1848 1664 2024 1680)
(rect 1856 2104 2032 2120)
(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "Data[7..0]" (rect 122 0 171 12)(font "Arial" ))
(pt 0 8)
@ -680,7 +713,7 @@ applicable agreement for further details.
(line (pt 52 8)(pt 56 12))
)
(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 2032 1552 2088 1664))
(annotation_block (location)(rect 2040 1992 2096 2104))
)
(pin
(bidir)
@ -1690,7 +1723,7 @@ applicable agreement for further details.
)
)
(symbol
(rect 1048 1640 1376 1752)
(rect 1040 2080 1368 2192)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst21" (rect 8 96 37 108)(font "Arial" ))
(port
@ -1741,7 +1774,7 @@ applicable agreement for further details.
(drawing
(rectangle (rect 16 16 312 96))
)
(annotation_block (parameter)(rect 1040 1592 1280 1640))
(annotation_block (parameter)(rect 1032 2032 1272 2080))
)
(symbol
(rect 704 -64 800 32)
@ -2100,6 +2133,171 @@ applicable agreement for further details.
(rectangle (rect 16 16 80 80))
)
)
(symbol
(rect 1048 1880 1376 2024)
(text "RAM9X8_OpticalBusMaster" (rect 5 0 138 12)(font "Arial" ))
(text "inst1" (rect 8 128 31 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 161 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 182 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 12 12)(font "Arial" ))
(text "we" (rect 21 59 33 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 11 12)(font "Arial" ))
(text "oe" (rect 21 75 32 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 11 12)(font "Arial" ))
(text "ce" (rect 21 91 32 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 328 48)
(output)
(text "obclk" (rect 0 0 25 12)(font "Arial" ))
(text "obclk" (rect 286 43 311 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48))
)
(port
(pt 328 64)
(output)
(text "obdata" (rect 0 0 33 12)(font "Arial" ))
(text "obdata" (rect 280 59 313 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 126 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 334 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"REG_ADDR_CMD_UPPER_BYTE"
"52"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_LOWER_BYTE"
"53"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_8_UPPER_BYTE"
"54"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_8_LOWER_BYTE"
"55"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_7_UPPER_BYTE"
"56"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_7_LOWER_BYTE"
"57"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_6_UPPER_BYTE"
"58"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_6_LOWER_BYTE"
"59"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_5_UPPER_BYTE"
"60"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_5_LOWER_BYTE"
"61"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_4_UPPER_BYTE"
"62"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_4_LOWER_BYTE"
"63"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_3_UPPER_BYTE"
"64"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_3_LOWER_BYTE"
"65"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_2_UPPER_BYTE"
"66"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_2_LOWER_BYTE"
"67"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_1_UPPER_BYTE"
"68"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_1_LOWER_BYTE"
"69"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 128))
)
(annotation_block (parameter)(rect 1032 1584 1344 1880))
)
(connector
(pt 488 136)
(pt 488 120)
@ -2390,10 +2588,6 @@ applicable agreement for further details.
(pt 608 976)
(pt 608 1432)
)
(connector
(pt 608 1432)
(pt 608 1512)
)
(connector
(pt 1000 592)
(pt 1000 912)
@ -2447,62 +2641,6 @@ applicable agreement for further details.
(pt 608 368)
(pt 608 408)
)
(connector
(pt 1048 1672)
(pt 1000 1672)
(bus)
)
(connector
(pt 1000 912)
(pt 1000 1448)
(bus)
)
(connector
(pt 1000 1448)
(pt 1000 1672)
(bus)
)
(connector
(pt 1048 1688)
(pt 984 1688)
)
(connector
(pt 984 928)
(pt 984 1464)
)
(connector
(pt 984 1464)
(pt 984 1688)
)
(connector
(pt 1048 1704)
(pt 968 1704)
)
(connector
(pt 968 944)
(pt 968 1480)
)
(connector
(pt 968 1480)
(pt 968 1704)
)
(connector
(pt 1048 1720)
(pt 952 1720)
)
(connector
(pt 952 960)
(pt 952 1496)
)
(connector
(pt 952 1496)
(pt 952 1720)
)
(connector
(pt 1848 1672)
(pt 1376 1672)
(bus)
)
(connector
(pt 1368 288)
(pt 1840 288)
@ -2898,6 +3036,116 @@ applicable agreement for further details.
(pt 800 -280)
(pt 904 -280)
)
(connector
(pt 1000 2112)
(pt 1040 2112)
(bus)
)
(connector
(pt 984 2128)
(pt 1040 2128)
)
(connector
(pt 968 2144)
(pt 1040 2144)
)
(connector
(pt 952 2160)
(pt 1040 2160)
)
(connector
(pt 1000 912)
(pt 1000 1448)
(bus)
)
(connector
(pt 984 928)
(pt 984 1464)
)
(connector
(pt 968 944)
(pt 968 1480)
)
(connector
(pt 952 960)
(pt 952 1496)
)
(connector
(pt 1048 1928)
(pt 1000 1928)
(bus)
)
(connector
(pt 1000 1448)
(pt 1000 1928)
(bus)
)
(connector
(pt 1000 1928)
(pt 1000 2112)
(bus)
)
(connector
(pt 1048 1944)
(pt 984 1944)
)
(connector
(pt 984 1464)
(pt 984 1944)
)
(connector
(pt 984 1944)
(pt 984 2128)
)
(connector
(pt 1048 1960)
(pt 968 1960)
)
(connector
(pt 968 1480)
(pt 968 1960)
)
(connector
(pt 968 1960)
(pt 968 2144)
)
(connector
(pt 1048 1976)
(pt 952 1976)
)
(connector
(pt 952 1496)
(pt 952 1976)
)
(connector
(pt 952 1976)
(pt 952 2160)
)
(connector
(pt 1048 1912)
(pt 608 1912)
)
(connector
(pt 608 1432)
(pt 608 1512)
)
(connector
(pt 608 1512)
(pt 608 1912)
)
(connector
(pt 1368 2112)
(pt 1856 2112)
(bus)
)
(connector
(pt 1376 1928)
(pt 1856 1928)
)
(connector
(pt 1376 1944)
(pt 1856 1944)
)
(junction (pt 1000 288))
(junction (pt 984 304))
(junction (pt 968 320))
@ -2944,3 +3192,8 @@ applicable agreement for further details.
(junction (pt 904 -280))
(junction (pt 608 -160))
(junction (pt 608 -264))
(junction (pt 1000 1928))
(junction (pt 984 1944))
(junction (pt 968 1960))
(junction (pt 952 1976))
(junction (pt 608 1512))

7
MainController/MainController.qsf
View File

@ -306,4 +306,11 @@ set_location_assignment PIN_5 -to AddrDevice_2
set_global_assignment -name VHDL_FILE RAM9X8_HWPBusMaster.vhd
set_location_assignment PIN_51 -to HWPdatain[0]
set_location_assignment PIN_46 -to HWPdatain[1]
set_global_assignment -name VHDL_FILE RAM9X8_OpticalBusMaster.vhd
set_location_assignment PIN_22 -to OBclk
set_location_assignment PIN_63 -to OBdata
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPdatain[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HWPdatain[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OBclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OBdata
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

186
MainController/RAM9X8_OpticalBusMaster.bsf Normal file
View File

@ -0,0 +1,186 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 344 160)
(text "RAM9X8_OpticalBusMaster" (rect 5 0 120 12)(font "Arial" ))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "we" (rect 0 0 10 12)(font "Arial" ))
(text "we" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "oe" (rect 0 0 9 12)(font "Arial" ))
(text "oe" (rect 21 75 30 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "ce" (rect 0 0 9 12)(font "Arial" ))
(text "ce" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 328 48)
(output)
(text "obclk" (rect 0 0 20 12)(font "Arial" ))
(text "obclk" (rect 287 43 307 55)(font "Arial" ))
(line (pt 328 48)(pt 312 48)(line_width 1))
)
(port
(pt 328 64)
(output)
(text "obdata" (rect 0 0 25 12)(font "Arial" ))
(text "obdata" (rect 282 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
)
(port
(pt 328 32)
(bidir)
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
(line (pt 328 32)(pt 312 32)(line_width 3))
)
(parameter
"REG_ADDR_CMD_UPPER_BYTE"
"52"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_CMD_LOWER_BYTE"
"53"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_8_UPPER_BYTE"
"54"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_8_LOWER_BYTE"
"55"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_7_UPPER_BYTE"
"56"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_7_LOWER_BYTE"
"57"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_6_UPPER_BYTE"
"58"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_6_LOWER_BYTE"
"59"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_5_UPPER_BYTE"
"60"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_5_LOWER_BYTE"
"61"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_4_UPPER_BYTE"
"62"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_4_LOWER_BYTE"
"63"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_3_UPPER_BYTE"
"64"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_3_LOWER_BYTE"
"65"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_2_UPPER_BYTE"
"66"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_2_LOWER_BYTE"
"67"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_1_UPPER_BYTE"
"68"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"REG_ADDR_WORD_1_LOWER_BYTE"
"69"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DATA_BUS_WIDTH"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"ADDRESS_BUS_WIDTH"
"9"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 312 128)(line_width 1))
)
(annotation_block (parameter)(rect 344 -64 444 16))
)

290
MainController/RAM9X8_OpticalBusMaster.vhd Normal file
View File

@ -0,0 +1,290 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RAM9X8_OpticalBusMaster is
generic(
REG_ADDR_CMD_UPPER_BYTE : integer := 52;
REG_ADDR_CMD_LOWER_BYTE : integer := 53;
REG_ADDR_WORD_8_UPPER_BYTE : integer := 54;
REG_ADDR_WORD_8_LOWER_BYTE : integer := 55;
REG_ADDR_WORD_7_UPPER_BYTE : integer := 56;
REG_ADDR_WORD_7_LOWER_BYTE : integer := 57;
REG_ADDR_WORD_6_UPPER_BYTE : integer := 58;
REG_ADDR_WORD_6_LOWER_BYTE : integer := 59;
REG_ADDR_WORD_5_UPPER_BYTE : integer := 60;
REG_ADDR_WORD_5_LOWER_BYTE : integer := 61;
REG_ADDR_WORD_4_UPPER_BYTE : integer := 62;
REG_ADDR_WORD_4_LOWER_BYTE : integer := 63;
REG_ADDR_WORD_3_UPPER_BYTE : integer := 64;
REG_ADDR_WORD_3_LOWER_BYTE : integer := 65;
REG_ADDR_WORD_2_UPPER_BYTE : integer := 66;
REG_ADDR_WORD_2_LOWER_BYTE : integer := 67;
REG_ADDR_WORD_1_UPPER_BYTE : integer := 68;
REG_ADDR_WORD_1_LOWER_BYTE : integer := 69;
DATA_BUS_WIDTH : integer := 8;
ADDRESS_BUS_WIDTH : integer := 9
);
port(
clk : in std_logic;
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
we : in std_logic;
oe : in std_logic;
ce : in std_logic;
obclk : out std_logic := '1';
obdata : out std_logic := '1'
);
end entity;
architecture behavorial of RAM9X8_OpticalBusMaster is
signal dataBuf : std_logic_vector(127 downto 0) := (others => '0');
signal dataToSend : std_logic_vector(127 downto 0) := (others => '0');
signal cmdBuf : std_logic_vector(15 downto 0) := (others => '0');
type CommunicationState_start is (Waiting, DataSending, CRCSending);
signal CommunicationState : CommunicationState_start := Waiting ;
signal resetCRC : std_logic := '1';
signal CRC : std_logic_vector(3 downto 0) := x"0";
signal bufCRC : std_logic_vector(3 downto 0) := x"0";
signal dataCRC : std_logic_vector(127 downto 0) := (others => '0'); -- переключает
signal readyCRC : std_logic := '0'; -- готовность контрольной суммы
signal lineBusy : std_logic := '1';
signal start : std_logic := '0';
signal startPrev : std_logic := '0';
begin
process (we, oe, ce)
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
begin
if (ce = '0') then -- Если микросхема выбрана
addr := conv_integer(address);
if (addr = REG_ADDR_CMD_UPPER_BYTE or addr = REG_ADDR_CMD_LOWER_BYTE
or addr = REG_ADDR_WORD_8_UPPER_BYTE or addr = REG_ADDR_WORD_8_LOWER_BYTE
or addr = REG_ADDR_WORD_7_UPPER_BYTE or addr = REG_ADDR_WORD_7_LOWER_BYTE
or addr = REG_ADDR_WORD_6_UPPER_BYTE or addr = REG_ADDR_WORD_6_LOWER_BYTE
or addr = REG_ADDR_WORD_5_UPPER_BYTE or addr = REG_ADDR_WORD_5_LOWER_BYTE
or addr = REG_ADDR_WORD_4_UPPER_BYTE or addr = REG_ADDR_WORD_4_LOWER_BYTE
or addr = REG_ADDR_WORD_3_UPPER_BYTE or addr = REG_ADDR_WORD_3_LOWER_BYTE
or addr = REG_ADDR_WORD_2_UPPER_BYTE or addr = REG_ADDR_WORD_2_LOWER_BYTE
or addr = REG_ADDR_WORD_1_UPPER_BYTE or addr = REG_ADDR_WORD_1_LOWER_BYTE) then
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
case addr is
when REG_ADDR_CMD_UPPER_BYTE =>
data <= cmdBuf(15 downto 8);
when REG_ADDR_CMD_LOWER_BYTE =>
data <= cmdBuf(7 downto 0);
when REG_ADDR_WORD_8_UPPER_BYTE =>
data <= dataBuf(127 downto 120);
when REG_ADDR_WORD_8_LOWER_BYTE =>
data <= dataBuf(119 downto 112);
when REG_ADDR_WORD_7_UPPER_BYTE =>
data <= dataBuf(111 downto 104);
when REG_ADDR_WORD_7_LOWER_BYTE =>
data <= dataBuf(103 downto 96);
when REG_ADDR_WORD_6_UPPER_BYTE =>
data <= dataBuf(95 downto 88);
when REG_ADDR_WORD_6_LOWER_BYTE =>
data <= dataBuf(87 downto 80);
when REG_ADDR_WORD_5_UPPER_BYTE =>
data <= dataBuf(79 downto 72);
when REG_ADDR_WORD_5_LOWER_BYTE =>
data <= dataBuf(71 downto 64);
when REG_ADDR_WORD_4_UPPER_BYTE =>
data <= dataBuf(63 downto 56);
when REG_ADDR_WORD_4_LOWER_BYTE =>
data <= dataBuf(55 downto 48);
when REG_ADDR_WORD_3_UPPER_BYTE =>
data <= dataBuf(47 downto 40);
when REG_ADDR_WORD_3_LOWER_BYTE =>
data <= dataBuf(39 downto 32);
when REG_ADDR_WORD_2_UPPER_BYTE =>
data <= dataBuf(31 downto 24);
when REG_ADDR_WORD_2_LOWER_BYTE =>
data <= dataBuf(23 downto 16);
when REG_ADDR_WORD_1_UPPER_BYTE =>
data <= dataBuf(15 downto 8);
when REG_ADDR_WORD_1_LOWER_BYTE =>
data <= dataBuf(7 downto 0);
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
case addr is
when REG_ADDR_CMD_UPPER_BYTE =>
cmdBuf(15 downto 8) <= data;
when REG_ADDR_CMD_LOWER_BYTE =>
cmdBuf(7 downto 0) <= data;
when REG_ADDR_WORD_8_UPPER_BYTE =>
dataBuf(127 downto 120) <= data;
when REG_ADDR_WORD_8_LOWER_BYTE =>
dataBuf(119 downto 112) <= data;
when REG_ADDR_WORD_7_UPPER_BYTE =>
dataBuf(111 downto 104) <= data;
when REG_ADDR_WORD_7_LOWER_BYTE =>
dataBuf(103 downto 96) <= data;
when REG_ADDR_WORD_6_UPPER_BYTE =>
dataBuf(95 downto 88) <= data;
when REG_ADDR_WORD_6_LOWER_BYTE =>
dataBuf(87 downto 80) <= data;
when REG_ADDR_WORD_5_UPPER_BYTE =>
dataBuf(79 downto 72) <= data;
when REG_ADDR_WORD_5_LOWER_BYTE =>
dataBuf(71 downto 64) <= data;
when REG_ADDR_WORD_4_UPPER_BYTE =>
dataBuf(63 downto 56) <= data;
when REG_ADDR_WORD_4_LOWER_BYTE =>
dataBuf(55 downto 48) <= data;
when REG_ADDR_WORD_3_UPPER_BYTE =>
dataBuf(47 downto 40) <= data;
when REG_ADDR_WORD_3_LOWER_BYTE =>
dataBuf(39 downto 32) <= data;
when REG_ADDR_WORD_2_UPPER_BYTE =>
dataBuf(31 downto 24) <= data;
when REG_ADDR_WORD_2_LOWER_BYTE =>
dataBuf(23 downto 16) <= data;
when REG_ADDR_WORD_1_UPPER_BYTE =>
dataBuf(15 downto 8) <= data;
when REG_ADDR_WORD_1_LOWER_BYTE =>
dataBuf(7 downto 0) <= data;
when others =>
data <= (others => 'Z'); -- Запретить запись на шину
end case;
if (addr = REG_ADDR_WORD_1_LOWER_BYTE) then
start <= '1';
else
start <= '0';
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
else
data <= (others => 'Z'); -- Запретить запись на шину
end if;
end process;
process(clk) is
variable count : integer range 0 to 31 := 0;
variable countValue : integer range 0 to 31 := 25;
variable state : integer range 0 to 1 := 0;
variable bitCnt : integer range 0 to 127 := 0;
begin
if(rising_edge (clk)) then
case CommunicationState is
when Waiting =>
obclk <= '1';
obdata <= '1';
resetCRC <= '1';
count := 0;
state := 0;
if start = '1' and startPrev = '0' then
dataToSend <= dataBuf;
dataCRC <= dataBuf;
bitCnt := (conv_integer(cmdBuf(2 downto 0)) * 16) - 1;
CommunicationState <= DataSending;
resetCRC <= '0';
end if;
when DataSending =>
if count < countValue and state = 0 then
if count = 0 then
obdata <= dataToSend(bitCnt);
end if;
count := count + 1;
elsif count = countValue and state = 0 then
obclk <= '0';
count := 0;
state := 1;
elsif count < countValue and state = 1 then
count := count + 1;
elsif count = countValue and state = 1 then
obclk <= '1';
count := 0;
state := 0;
if bitCnt > 0 then
bitCnt := bitCnt - 1;
else
bitCnt := 3;
CommunicationState <= CRCSending;
end if;
end if;
when CRCSending =>
if count < countValue and state = 0 then
if count = 0 then
obdata <= CRC(bitCnt);
end if;
count := count + 1;
elsif count = countValue and state = 0 then
obclk <= '0';
count := 0;
state := 1;
elsif count < countValue and state = 1 then
count := count + 1;
elsif count = countValue and state = 1 then
obclk <= '1';
count := 0;
state := 0;
if bitCnt > 0 then
bitCnt := bitCnt - 1;
else
CommunicationState <= Waiting;
end if;
end if;
when others =>
CommunicationState <= Waiting;
end case;
startPrev <= start;
end if;
end process;
process(clk)
variable lacth : integer range 0 to 1 := 0;
variable bitCnt : integer range -1 to 127 := 0;
begin
if rising_edge(clk) then
if resetCRC = '1' then
bitCnt := (conv_integer(cmdBuf(2 downto 0)) * 16) - 1;
CRC <= x"0";
lacth := 0;
readyCRC <= '0';
else
if readyCRC = '0' then
if lacth = 0 then
if bitCnt /= -1 then
CRC(3) <= CRC(2) xor CRC(3);
CRC(2) <= CRC(1) xor CRC(0);
CRC(1) <= CRC(0);
CRC(0) <= dataCRC(bitCnt) xor CRC(1);
bitCnt := bitCnt - 1;
else
bitCnt := 3;
lacth := 1;
end if;
else
if bitCnt /= -1 then
CRC(3) <= CRC(2) xor CRC(3);
CRC(2) <= CRC(1) xor CRC(0);
CRC(1) <= CRC(0);
CRC(0) <= '1' xor CRC(1);
bitCnt := bitCnt - 1;
else
readyCRC <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
end behavorial;

2
MainController/RAM9X8_SerialBusMaster.vhd
View File

@ -201,7 +201,7 @@ begin
if bitCnt = -1 then
CommunicationState <= TransmitCheck;
else
if count < count and state = 1 then
if count < countValue and state = 1 then
if count = 0 then
sbdataout <= CRC(bitCnt);
sbclk <= '0';