Добавил блок работы с МАЗ, но надо детально проверять состояния автомата. Код переписал, но много путаницы было в проекте для SP2, из-за этого уверености в работе модуля нет.
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@ -176,7 +176,7 @@ applicable agreement for further details.
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@ -189,9 +189,25 @@ applicable agreement for further details.
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@ -204,7 +220,7 @@ applicable agreement for further details.
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@ -728,7 +744,7 @@ applicable agreement for further details.
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@ -1904,6 +1920,186 @@ applicable agreement for further details.
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(parameter
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"REG_ADDR_CMD_2_UPPER_BYTE"
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"44"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_CMD_2_LOWER_BYTE"
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"45"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_CMD_1_UPPER_BYTE"
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"46"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_CMD_1_LOWER_BYTE"
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"47"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_DATA_2_UPPER_BYTE"
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"48"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_DATA_2_LOWER_BYTE"
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"49"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_DATA_1_UPPER_BYTE"
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"50"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"REG_ADDR_DATA_1_LOWER_BYTE"
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"51"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"DATA_BUS_WIDTH"
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"8"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(parameter
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"ADDRESS_BUS_WIDTH"
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"9"
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""
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(pt 0 32)
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(port
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(pt 0 48)
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(input)
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(text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
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(pt 96 32)
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(pt 488 136)
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(pt 488 120)
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@ -2374,14 +2570,6 @@ applicable agreement for further details.
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(pt 1712 16)
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(pt 1712 32)
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(pt 1768 -128)
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@ -2464,40 +2652,19 @@ applicable agreement for further details.
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(pt 1840 -16)
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(pt 1368 -16)
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(pt 1000 288)
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(bus)
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(pt 1000 288)
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(pt 1000 592)
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(bus)
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(pt 984 -80)
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(pt 984 272)
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(pt 984 272)
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||||
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(pt 968 -64)
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||||
(pt 968 256)
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||||
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(pt 952 -48)
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(pt 952 240)
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(connector
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(pt 952 240)
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||||
(pt 952 336)
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@ -2554,6 +2721,183 @@ applicable agreement for further details.
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(pt 1032 32)
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(pt 1032 80)
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)
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(connector
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(pt 608 -360)
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(pt 1000 -344)
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(pt 1040 -344)
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(bus)
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)
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(connector
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(pt 984 -328)
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(pt 1040 -328)
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(pt 1040 -296)
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(connector
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(pt 1000 -344)
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(pt 1000 -96)
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(bus)
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)
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(connector
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(pt 1000 -96)
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(pt 1000 288)
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(bus)
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)
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(connector
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(pt 984 -328)
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(pt 984 -80)
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)
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(connector
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(pt 984 -80)
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||||
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(connector
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(pt 952 -296)
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(pt 952 -48)
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)
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(pt 952 -48)
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||||
(pt 952 240)
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)
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(connector
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(pt 1368 -328)
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(pt 1384 -328)
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)
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(connector
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(pt 1384 -328)
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)
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)
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(connector
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(pt 1528 -608)
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)
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(connector
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(pt 1768 -608)
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(pt 1768 -144)
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)
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(connector
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(pt 1840 -144)
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(pt 1768 -144)
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)
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(connector
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(text "HWPdatain[1..0]" (rect 554 -296 635 -284)(font "Arial" ))
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(pt 544 -280)
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(pt 624 -280)
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(bus)
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)
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(connector
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(text "HWPdata[1..0]" (rect 914 -296 987 -284)(font "Arial" ))
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(pt 1040 -280)
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(pt 904 -280)
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(bus)
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)
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(connector
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(pt 624 -280)
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(pt 624 -176)
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(bus)
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)
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(connector
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(pt 904 -280)
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(pt 904 -176)
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(bus)
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)
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(connector
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(pt 608 -160)
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(pt 704 -160)
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)
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(connector
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(text "HWPdatain[1]" (rect 634 -192 702 -180)(font "Arial" ))
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(pt 624 -176)
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(pt 704 -176)
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)
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(connector
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(pt 608 -160)
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(pt 608 -112)
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)
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(connector
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(text "HWPdata[1]" (rect 842 -192 902 -180)(font "Arial" ))
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(pt 800 -176)
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(pt 904 -176)
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)
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(connector
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||||
(text "HWPdatain[0]" (rect 634 -296 702 -284)(font "Arial" ))
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(pt 624 -280)
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(pt 704 -280)
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)
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(connector
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(pt 608 -264)
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(pt 704 -264)
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)
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(connector
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(pt 608 -360)
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(pt 608 -264)
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)
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(connector
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(pt 608 -264)
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(pt 608 -160)
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)
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(connector
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(text "HWPdata[0]" (rect 842 -296 902 -284)(font "Arial" ))
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(pt 800 -280)
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(pt 904 -280)
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)
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(junction (pt 1000 288))
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(junction (pt 984 304))
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(junction (pt 968 320))
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@ -2591,3 +2935,12 @@ applicable agreement for further details.
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(junction (pt 1768 -112))
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(junction (pt 1712 72))
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(junction (pt 608 -16))
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(junction (pt 1000 -96))
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(junction (pt 984 -80))
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(junction (pt 968 -64))
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(junction (pt 952 -48))
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(junction (pt 608 -360))
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(junction (pt 624 -280))
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(junction (pt 904 -280))
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(junction (pt 608 -160))
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(junction (pt 608 -264))
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@ -303,4 +303,7 @@ set_location_assignment PIN_64 -to Reset
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set_location_assignment PIN_9 -to HWPDATA
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set_location_assignment PIN_6 -to AddrDevice_1
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set_location_assignment PIN_5 -to AddrDevice_2
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set_global_assignment -name VHDL_FILE RAM9X8_HWPBusMaster.vhd
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set_location_assignment PIN_51 -to HWPdatain[0]
|
||||
set_location_assignment PIN_46 -to HWPdatain[1]
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
143
MainController/RAM9X8_HWPBusMaster.bsf
Normal file
143
MainController/RAM9X8_HWPBusMaster.bsf
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2013 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 344 160)
|
||||
(text "RAM9X8_HWPBusMaster" (rect 5 0 118 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "clk" (rect 21 27 31 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address[address_bus_width-1..0]" (rect 0 0 129 12)(font "Arial" ))
|
||||
(text "address[address_bus_width-1..0]" (rect 21 43 150 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "we" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "we" (rect 21 59 31 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "oe" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "oe" (rect 21 75 30 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "ce" (rect 0 0 9 12)(font "Arial" ))
|
||||
(text "ce" (rect 21 91 30 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "hwpdatain[1..0]" (rect 0 0 56 12)(font "Arial" ))
|
||||
(text "hwpdatain[1..0]" (rect 21 107 77 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 328 48)
|
||||
(output)
|
||||
(text "hwpdataout" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "hwpdataout" (rect 264 43 307 55)(font "Arial" ))
|
||||
(line (pt 328 48)(pt 312 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 64)
|
||||
(output)
|
||||
(text "hwpclk" (rect 0 0 25 12)(font "Arial" ))
|
||||
(text "hwpclk" (rect 282 59 307 71)(font "Arial" ))
|
||||
(line (pt 328 64)(pt 312 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 32)
|
||||
(bidir)
|
||||
(text "data[data_bus_width-1..0]" (rect 0 0 99 12)(font "Arial" ))
|
||||
(text "data[data_bus_width-1..0]" (rect 208 27 307 39)(font "Arial" ))
|
||||
(line (pt 328 32)(pt 312 32)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"REG_ADDR_CMD_2_UPPER_BYTE"
|
||||
"44"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_CMD_2_LOWER_BYTE"
|
||||
"45"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_CMD_1_UPPER_BYTE"
|
||||
"46"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_CMD_1_LOWER_BYTE"
|
||||
"47"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_DATA_2_UPPER_BYTE"
|
||||
"48"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_DATA_2_LOWER_BYTE"
|
||||
"49"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_DATA_1_UPPER_BYTE"
|
||||
"50"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"REG_ADDR_DATA_1_LOWER_BYTE"
|
||||
"51"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"DATA_BUS_WIDTH"
|
||||
"8"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"ADDRESS_BUS_WIDTH"
|
||||
"9"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 312 128)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 344 -64 444 16))
|
||||
)
|
||||
207
MainController/RAM9X8_HWPBusMaster.vhd
Normal file
207
MainController/RAM9X8_HWPBusMaster.vhd
Normal file
@ -0,0 +1,207 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity RAM9X8_HWPBusMaster is
|
||||
generic(
|
||||
REG_ADDR_CMD_2_UPPER_BYTE : integer := 44;
|
||||
REG_ADDR_CMD_2_LOWER_BYTE : integer := 45;
|
||||
REG_ADDR_CMD_1_UPPER_BYTE : integer := 46;
|
||||
REG_ADDR_CMD_1_LOWER_BYTE : integer := 47;
|
||||
REG_ADDR_DATA_2_UPPER_BYTE : integer := 48;
|
||||
REG_ADDR_DATA_2_LOWER_BYTE : integer := 49;
|
||||
REG_ADDR_DATA_1_UPPER_BYTE : integer := 50;
|
||||
REG_ADDR_DATA_1_LOWER_BYTE : integer := 51;
|
||||
|
||||
DATA_BUS_WIDTH : integer := 8;
|
||||
ADDRESS_BUS_WIDTH : integer := 9
|
||||
);
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
|
||||
data : inout std_logic_vector(DATA_BUS_WIDTH - 1 downto 0);
|
||||
address : in std_logic_vector(ADDRESS_BUS_WIDTH - 1 downto 0);
|
||||
we : in std_logic;
|
||||
oe : in std_logic;
|
||||
ce : in std_logic;
|
||||
|
||||
hwpdataout : out std_logic;
|
||||
hwpclk : out std_logic;
|
||||
hwpdatain : in std_logic_vector(1 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture behavorial of RAM9X8_HWPBusMaster is
|
||||
|
||||
signal cmdBuf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dataBuf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal tempBuf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dataToSend : std_logic_vector(33 downto 0) := (others => '0');
|
||||
signal cmdBuf_0_prev : std_logic := '0';
|
||||
signal done : std_logic := '1';
|
||||
|
||||
type HWPSt is (Waiting, SendingData, ReceivingData, Checking);
|
||||
signal HWPState : HWPSt := Waiting;
|
||||
|
||||
begin
|
||||
|
||||
process (we, oe, ce)
|
||||
variable addr : integer range 0 to 2**ADDRESS_BUS_WIDTH - 1 := 0;
|
||||
begin
|
||||
if (ce = '0') then -- Если микросхема выбрана
|
||||
addr := conv_integer(address);
|
||||
if (addr = REG_ADDR_CMD_2_UPPER_BYTE or addr = REG_ADDR_CMD_2_LOWER_BYTE or addr = REG_ADDR_CMD_1_UPPER_BYTE or addr = REG_ADDR_CMD_1_LOWER_BYTE
|
||||
or addr = REG_ADDR_DATA_2_UPPER_BYTE or addr = REG_ADDR_DATA_2_LOWER_BYTE or addr = REG_ADDR_DATA_1_UPPER_BYTE or addr = REG_ADDR_DATA_1_LOWER_BYTE) then
|
||||
if (oe = '0' and we = '1') then -- Если сигнал чтения активен, а записи нет
|
||||
case addr is
|
||||
when REG_ADDR_CMD_2_UPPER_BYTE =>
|
||||
data <= cmdBuf(31 downto 24);
|
||||
when REG_ADDR_CMD_2_LOWER_BYTE =>
|
||||
data <= cmdBuf(23 downto 16);
|
||||
when REG_ADDR_CMD_1_UPPER_BYTE =>
|
||||
data <= cmdBuf(15 downto 8);
|
||||
when REG_ADDR_CMD_1_LOWER_BYTE =>
|
||||
data(7 downto 1) <= cmdBuf(7 downto 1);
|
||||
data(0) <= done;
|
||||
when REG_ADDR_DATA_2_UPPER_BYTE =>
|
||||
data <= tempBuf(29 downto 22);
|
||||
when REG_ADDR_DATA_2_LOWER_BYTE =>
|
||||
data <= tempBuf(21 downto 14);
|
||||
when REG_ADDR_DATA_1_UPPER_BYTE =>
|
||||
data <= tempBuf(13 downto 6);
|
||||
when REG_ADDR_DATA_1_LOWER_BYTE =>
|
||||
data(7 downto 2) <= tempBuf(5 downto 0);
|
||||
data(1 downto 0) <= (others => '0');
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
elsif (oe = '1' and we = '0') then -- Если сигнал записи активен, а чтения нет
|
||||
case addr is
|
||||
when REG_ADDR_CMD_2_UPPER_BYTE =>
|
||||
cmdBuf(31 downto 24) <= data;
|
||||
when REG_ADDR_CMD_2_LOWER_BYTE =>
|
||||
cmdBuf(23 downto 16) <= data;
|
||||
when REG_ADDR_CMD_1_UPPER_BYTE =>
|
||||
cmdBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_CMD_1_LOWER_BYTE =>
|
||||
cmdBuf(7 downto 0) <= data;
|
||||
when REG_ADDR_DATA_2_UPPER_BYTE =>
|
||||
dataBuf(31 downto 24) <= data;
|
||||
when REG_ADDR_DATA_2_LOWER_BYTE =>
|
||||
dataBuf(23 downto 16) <= data;
|
||||
when REG_ADDR_DATA_1_UPPER_BYTE =>
|
||||
dataBuf(15 downto 8) <= data;
|
||||
when REG_ADDR_DATA_1_LOWER_BYTE =>
|
||||
dataBuf(7 downto 0) <= data;
|
||||
when others =>
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end case;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
else
|
||||
data <= (others => 'Z'); -- Запретить запись на шину
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk) is
|
||||
variable count : integer range 0 to 511 := 0;
|
||||
variable state : integer range 0 to 1 := 0;
|
||||
variable countBit : integer range 0 to 32 := 0;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case HWPState is
|
||||
when Waiting =>
|
||||
if cmdBuf(0) = '1' and cmdBuf_0_prev = '0' then
|
||||
done <= '1';
|
||||
if cmdBuf(14) = '0' then
|
||||
if cmdBuf(13) = '0' then
|
||||
dataToSend(33 downto 22) <= (others => '0');
|
||||
dataToSend(21 downto 16) <= cmdBuf(15 downto 10);
|
||||
dataToSend(15 downto 0) <= cmdBuf(31 downto 16);
|
||||
countBit := 21;
|
||||
else
|
||||
dataToSend(33) <= '0';
|
||||
dataToSend(32 downto 30) <= cmdBuf(15 downto 13);
|
||||
dataToSend(29 downto 0) <= dataBuf(31 downto 2);
|
||||
countBit := 32;
|
||||
end if;
|
||||
else
|
||||
dataToSend(33) <= '1';
|
||||
dataToSend(32 downto 2) <= (others => '0');
|
||||
dataToSend(1 downto 0) <= cmdBuf(15 downto 14);
|
||||
countBit := 1;
|
||||
end if;
|
||||
HWPState <= SendingData;
|
||||
count := 0;
|
||||
state := 0;
|
||||
end if;
|
||||
when SendingData =>
|
||||
if count < 511 and state = 0 then
|
||||
if count = 0 then
|
||||
hwpdataout <= dataToSend(countBit);
|
||||
end if;
|
||||
count := count + 1;
|
||||
elsif count = 511 and state = 0 then
|
||||
hwpclk <= '0';
|
||||
count := 0;
|
||||
state := 1;
|
||||
elsif count < 511 and state = 1 then
|
||||
count := count + 1;
|
||||
elsif count = 511 and state = 1 then
|
||||
hwpclk <= '1';
|
||||
count := 0;
|
||||
state := 0;
|
||||
if countBit > 0 then
|
||||
countBit := countBit - 1;
|
||||
else
|
||||
if dataToSend(33) = '1' then
|
||||
HWPState <= ReceivingData;
|
||||
countBit := 29;
|
||||
else
|
||||
HWPState <= Checking;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when ReceivingData =>
|
||||
if count < 511 and state = 0 then
|
||||
count := count + 1;
|
||||
elsif count = 511 and state = 0 then
|
||||
hwpclk <= '0';
|
||||
count := 0;
|
||||
state := 1;
|
||||
if dataToSend(1) = '0' then
|
||||
tempBuf(countBit) <= hwpdatain(0);
|
||||
hwpdataout <= hwpdatain(0);
|
||||
else
|
||||
tempBuf(countBit) <= hwpdatain(1);
|
||||
hwpdataout <= hwpdatain(1);
|
||||
end if;
|
||||
elsif count < 511 and state = 1 then
|
||||
count := count + 1;
|
||||
elsif count = 511 and state = 1 then
|
||||
hwpclk <= '1';
|
||||
count := 0;
|
||||
state := 0;
|
||||
if countBit > 0 then
|
||||
countBit := countBit - 1;
|
||||
else
|
||||
HWPState <= Checking;
|
||||
end if;
|
||||
end if;
|
||||
when Checking =>
|
||||
done <= '0';
|
||||
HWPState <= Waiting;
|
||||
when others =>
|
||||
HWPState <= Waiting;
|
||||
end case;
|
||||
cmdBuf_0_prev <= cmdBuf(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavorial;
|
||||
Loading…
Reference in New Issue
Block a user