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Для согласования работы с процессором было принято решение перейти на питание ПЛИС 3.3В. Внесли изменения в проект.

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sokolovstanislav 2024-03-12 16:30:45 +03:00
parent 6bb13aec36
commit 71cbaf57d8
48 changed files with 16014 additions and 424 deletions
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43
MainController/LedBlink.bsf Normal file
View File

@ -0,0 +1,43 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 136 96)
(text "LedBlink" (rect 5 0 38 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 120 32)
(output)
(text "led" (rect 0 0 10 12)(font "Arial" ))
(text "led" (rect 89 27 99 39)(font "Arial" ))
(line (pt 120 32)(pt 104 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 104 64)(line_width 1))
)
)

31
MainController/LedBlink.vhd Normal file
View File

@ -0,0 +1,31 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LedBlink is
Port (
clk : in STD_LOGIC;
led : out STD_LOGIC
);
end LedBlink;
architecture Behavioral of LedBlink is
signal counter : natural range 0 to 16666667 := 0;
signal ledBuf : STD_LOGIC := '1';
begin
process(clk)
begin
if rising_edge(clk) then
if counter < 16666667 then
counter <= counter + 1;
else
counter <= 0;
ledBuf <= not ledBuf;
end if;
end if;
end process;
led <= ledBuf;
end Behavioral;

263
MainController/MainController.bdf
View File

@ -19,43 +19,11 @@ Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 376 248 544 264)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "WR" (rect 5 0 23 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 376 216 544 232)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "Address[7..0]" (rect 5 0 72 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 376 264 544 280)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "Clk" (rect 5 0 22 12)(font "Arial" ))
(text "Address[7..0]" (rect 5 0 71 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
@ -66,12 +34,13 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 264 104 320 216))
)
(pin
(input)
(rect 376 144 544 160)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "Clk50MHh" (rect 5 0 56 12)(font "Arial" ))
(text "FPGA_CLK" (rect 5 0 61 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
@ -82,12 +51,81 @@ applicable agreement for further details.
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 328 144 376 160))
)
(pin
(input)
(rect 376 248 544 264)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "nOE" (rect 5 0 26 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 248 376 264))
)
(pin
(input)
(rect 376 264 544 280)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "nWE" (rect 5 0 28 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 264 376 280))
)
(pin
(input)
(rect 376 280 544 296)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "nCE" (rect 5 0 26 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 320 280 376 296))
)
(pin
(output)
(rect 1144 40 1320 56)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 1320 40 1376 56))
)
(pin
(bidir)
(rect 368 232 544 248)
(text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6)))
(text "Data[15..0]" (rect 5 0 61 12)(font "Arial" ))
(text "Data[7..0]" (rect 5 0 54 12)(font "Arial" ))
(pt 176 8)
(drawing
(line (pt 120 4)(pt 98 4))
@ -100,6 +138,7 @@ applicable agreement for further details.
)
(flipy)
(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 200 120 256 232))
)
(symbol
(rect 632 104 784 216)
@ -145,9 +184,9 @@ applicable agreement for further details.
)
)
(symbol
(rect 848 160 1048 304)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst1" (rect 24 128 47 140)(font "Arial" ))
(rect 632 16 752 96)
(text "LedBlink" (rect 5 0 46 12)(font "Arial" ))
(text "inst2" (rect 8 64 31 76)(font "Arial" ))
(port
(pt 0 32)
(input)
@ -156,63 +195,85 @@ applicable agreement for further details.
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 64)
(pt 120 32)
(output)
(text "led" (rect 0 0 14 12)(font "Arial" ))
(text "led" (rect 88 27 102 39)(font "Arial" ))
(line (pt 120 32)(pt 104 32))
)
(drawing
(rectangle (rect 16 16 104 64))
)
)
(symbol
(rect 952 176 1152 352)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst1" (rect 8 160 31 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "address0[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address0[7..0]" (rect 24 56 94 68)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
(text "address0[7..0]" (rect 21 43 91 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wr0" (rect 0 0 16 12)(font "Arial" ))
(text "wr0" (rect 21 59 37 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "clk0" (rect 0 0 20 12)(font "Arial" ))
(text "clk0" (rect 21 75 41 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "wr0" (rect 0 0 16 12)(font "Arial" ))
(text "wr0" (rect 24 88 40 100)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 91 91 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "clk0" (rect 0 0 20 12)(font "Arial" ))
(text "clk0" (rect 24 104 44 116)(font "Arial" ))
(text "wr1" (rect 0 0 16 12)(font "Arial" ))
(text "wr1" (rect 21 107 37 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 200 64)
(input)
(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address1[7..0]" (rect 120 56 190 68)(font "Arial" ))
(line (pt 184 64)(pt 200 64)(line_width 3))
)
(port
(pt 200 96)
(input)
(text "wr1" (rect 0 0 16 12)(font "Arial" ))
(text "wr1" (rect 160 88 176 100)(font "Arial" ))
(line (pt 184 96)(pt 200 96))
)
(port
(pt 200 112)
(pt 0 128)
(input)
(text "clk1" (rect 0 0 20 12)(font "Arial" ))
(text "clk1" (rect 160 104 180 116)(font "Arial" ))
(line (pt 184 112)(pt 200 112))
(text "clk1" (rect 21 123 41 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 80)
(pt 200 32)
(bidir)
(text "data0[15..0]" (rect 0 0 59 12)(font "Arial" ))
(text "data0[15..0]" (rect 24 72 83 84)(font "Arial" ))
(line (pt 16 80)(pt 0 80)(line_width 3))
(text "data0[7..0]" (rect 0 0 53 12)(font "Arial" ))
(text "data0[7..0]" (rect 138 27 191 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(port
(pt 200 80)
(pt 200 48)
(bidir)
(text "data1[15..0]" (rect 0 0 59 12)(font "Arial" ))
(text "data1[15..0]" (rect 128 72 187 84)(font "Arial" ))
(line (pt 200 80)(pt 184 80)(line_width 3))
(text "data1[7..0]" (rect 0 0 53 12)(font "Arial" ))
(text "data1[7..0]" (rect 139 43 192 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 184 128))
(rectangle (rect 16 16 184 160))
)
)
(connector
@ -229,10 +290,6 @@ applicable agreement for further details.
(pt 592 624)
(bus)
)
(connector
(pt 608 152)
(pt 608 624)
)
(connector
(pt 544 152)
(pt 608 152)
@ -257,6 +314,30 @@ applicable agreement for further details.
(pt 544 272)
(pt 848 272)
)
(connector
(pt 544 256)
(pt 560 256)
)
(connector
(pt 560 256)
(pt 848 256)
)
(connector
(pt 608 48)
(pt 608 152)
)
(connector
(pt 608 152)
(pt 608 624)
)
(connector
(pt 608 48)
(pt 632 48)
)
(connector
(pt 752 48)
(pt 1144 48)
)
(connector
(pt 544 224)
(pt 592 224)
@ -264,7 +345,12 @@ applicable agreement for further details.
)
(connector
(pt 592 224)
(pt 848 224)
(pt 952 224)
(bus)
)
(connector
(pt 936 240)
(pt 936 160)
(bus)
)
(connector
@ -274,18 +360,29 @@ applicable agreement for further details.
)
(connector
(pt 576 240)
(pt 848 240)
(pt 936 240)
(bus)
)
(connector
(pt 544 256)
(pt 560 256)
(pt 936 160)
(pt 1168 160)
(bus)
)
(connector
(pt 560 256)
(pt 848 256)
(pt 1168 160)
(pt 1168 208)
(bus)
)
(connector
(pt 1168 208)
(pt 1152 208)
(bus)
)
(connector
(pt 544 288)
(pt 848 288)
)
(junction (pt 608 152))
(junction (pt 592 224))
(junction (pt 576 240))
(junction (pt 560 256))
(junction (pt 576 240))

44
MainController/MainController.qsf
View File

@ -55,4 +55,48 @@ set_global_assignment -name VHDL_FILE RAM.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE LedBlink.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_166 -to FPGA_LED_1
set_location_assignment PIN_224 -to Data[5]
set_location_assignment PIN_223 -to Data[6]
set_location_assignment PIN_226 -to Data[4]
set_location_assignment PIN_230 -to Address[6]
set_location_assignment PIN_231 -to Address[1]
set_location_assignment PIN_232 -to Address[4]
set_location_assignment PIN_233 -to Address[3]
set_location_assignment PIN_234 -to Address[2]
set_location_assignment PIN_235 -to Address[5]
set_location_assignment PIN_221 -to Data[7]
set_location_assignment PIN_196 -to Address[0]
set_location_assignment PIN_195 -to Address[7]
set_location_assignment PIN_194 -to Data[0]
set_location_assignment PIN_189 -to Data[1]
set_location_assignment PIN_188 -to Data[2]
set_location_assignment PIN_187 -to Data[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nOE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nWE
set_location_assignment PIN_217 -to nOE
set_location_assignment PIN_218 -to nWE
set_location_assignment PIN_219 -to nCE
set_location_assignment PIN_31 -to FPGA_CLK
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

86
MainController/RAM.bsf
View File

@ -18,75 +18,75 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 64 64 264 208)
(text "RAM" (rect 5 0 28 12)(font "Arial" ))
(text "inst" (rect 24 128 41 140)(font "Arial" ))
(rect 16 16 216 192)
(text "RAM" (rect 5 0 29 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 27 31 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "address0[7..0]" (rect 0 0 56 12)(font "Arial" ))
(text "address0[7..0]" (rect 21 43 77 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "address0[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address0[7..0]" (rect 24 56 94 68)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
(text "wr0" (rect 0 0 14 12)(font "Arial" ))
(text "wr0" (rect 21 59 35 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "clk0" (rect 0 0 15 12)(font "Arial" ))
(text "clk0" (rect 21 75 36 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "wr0" (rect 0 0 16 12)(font "Arial" ))
(text "wr0" (rect 24 88 40 100)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
(text "address1[7..0]" (rect 21 91 76 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "clk0" (rect 0 0 20 12)(font "Arial" ))
(text "clk0" (rect 24 104 44 116)(font "Arial" ))
(line (pt 0 112)(pt 16 112))
(text "wr1" (rect 0 0 12 12)(font "Arial" ))
(text "wr1" (rect 21 107 33 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 200 64)
(pt 0 128)
(input)
(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
(text "address1[7..0]" (rect 120 56 190 68)(font "Arial" ))
(line (pt 184 64)(pt 200 64)(line_width 3))
(text "clk1" (rect 0 0 14 12)(font "Arial" ))
(text "clk1" (rect 21 123 35 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 200 96)
(input)
(text "wr1" (rect 0 0 16 12)(font "Arial" ))
(text "wr1" (rect 160 88 176 100)(font "Arial" ))
(line (pt 184 96)(pt 200 96))
)
(port
(pt 200 112)
(input)
(text "clk1" (rect 0 0 20 12)(font "Arial" ))
(text "clk1" (rect 160 104 180 116)(font "Arial" ))
(line (pt 184 112)(pt 200 112))
)
(port
(pt 0 80)
(pt 200 32)
(bidir)
(text "data0[15..0]" (rect 0 0 59 12)(font "Arial" ))
(text "data0[15..0]" (rect 24 72 83 84)(font "Arial" ))
(line (pt 16 80)(pt 0 80)(line_width 3))
(text "data0[7..0]" (rect 0 0 41 12)(font "Arial" ))
(text "data0[7..0]" (rect 138 27 179 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(port
(pt 200 80)
(pt 200 48)
(bidir)
(text "data1[15..0]" (rect 0 0 59 12)(font "Arial" ))
(text "data1[15..0]" (rect 128 72 187 84)(font "Arial" ))
(line (pt 200 80)(pt 184 80)(line_width 3))
(text "data1[7..0]" (rect 0 0 40 12)(font "Arial" ))
(text "data1[7..0]" (rect 139 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 184 128))
(rectangle (rect 16 16 184 160)(line_width 1))
)
)

6
MainController/RAM.vhd
View File

@ -8,12 +8,12 @@ entity RAM is
port(
clk : in std_logic;
data0 : inout std_logic_vector(15 downto 0);
data0 : inout std_logic_vector(7 downto 0);
address0 : in std_logic_vector(7 downto 0);
wr0 : in std_logic;
clk0 : in std_logic;
data1 : inout std_logic_vector(15 downto 0);
data1 : inout std_logic_vector(7 downto 0);
address1 : in std_logic_vector(7 downto 0);
wr1 : in std_logic;
clk1 : in std_logic
@ -22,7 +22,7 @@ end entity;
architecture behavorial of RAM is
type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
type mem is array (255 downto 0) of std_logic_vector(7 downto 0);
signal memory : mem;
signal clk0Prev : std_logic := '0';

66
MainController/greybox_tmp/cbx_args.txt Normal file
View File

@ -0,0 +1,66 @@
BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=1
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=4
CLK0_PHASE_SHIFT=0
CLK1_DIVIDE_BY=1
CLK1_DUTY_CYCLE=50
CLK1_MULTIPLY_BY=8
CLK1_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=40000
INTENDED_DEVICE_FAMILY="Cyclone III"
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_USED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_USED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_USED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
SELF_RESET_ON_LOSS_LOCK=OFF
WIDTH_CLOCK=5
DEVICE_FAMILY="Cyclone III"
CBX_AUTO_BLACKBOX=ALL
areset
inclk
inclk
clk
clk
locked

11
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
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Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Version_Index = 318808576
Creation_Time = Mon Mar 04 15:47:51 2024

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v1

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d1187c24d5e18b5b14f48701f0f8928b

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Assembler report for MainController
Tue Mar 12 16:24:24 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/GITEA/altera/MainController/output_files/MainController.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Mar 12 16:24:24 2024 ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Device ; EP3C25Q240C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+----------------------------------------------------------------+
; Assembler Generated Files ;
+----------------------------------------------------------------+
; File Name ;
+----------------------------------------------------------------+
; D:/GITEA/altera/MainController/output_files/MainController.sof ;
+----------------------------------------------------------------+
+------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/GITEA/altera/MainController/output_files/MainController.sof ;
+----------------+-------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------------------------------------------+
; Device ; EP3C25Q240C8 ;
; JTAG usercode ; 0x0013959E ;
; Checksum ; 0x0013959E ;
+----------------+-------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Tue Mar 12 16:24:23 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off MainController -c MainController
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4610 megabytes
Info: Processing ended: Tue Mar 12 16:24:24 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

1
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Tue Mar 12 16:24:29 2024

107
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EDA Netlist Writer report for MainController
Tue Mar 12 16:24:29 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Mar 12 16:24:29 2024 ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Tool Name ; ModelSim-Altera (VHDL) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------+
+----------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+----------------------------------------------------------------------------------------------+
; Generated Files ;
+----------------------------------------------------------------------------------------------+
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController.vho ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo ;
; D:/GITEA/altera/MainController/simulation/modelsim/MainController_vhd.sdo ;
+----------------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Tue Mar 12 16:24:28 2024
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController
Info (204019): Generated file MainController_8_1200mv_85c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_8_1200mv_0c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_min_1200mv_0c_fast.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_8_1200mv_85c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_8_1200mv_0c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_min_1200mv_0c_vhd_fast.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file MainController_vhd.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4567 megabytes
Info: Processing ended: Tue Mar 12 16:24:29 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

1192
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8
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
MainController/output_files/MainController.fit.summary Normal file
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Fitter Status : Successful - Tue Mar 12 16:24:21 2024
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : MainController
Top-level Entity Name : MainController
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 34 / 24,624 ( < 1 % )
Total combinational functions : 34 / 24,624 ( < 1 % )
Dedicated logic registers : 25 / 24,624 ( < 1 % )
Total registers : 25
Total pins : 21 / 149 ( 14 % )
Total virtual pins : 0
Total memory bits : 0 / 608,256 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

132
MainController/output_files/MainController.flow.rpt Normal file
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Flow report for MainController
Tue Mar 12 16:24:29 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Tue Mar 12 16:24:29 2024 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; MainController ;
; Top-level Entity Name ; MainController ;
; Family ; Cyclone III ;
; Device ; EP3C25Q240C8 ;
; Timing Models ; Final ;
; Total logic elements ; 34 / 24,624 ( < 1 % ) ;
; Total combinational functions ; 34 / 24,624 ( < 1 % ) ;
; Dedicated logic registers ; 25 / 24,624 ( < 1 % ) ;
; Total registers ; 25 ;
; Total pins ; 21 / 149 ( 14 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/12/2024 16:24:14 ;
; Main task ; Compilation ;
; Revision Name ; MainController ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 30902508249626.171024985402028 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; AlteraPLL.cmp ; -- ; -- ; -- ;
; MISC_FILE ; AlteraPLL.ppf ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4707 MB ; 00:00:02 ;
; Fitter ; 00:00:04 ; 1.0 ; 5391 MB ; 00:00:06 ;
; Assembler ; 00:00:01 ; 1.0 ; 4590 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4700 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4550 MB ; 00:00:01 ;
; Total ; 00:00:09 ; -- ; -- ; 00:00:11 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; STAS-W10 ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; STAS-W10 ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; STAS-W10 ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; STAS-W10 ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; STAS-W10 ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController
quartus_fit --read_settings_files=off --write_settings_files=off MainController -c MainController
quartus_asm --read_settings_files=off --write_settings_files=off MainController -c MainController
quartus_sta MainController -c MainController
quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController

8
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<sld_project_info>
<project>
<hash md5_digest_80b="9c3406557f2dade88a26"/>
</project>
<file_info>
<file device="EP3C25Q240C8" path="MainController.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

2372
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Analysis & Synthesis Status : Successful - Tue Mar 12 16:24:16 2024
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : MainController
Top-level Entity Name : MainController
Family : Cyclone III
Total logic elements : 34
Total combinational functions : 34
Dedicated logic registers : 25
Total registers : 25
Total pins : 21
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

310
MainController/output_files/MainController.pin Normal file
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-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
CHIP "MainController" ASSIGNED TO AN: EP3C25Q240C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCD_PLL3 : 1 : power : : 1.2V : :
GNDA3 : 2 : gnd : : : :
VCCA3 : 3 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
GND : 8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 9 : : : : 1 :
VCCINT : 10 : power : : 1.2V : :
GND : 11 : gnd : : : :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 12 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : : : : 1 :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 14 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 15 : power : : 3.3V : 1 :
GND : 16 : gnd : : : :
nSTATUS : 17 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 18 : : : : 1 :
VCCINT : 19 : power : : 1.2V : :
GND : 20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 21 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 22 : : : : 1 :
~ALTERA_DCLK~ : 23 : output : 3.3-V LVTTL : : 1 : N
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : input : 3.3-V LVTTL : : 1 : N
nCONFIG : 25 : : : : 1 :
TDI : 26 : input : : : 1 :
TCK : 27 : input : : : 1 :
TMS : 28 : input : : : 1 :
TDO : 29 : output : : : 1 :
nCE : 30 : : : : 1 :
FPGA_CLK : 31 : input : 3.3-V LVTTL : : 1 : Y
GND+ : 32 : : : : 1 :
GND+ : 33 : : : : 2 :
GND+ : 34 : : : : 2 :
VCCIO2 : 35 : power : : 2.5V : 2 :
GND : 36 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 37 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 2 :
VCCINT : 40 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 41 : : : : 2 :
GND : 42 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 45 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 2 :
VCCIO2 : 47 : power : : 2.5V : 2 :
GND : 48 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 2 :
VCCINT : 53 : power : : 1.2V : :
GND : 54 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 56 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 57 : : : : 2 :
VCCA1 : 58 : power : : 2.5V : :
GNDA1 : 59 : gnd : : : :
VCCD_PLL1 : 60 : power : : 1.2V : :
VCCINT : 61 : power : : 1.2V : :
GND : 62 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 63 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 3 :
VCCIO3 : 66 : power : : 2.5V : 3 :
GND : 67 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 3 :
VCCINT : 74 : power : : 1.2V : :
GND : 75 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 3 :
VCCIO3 : 77 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 78 : : : : 3 :
GND : 79 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 81 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 82 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 3 :
VCCINT : 85 : power : : 1.2V : :
GND : 86 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 88 : : : : 3 :
GND+ : 89 : : : : 3 :
GND+ : 90 : : : : 3 :
GND+ : 91 : : : : 4 :
GND+ : 92 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 93 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 94 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 95 : : : : 4 :
VCCIO4 : 96 : power : : 2.5V : 4 :
GND : 97 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 4 :
VCCINT : 101 : power : : 1.2V : :
GND : 102 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 4 :
VCCIO4 : 104 : power : : 2.5V : 4 :
GND : 105 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 107 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 108 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 109 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 4 :
VCCINT : 115 : power : : 1.2V : :
GND : 116 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 117 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 118 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 120 : : : : 4 :
VCCD_PLL4 : 121 : power : : 1.2V : :
GNDA4 : 122 : gnd : : : :
VCCA4 : 123 : power : : 2.5V : :
VCCIO5 : 124 : power : : 2.5V : 5 :
GND : 125 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 5 :
VCCINT : 129 : power : : 1.2V : :
GND : 130 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 131 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 134 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 5 :
VCCIO5 : 136 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 5 :
GND : 138 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 139 : : : : 5 :
VCCINT : 140 : power : : 1.2V : :
GND : 141 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 145 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 146 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 147 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 148 : : : : 5 :
GND+ : 149 : : : : 5 :
GND+ : 150 : : : : 5 :
GND+ : 151 : : : : 6 :
GND+ : 152 : : : : 6 :
CONF_DONE : 153 : : : : 6 :
VCCIO6 : 154 : power : : 3.3V : 6 :
MSEL0 : 155 : : : : 6 :
GND : 156 : gnd : : : :
MSEL1 : 157 : : : : 6 :
MSEL2 : 158 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 159 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 160 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 161 : : : : 6 :
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 162 : output : 3.3-V LVTTL : : 6 : N
VCCINT : 163 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 164 : : : : 6 :
GND : 165 : gnd : : : :
FPGA_LED_1 : 166 : output : 3.3-V LVTTL : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 167 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 168 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 169 : : : : 6 :
VCCIO6 : 170 : power : : 3.3V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 171 : : : : 6 :
GND : 172 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 173 : : : : 6 :
VCCINT : 174 : power : : 1.2V : :
GND : 175 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 176 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 177 : : : : 6 :
VCCA2 : 178 : power : : 2.5V : :
GNDA2 : 179 : gnd : : : :
VCCD_PLL2 : 180 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 181 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 182 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 183 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 184 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 185 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 186 : : : : 7 :
Data[3] : 187 : bidir : 3.3-V LVTTL : : 7 : Y
Data[2] : 188 : bidir : 3.3-V LVTTL : : 7 : Y
Data[1] : 189 : bidir : 3.3-V LVTTL : : 7 : Y
VCCINT : 190 : power : : 1.2V : :
GND : 191 : gnd : : : :
VCCIO7 : 192 : power : : 3.3V : 7 :
GND : 193 : gnd : : : :
Data[0] : 194 : bidir : 3.3-V LVTTL : : 7 : Y
Address[7] : 195 : input : 3.3-V LVTTL : : 7 : Y
Address[0] : 196 : input : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 197 : : : : 7 :
VCCINT : 198 : power : : 1.2V : :
GND : 199 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 200 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 201 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 202 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 203 : : : : 7 :
VCCINT : 204 : power : : 1.2V : :
GND : 205 : gnd : : : :
VCCIO7 : 206 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 207 : : : : 7 :
GND : 208 : gnd : : : :
GND+ : 209 : : : : 7 :
GND+ : 210 : : : : 7 :
GND+ : 211 : : : : 8 :
GND+ : 212 : : : : 8 :
VCCIO8 : 213 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 214 : : : : 8 :
GND : 215 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 216 : : : : 8 :
nOE : 217 : input : 3.3-V LVTTL : : 8 : Y
nWE : 218 : input : 3.3-V LVTTL : : 8 : Y
nCE : 219 : input : 3.3-V LVTTL : : 8 : Y
VCCINT : 220 : power : : 1.2V : :
Data[7] : 221 : bidir : 3.3-V LVTTL : : 8 : Y
GND : 222 : gnd : : : :
Data[6] : 223 : bidir : 3.3-V LVTTL : : 8 : Y
Data[5] : 224 : bidir : 3.3-V LVTTL : : 8 : Y
VCCIO8 : 225 : power : : 3.3V : 8 :
Data[4] : 226 : bidir : 3.3-V LVTTL : : 8 : Y
GND : 227 : gnd : : : :
VCCINT : 228 : power : : 1.2V : :
GND : 229 : gnd : : : :
Address[6] : 230 : input : 3.3-V LVTTL : : 8 : Y
Address[1] : 231 : input : 3.3-V LVTTL : : 8 : Y
Address[4] : 232 : input : 3.3-V LVTTL : : 8 : Y
Address[3] : 233 : input : 3.3-V LVTTL : : 8 : Y
Address[2] : 234 : input : 3.3-V LVTTL : : 8 : Y
Address[5] : 235 : input : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 236 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 237 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 238 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 239 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 240 : : : : 8 :

BIN
MainController/output_files/MainController.sof Normal file
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1558
MainController/output_files/MainController.sta.rpt Normal file
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MainController/output_files/MainController.sta.summary Normal file
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'FPGA_CLK'
Slack : -3.954
TNS : -84.790
Type : Slow 1200mV 85C Model Hold 'FPGA_CLK'
Slack : 0.435
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'FPGA_CLK'
Slack : -3.000
TNS : -40.175
Type : Slow 1200mV 0C Model Setup 'FPGA_CLK'
Slack : -3.662
TNS : -77.889
Type : Slow 1200mV 0C Model Hold 'FPGA_CLK'
Slack : 0.384
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
Slack : -3.000
TNS : -40.175
Type : Fast 1200mV 0C Model Setup 'FPGA_CLK'
Slack : -1.072
TNS : -20.939
Type : Fast 1200mV 0C Model Hold 'FPGA_CLK'
Slack : 0.179
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
Slack : -3.000
TNS : -35.949
------------------------------------------------------------

6
MainController/simulation/modelsim/MainController.sft Normal file
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set tool_name "ModelSim-Altera (VHDL)"
set corner_file_list {
{{"Slow -8 1.2V 85 Model"} {MainController_8_1200mv_85c_slow.vho MainController_8_1200mv_85c_vhd_slow.sdo}}
{{"Slow -8 1.2V 0 Model"} {MainController_8_1200mv_0c_slow.vho MainController_8_1200mv_0c_vhd_slow.sdo}}
{{"Fast -M 1.2V 0 Model"} {MainController_min_1200mv_0c_fast.vho MainController_min_1200mv_0c_vhd_fast.sdo}}
}

1520
MainController/simulation/modelsim/MainController.vho
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MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho Normal file
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MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo Normal file
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@ -0,0 +1,949 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP3C25Q240C8 Package PQFP240
//
//
// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "MainController")
(DATE "03/12/2024 16:24:29")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiii_io_obuf")
(INSTANCE \\FPGA_LED_1\~output\\)
(DELAY
(ABSOLUTE
(PORT i (1277:1277:1277) (1446:1446:1446))
(IOPATH i o (2195:2195:2195) (2297:2297:2297))
)
)
)
(CELL
(CELLTYPE "cycloneiii_io_ibuf")
(INSTANCE \\FPGA_CLK\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (899:899:899) (1014:1014:1014))
)
)
)
(CELL
(CELLTYPE "cycloneiii_clkctrl")
(INSTANCE \\FPGA_CLK\~inputclkctrl\\)
(DELAY
(ABSOLUTE
(PORT inclk[0] (166:166:166) (162:162:162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[0\]\~24\\)
(DELAY
(ABSOLUTE
(PORT dataa (553:553:553) (536:536:536))
(IOPATH dataa combout (435:435:435) (425:425:425))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[0\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[1\]\~26\\)
(DELAY
(ABSOLUTE
(PORT datab (558:558:558) (530:530:530))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[1\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[2\]\~28\\)
(DELAY
(ABSOLUTE
(PORT datab (548:548:548) (534:534:534))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[2\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[3\]\~30\\)
(DELAY
(ABSOLUTE
(PORT datab (326:326:326) (383:383:383))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[3\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2182:2182:2182) (2152:2152:2152))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[4\]\~32\\)
(DELAY
(ABSOLUTE
(PORT dataa (568:568:568) (551:551:551))
(IOPATH dataa combout (435:435:435) (425:425:425))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[4\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[5\]\~34\\)
(DELAY
(ABSOLUTE
(PORT datab (326:326:326) (383:383:383))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[5\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[6\]\~36\\)
(DELAY
(ABSOLUTE
(PORT datab (326:326:326) (384:384:384))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[6\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2182:2182:2182) (2152:2152:2152))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[7\]\~38\\)
(DELAY
(ABSOLUTE
(PORT datab (548:548:548) (530:530:530))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[7\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[8\]\~40\\)
(DELAY
(ABSOLUTE
(PORT datab (325:325:325) (382:382:382))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[8\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[9\]\~42\\)
(DELAY
(ABSOLUTE
(PORT dataa (328:328:328) (392:392:392))
(IOPATH dataa combout (414:414:414) (444:444:444))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[9\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1712:1712:1712) (1732:1732:1732))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[10\]\~44\\)
(DELAY
(ABSOLUTE
(PORT datab (324:324:324) (381:381:381))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[10\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2182:2182:2182) (2152:2152:2152))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[11\]\~46\\)
(DELAY
(ABSOLUTE
(PORT dataa (328:328:328) (392:392:392))
(IOPATH dataa combout (414:414:414) (444:444:444))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[11\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2182:2182:2182) (2152:2152:2152))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (1344:1344:1344) (1536:1536:1536))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[12\]\~48\\)
(DELAY
(ABSOLUTE
(PORT datab (323:323:323) (381:381:381))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[12\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[13\]\~50\\)
(DELAY
(ABSOLUTE
(PORT datab (338:338:338) (392:392:392))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[13\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[14\]\~52\\)
(DELAY
(ABSOLUTE
(PORT datab (339:339:339) (393:393:393))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[14\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[15\]\~54\\)
(DELAY
(ABSOLUTE
(PORT dataa (351:351:351) (414:414:414))
(IOPATH dataa combout (414:414:414) (444:444:444))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[15\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1711:1711:1711) (1731:1731:1731))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[16\]\~56\\)
(DELAY
(ABSOLUTE
(PORT datab (340:340:340) (394:394:394))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[16\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1711:1711:1711) (1731:1731:1731))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[17\]\~58\\)
(DELAY
(ABSOLUTE
(PORT dataa (343:343:343) (403:403:403))
(IOPATH dataa combout (414:414:414) (444:444:444))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[17\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1711:1711:1711) (1731:1731:1731))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (880:880:880) (761:761:761))
(PORT datab (618:618:618) (575:575:575))
(PORT datac (513:513:513) (507:507:507))
(PORT datad (552:552:552) (524:524:524))
(IOPATH dataa combout (392:392:392) (419:419:419))
(IOPATH datab combout (393:393:393) (431:431:431))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[18\]\~60\\)
(DELAY
(ABSOLUTE
(PORT dataa (330:330:330) (394:394:394))
(IOPATH dataa combout (435:435:435) (425:425:425))
(IOPATH dataa cout (486:486:486) (375:375:375))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[18\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1711:1711:1711) (1731:1731:1731))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[19\]\~62\\)
(DELAY
(ABSOLUTE
(PORT datab (327:327:327) (384:384:384))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[19\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[20\]\~64\\)
(DELAY
(ABSOLUTE
(PORT datab (328:328:328) (384:384:384))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[20\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[21\]\~66\\)
(DELAY
(ABSOLUTE
(PORT datab (326:326:326) (384:384:384))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[21\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[22\]\~68\\)
(DELAY
(ABSOLUTE
(PORT datab (328:328:328) (386:386:386))
(IOPATH datab combout (437:437:437) (425:425:425))
(IOPATH datab cout (497:497:497) (381:381:381))
(IOPATH datad combout (167:167:167) (143:143:143))
(IOPATH cin combout (549:549:549) (519:519:519))
(IOPATH cin cout (63:63:63) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[22\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[23\]\~70\\)
(DELAY
(ABSOLUTE
(PORT dataa (808:808:808) (716:716:716))
(IOPATH dataa combout (435:435:435) (444:444:444))
(IOPATH cin combout (549:549:549) (519:519:519))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[23\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(PORT sclr (884:884:884) (924:924:924))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
(HOLD sclr (posedge clk) (195:195:195))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~1\\)
(DELAY
(ABSOLUTE
(PORT dataa (329:329:329) (393:393:393))
(PORT datab (326:326:326) (383:383:383))
(PORT datac (283:283:283) (349:349:349))
(PORT datad (284:284:284) (342:342:342))
(IOPATH dataa combout (374:374:374) (392:392:392))
(IOPATH datab combout (384:384:384) (398:398:398))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~2\\)
(DELAY
(ABSOLUTE
(PORT datab (327:327:327) (384:384:384))
(PORT datac (761:761:761) (676:676:676))
(PORT datad (225:225:225) (233:233:233))
(IOPATH datab combout (423:423:423) (451:451:451))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~5\\)
(DELAY
(ABSOLUTE
(PORT dataa (328:328:328) (392:392:392))
(PORT datab (325:325:325) (382:382:382))
(PORT datac (297:297:297) (359:359:359))
(PORT datad (284:284:284) (343:343:343))
(IOPATH dataa combout (404:404:404) (450:450:450))
(IOPATH datab combout (406:406:406) (453:453:453))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~3\\)
(DELAY
(ABSOLUTE
(PORT dataa (341:341:341) (401:401:401))
(PORT datab (339:339:339) (394:394:394))
(PORT datac (296:296:296) (359:359:359))
(PORT datad (297:297:297) (353:353:353))
(IOPATH dataa combout (404:404:404) (450:450:450))
(IOPATH datab combout (406:406:406) (453:453:453))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~4\\)
(DELAY
(ABSOLUTE
(PORT dataa (570:570:570) (549:549:549))
(PORT datab (326:326:326) (382:382:382))
(PORT datac (283:283:283) (348:348:348))
(PORT datad (225:225:225) (232:232:232))
(IOPATH dataa combout (428:428:428) (449:449:449))
(IOPATH datab combout (438:438:438) (455:455:455))
(IOPATH datac combout (301:301:301) (283:283:283))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~6\\)
(DELAY
(ABSOLUTE
(PORT dataa (332:332:332) (396:396:396))
(PORT datab (328:328:328) (385:385:385))
(PORT datac (224:224:224) (239:239:239))
(PORT datad (225:225:225) (233:233:233))
(IOPATH dataa combout (350:350:350) (371:371:371))
(IOPATH datab combout (354:354:354) (380:380:380))
(IOPATH datac combout (301:301:301) (285:285:285))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~7\\)
(DELAY
(ABSOLUTE
(PORT dataa (563:563:563) (549:549:549))
(PORT datab (329:329:329) (387:387:387))
(PORT datac (522:522:522) (502:502:502))
(PORT datad (799:799:799) (654:654:654))
(IOPATH dataa combout (435:435:435) (407:407:407))
(IOPATH datab combout (437:437:437) (407:407:407))
(IOPATH datac combout (305:305:305) (285:285:285))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~8\\)
(DELAY
(ABSOLUTE
(PORT dataa (355:355:355) (418:418:418))
(PORT datab (529:529:529) (432:432:432))
(PORT datac (224:224:224) (239:239:239))
(PORT datad (224:224:224) (232:232:232))
(IOPATH dataa combout (404:404:404) (450:450:450))
(IOPATH datab combout (415:415:415) (425:425:425))
(IOPATH datac combout (305:305:305) (285:285:285))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|ledBuf\~0\\)
(DELAY
(ABSOLUTE
(PORT datad (737:737:737) (601:601:601))
(IOPATH datac combout (415:415:415) (429:429:429))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|ledBuf\\)
(DELAY
(ABSOLUTE
(PORT clk (2183:2183:2183) (2153:2153:2153))
(PORT d (90:90:90) (101:101:101))
(IOPATH (posedge clk) q (240:240:240) (240:240:240))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (195:195:195))
)
)
)

1526
MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho Normal file
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949
MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo Normal file
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@ -0,0 +1,949 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP3C25Q240C8 Package PQFP240
//
//
// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "MainController")
(DATE "03/12/2024 16:24:29")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiii_io_obuf")
(INSTANCE \\FPGA_LED_1\~output\\)
(DELAY
(ABSOLUTE
(PORT i (1403:1403:1403) (1502:1502:1502))
(IOPATH i o (2195:2195:2195) (2297:2297:2297))
)
)
)
(CELL
(CELLTYPE "cycloneiii_io_ibuf")
(INSTANCE \\FPGA_CLK\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (899:899:899) (1014:1014:1014))
)
)
)
(CELL
(CELLTYPE "cycloneiii_clkctrl")
(INSTANCE \\FPGA_CLK\~inputclkctrl\\)
(DELAY
(ABSOLUTE
(PORT inclk[0] (190:190:190) (179:179:179))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[0\]\~24\\)
(DELAY
(ABSOLUTE
(PORT dataa (567:567:567) (600:600:600))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[0\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[1\]\~26\\)
(DELAY
(ABSOLUTE
(PORT datab (576:576:576) (592:592:592))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[1\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[2\]\~28\\)
(DELAY
(ABSOLUTE
(PORT datab (566:566:566) (594:594:594))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[2\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[3\]\~30\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (423:423:423))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[3\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[4\]\~32\\)
(DELAY
(ABSOLUTE
(PORT dataa (583:583:583) (615:615:615))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[4\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[5\]\~34\\)
(DELAY
(ABSOLUTE
(PORT datab (342:342:342) (425:425:425))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[5\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[6\]\~36\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (425:425:425))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[6\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[7\]\~38\\)
(DELAY
(ABSOLUTE
(PORT datab (561:561:561) (592:592:592))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[7\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[8\]\~40\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (423:423:423))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[8\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[9\]\~42\\)
(DELAY
(ABSOLUTE
(PORT dataa (343:343:343) (434:434:434))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[9\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[10\]\~44\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (421:421:421))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[10\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[11\]\~46\\)
(DELAY
(ABSOLUTE
(PORT dataa (343:343:343) (434:434:434))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[11\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[12\]\~48\\)
(DELAY
(ABSOLUTE
(PORT datab (340:340:340) (422:422:422))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[12\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[13\]\~50\\)
(DELAY
(ABSOLUTE
(PORT datab (357:357:357) (434:434:434))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[13\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[14\]\~52\\)
(DELAY
(ABSOLUTE
(PORT datab (358:358:358) (435:435:435))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[14\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[15\]\~54\\)
(DELAY
(ABSOLUTE
(PORT dataa (370:370:370) (460:460:460))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[15\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[16\]\~56\\)
(DELAY
(ABSOLUTE
(PORT datab (359:359:359) (436:436:436))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[16\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[17\]\~58\\)
(DELAY
(ABSOLUTE
(PORT dataa (362:362:362) (447:447:447))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[17\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (893:893:893) (866:866:866))
(PORT datab (635:635:635) (645:645:645))
(PORT datac (534:534:534) (562:562:562))
(PORT datad (572:572:572) (584:584:584))
(IOPATH dataa combout (438:438:438) (448:448:448))
(IOPATH datab combout (440:440:440) (462:462:462))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[18\]\~60\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (436:436:436))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[18\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[19\]\~62\\)
(DELAY
(ABSOLUTE
(PORT datab (344:344:344) (425:425:425))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[19\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[20\]\~64\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (426:426:426))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[20\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[21\]\~66\\)
(DELAY
(ABSOLUTE
(PORT datab (344:344:344) (424:424:424))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[21\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[22\]\~68\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (428:428:428))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[22\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[23\]\~70\\)
(DELAY
(ABSOLUTE
(PORT dataa (821:821:821) (810:810:810))
(IOPATH dataa combout (471:471:471) (481:481:481))
(IOPATH cin combout (607:607:607) (577:577:577))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[23\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~1\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (435:435:435))
(PORT datab (342:342:342) (425:425:425))
(PORT datac (302:302:302) (385:385:385))
(PORT datad (302:302:302) (378:378:378))
(IOPATH dataa combout (420:420:420) (428:428:428))
(IOPATH datab combout (432:432:432) (433:433:433))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~2\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (427:427:427))
(PORT datac (776:776:776) (761:761:761))
(PORT datad (237:237:237) (256:256:256))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~5\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (434:434:434))
(PORT datab (343:343:343) (424:424:424))
(PORT datac (319:319:319) (396:396:396))
(PORT datad (304:304:304) (379:379:379))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (457:457:457) (489:489:489))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~3\\)
(DELAY
(ABSOLUTE
(PORT dataa (361:361:361) (445:445:445))
(PORT datab (359:359:359) (437:437:437))
(PORT datac (318:318:318) (396:396:396))
(PORT datad (319:319:319) (389:389:389))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (457:457:457) (489:489:489))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~4\\)
(DELAY
(ABSOLUTE
(PORT dataa (583:583:583) (613:613:613))
(PORT datab (342:342:342) (424:424:424))
(PORT datac (301:301:301) (385:385:385))
(PORT datad (237:237:237) (255:255:255))
(IOPATH dataa combout (481:481:481) (491:491:491))
(IOPATH datab combout (494:494:494) (496:496:496))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~6\\)
(DELAY
(ABSOLUTE
(PORT dataa (348:348:348) (438:438:438))
(PORT datab (344:344:344) (427:427:427))
(PORT datac (235:235:235) (262:262:262))
(PORT datad (237:237:237) (255:255:255))
(IOPATH dataa combout (393:393:393) (398:398:398))
(IOPATH datab combout (393:393:393) (408:408:408))
(IOPATH datac combout (324:324:324) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~7\\)
(DELAY
(ABSOLUTE
(PORT dataa (579:579:579) (617:617:617))
(PORT datab (345:345:345) (429:429:429))
(PORT datac (541:541:541) (559:559:559))
(PORT datad (816:816:816) (741:741:741))
(IOPATH dataa combout (471:471:471) (453:453:453))
(IOPATH datab combout (472:472:472) (452:452:452))
(IOPATH datac combout (327:327:327) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~8\\)
(DELAY
(ABSOLUTE
(PORT dataa (373:373:373) (464:464:464))
(PORT datab (531:531:531) (492:492:492))
(PORT datac (235:235:235) (262:262:262))
(PORT datad (236:236:236) (255:255:255))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (454:454:454) (473:473:473))
(IOPATH datac combout (327:327:327) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|ledBuf\~0\\)
(DELAY
(ABSOLUTE
(PORT datad (747:747:747) (674:674:674))
(IOPATH datac combout (462:462:462) (482:482:482))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|ledBuf\\)
(DELAY
(ABSOLUTE
(PORT clk (2411:2411:2411) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
)
)
)

1526
MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho Normal file
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949
MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo Normal file
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@ -0,0 +1,949 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP3C25Q240C8 Package PQFP240
//
//
// This file contains Fast Corner delays for the design using part EP3C25Q240C8,
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "MainController")
(DATE "03/12/2024 16:24:29")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiii_io_obuf")
(INSTANCE \\FPGA_LED_1\~output\\)
(DELAY
(ABSOLUTE
(PORT i (677:677:677) (604:604:604))
(IOPATH i o (1309:1309:1309) (1354:1354:1354))
)
)
)
(CELL
(CELLTYPE "cycloneiii_io_ibuf")
(INSTANCE \\FPGA_CLK\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (320:320:320) (873:873:873))
)
)
)
(CELL
(CELLTYPE "cycloneiii_clkctrl")
(INSTANCE \\FPGA_CLK\~inputclkctrl\\)
(DELAY
(ABSOLUTE
(PORT inclk[0] (91:91:91) (78:78:78))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[0\]\~24\\)
(DELAY
(ABSOLUTE
(PORT dataa (211:211:211) (266:266:266))
(IOPATH dataa combout (186:186:186) (180:180:180))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[0\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[1\]\~26\\)
(DELAY
(ABSOLUTE
(PORT datab (212:212:212) (265:265:265))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[1\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[2\]\~28\\)
(DELAY
(ABSOLUTE
(PORT datab (209:209:209) (265:265:265))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[2\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[3\]\~30\\)
(DELAY
(ABSOLUTE
(PORT datab (134:134:134) (184:184:184))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[3\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1150:1150:1150))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[4\]\~32\\)
(DELAY
(ABSOLUTE
(PORT dataa (217:217:217) (273:273:273))
(IOPATH dataa combout (186:186:186) (175:175:175))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[4\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[5\]\~34\\)
(DELAY
(ABSOLUTE
(PORT datab (134:134:134) (185:185:185))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[5\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[6\]\~36\\)
(DELAY
(ABSOLUTE
(PORT datab (134:134:134) (184:184:184))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[6\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1150:1150:1150))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[7\]\~38\\)
(DELAY
(ABSOLUTE
(PORT datab (211:211:211) (265:265:265))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[7\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[8\]\~40\\)
(DELAY
(ABSOLUTE
(PORT datab (134:134:134) (183:183:183))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[8\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[9\]\~42\\)
(DELAY
(ABSOLUTE
(PORT dataa (135:135:135) (187:187:187))
(IOPATH dataa combout (165:165:165) (173:173:173))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[9\]\\)
(DELAY
(ABSOLUTE
(PORT clk (918:918:918) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[10\]\~44\\)
(DELAY
(ABSOLUTE
(PORT datab (133:133:133) (182:182:182))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[10\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1150:1150:1150))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[11\]\~46\\)
(DELAY
(ABSOLUTE
(PORT dataa (134:134:134) (187:187:187))
(IOPATH dataa combout (165:165:165) (173:173:173))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[11\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1150:1150:1150))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (612:612:612) (611:611:611))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[12\]\~48\\)
(DELAY
(ABSOLUTE
(PORT datab (133:133:133) (183:183:183))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[12\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[13\]\~50\\)
(DELAY
(ABSOLUTE
(PORT datab (141:141:141) (189:189:189))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[13\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[14\]\~52\\)
(DELAY
(ABSOLUTE
(PORT datab (141:141:141) (189:189:189))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[14\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[15\]\~54\\)
(DELAY
(ABSOLUTE
(PORT dataa (147:147:147) (199:199:199))
(IOPATH dataa combout (165:165:165) (173:173:173))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[15\]\\)
(DELAY
(ABSOLUTE
(PORT clk (917:917:917) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[16\]\~56\\)
(DELAY
(ABSOLUTE
(PORT datab (142:142:142) (189:189:189))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[16\]\\)
(DELAY
(ABSOLUTE
(PORT clk (917:917:917) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[17\]\~58\\)
(DELAY
(ABSOLUTE
(PORT dataa (143:143:143) (194:194:194))
(IOPATH dataa combout (165:165:165) (173:173:173))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[17\]\\)
(DELAY
(ABSOLUTE
(PORT clk (917:917:917) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (331:331:331) (397:397:397))
(PORT datab (233:233:233) (291:291:291))
(PORT datac (200:200:200) (249:249:249))
(PORT datad (212:212:212) (260:260:260))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (120:120:120) (125:125:125))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[18\]\~60\\)
(DELAY
(ABSOLUTE
(PORT dataa (136:136:136) (190:190:190))
(IOPATH dataa combout (186:186:186) (175:175:175))
(IOPATH dataa cout (226:226:226) (171:171:171))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[18\]\\)
(DELAY
(ABSOLUTE
(PORT clk (917:917:917) (925:925:925))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[19\]\~62\\)
(DELAY
(ABSOLUTE
(PORT datab (135:135:135) (185:185:185))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[19\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[20\]\~64\\)
(DELAY
(ABSOLUTE
(PORT datab (135:135:135) (185:185:185))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[20\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[21\]\~66\\)
(DELAY
(ABSOLUTE
(PORT datab (135:135:135) (185:185:185))
(IOPATH datab combout (166:166:166) (176:176:176))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[21\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[22\]\~68\\)
(DELAY
(ABSOLUTE
(PORT datab (135:135:135) (186:186:186))
(IOPATH datab combout (192:192:192) (177:177:177))
(IOPATH datab cout (227:227:227) (175:175:175))
(IOPATH datad combout (68:68:68) (63:63:63))
(IOPATH cin combout (187:187:187) (204:204:204))
(IOPATH cin cout (34:34:34) (34:34:34))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[22\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[23\]\~70\\)
(DELAY
(ABSOLUTE
(PORT dataa (303:303:303) (368:368:368))
(IOPATH dataa combout (195:195:195) (203:203:203))
(IOPATH cin combout (187:187:187) (204:204:204))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[23\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1151:1151:1151))
(PORT d (37:37:37) (50:50:50))
(PORT sclr (348:348:348) (372:372:372))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
(HOLD sclr (posedge clk) (84:84:84))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~1\\)
(DELAY
(ABSOLUTE
(PORT dataa (138:138:138) (190:190:190))
(PORT datab (135:135:135) (184:184:184))
(PORT datac (122:122:122) (164:164:164))
(PORT datad (122:122:122) (160:160:160))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (119:119:119) (125:125:125))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~2\\)
(DELAY
(ABSOLUTE
(PORT datab (135:135:135) (184:184:184))
(PORT datac (289:289:289) (344:344:344))
(PORT datad (90:90:90) (107:107:107))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (120:120:120) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~5\\)
(DELAY
(ABSOLUTE
(PORT dataa (138:138:138) (190:190:190))
(PORT datab (137:137:137) (186:186:186))
(PORT datac (130:130:130) (170:170:170))
(PORT datad (124:124:124) (162:162:162))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (120:120:120) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~3\\)
(DELAY
(ABSOLUTE
(PORT dataa (143:143:143) (193:193:193))
(PORT datab (143:143:143) (192:192:192))
(PORT datac (128:128:128) (168:168:168))
(PORT datad (129:129:129) (165:165:165))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (119:119:119) (125:125:125))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~4\\)
(DELAY
(ABSOLUTE
(PORT dataa (218:218:218) (274:274:274))
(PORT datab (135:135:135) (185:185:185))
(PORT datac (121:121:121) (164:164:164))
(PORT datad (90:90:90) (107:107:107))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (120:120:120) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~6\\)
(DELAY
(ABSOLUTE
(PORT dataa (139:139:139) (193:193:193))
(PORT datab (137:137:137) (188:188:188))
(PORT datac (89:89:89) (109:109:109))
(PORT datad (90:90:90) (106:106:106))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (160:160:160) (156:156:156))
(IOPATH datac combout (119:119:119) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~7\\)
(DELAY
(ABSOLUTE
(PORT dataa (218:218:218) (278:278:278))
(PORT datab (138:138:138) (189:189:189))
(PORT datac (203:203:203) (249:249:249))
(PORT datad (301:301:301) (355:355:355))
(IOPATH dataa combout (170:170:170) (163:163:163))
(IOPATH datab combout (168:168:168) (167:167:167))
(IOPATH datac combout (119:119:119) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~8\\)
(DELAY
(ABSOLUTE
(PORT dataa (151:151:151) (205:205:205))
(PORT datab (185:185:185) (222:222:222))
(PORT datac (88:88:88) (110:110:110))
(PORT datad (89:89:89) (106:106:106))
(IOPATH dataa combout (158:158:158) (157:157:157))
(IOPATH datab combout (168:168:168) (167:167:167))
(IOPATH datac combout (119:119:119) (124:124:124))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|ledBuf\~0\\)
(DELAY
(ABSOLUTE
(PORT datad (274:274:274) (308:308:308))
(IOPATH datac combout (190:190:190) (195:195:195))
(IOPATH datad combout (68:68:68) (63:63:63))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|ledBuf\\)
(DELAY
(ABSOLUTE
(PORT clk (1115:1115:1115) (1152:1152:1152))
(PORT d (37:37:37) (50:50:50))
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (84:84:84))
)
)
)

108
MainController/simulation/modelsim/MainController_modelsim.xrf Normal file
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@ -0,0 +1,108 @@
vendor_name = ModelSim
source_file = 1, D:/GITEA/altera/MainController/MainController.bdf
source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.qip
source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.vhd
source_file = 1, D:/GITEA/altera/MainController/RAM.vhd
source_file = 1, D:/GITEA/altera/MainController/LedBlink.vhd
source_file = 1, D:/GITEA/altera/MainController/db/MainController.cbx.xml
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v
design_name = MainController
instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1
instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1
instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1
instance = comp, \Data[4]~output\, Data[4]~output, MainController, 1
instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1
instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1
instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1
instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1
instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1
instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1
instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1
instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1
instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1
instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1
instance = comp, \inst2|counter[2]~28\, inst2|counter[2]~28, MainController, 1
instance = comp, \inst2|counter[2]\, inst2|counter[2], MainController, 1
instance = comp, \inst2|counter[3]~30\, inst2|counter[3]~30, MainController, 1
instance = comp, \inst2|counter[3]\, inst2|counter[3], MainController, 1
instance = comp, \inst2|counter[4]~32\, inst2|counter[4]~32, MainController, 1
instance = comp, \inst2|counter[4]\, inst2|counter[4], MainController, 1
instance = comp, \inst2|counter[5]~34\, inst2|counter[5]~34, MainController, 1
instance = comp, \inst2|counter[5]\, inst2|counter[5], MainController, 1
instance = comp, \inst2|counter[6]~36\, inst2|counter[6]~36, MainController, 1
instance = comp, \inst2|counter[6]\, inst2|counter[6], MainController, 1
instance = comp, \inst2|counter[7]~38\, inst2|counter[7]~38, MainController, 1
instance = comp, \inst2|counter[7]\, inst2|counter[7], MainController, 1
instance = comp, \inst2|counter[8]~40\, inst2|counter[8]~40, MainController, 1
instance = comp, \inst2|counter[8]\, inst2|counter[8], MainController, 1
instance = comp, \inst2|counter[9]~42\, inst2|counter[9]~42, MainController, 1
instance = comp, \inst2|counter[9]\, inst2|counter[9], MainController, 1
instance = comp, \inst2|counter[10]~44\, inst2|counter[10]~44, MainController, 1
instance = comp, \inst2|counter[10]\, inst2|counter[10], MainController, 1
instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1
instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1
instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1
instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1
instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1
instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1
instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1
instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1
instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1
instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
instance = comp, \nOE~input\, nOE~input, MainController, 1
instance = comp, \nWE~input\, nWE~input, MainController, 1
instance = comp, \nCE~input\, nCE~input, MainController, 1
instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1

949
MainController/simulation/modelsim/MainController_vhd.sdo Normal file
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@ -0,0 +1,949 @@
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP3C25Q240C8 Package PQFP240
//
//
// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "MainController")
(DATE "03/12/2024 16:24:29")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiii_io_obuf")
(INSTANCE \\FPGA_LED_1\~output\\)
(DELAY
(ABSOLUTE
(PORT i (1403:1403:1403) (1502:1502:1502))
(IOPATH i o (2195:2195:2195) (2297:2297:2297))
)
)
)
(CELL
(CELLTYPE "cycloneiii_io_ibuf")
(INSTANCE \\FPGA_CLK\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (899:899:899) (1014:1014:1014))
)
)
)
(CELL
(CELLTYPE "cycloneiii_clkctrl")
(INSTANCE \\FPGA_CLK\~inputclkctrl\\)
(DELAY
(ABSOLUTE
(PORT inclk[0] (190:190:190) (179:179:179))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[0\]\~24\\)
(DELAY
(ABSOLUTE
(PORT dataa (567:567:567) (600:600:600))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[0\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[1\]\~26\\)
(DELAY
(ABSOLUTE
(PORT datab (576:576:576) (592:592:592))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[1\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[2\]\~28\\)
(DELAY
(ABSOLUTE
(PORT datab (566:566:566) (594:594:594))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[2\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[3\]\~30\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (423:423:423))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[3\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[4\]\~32\\)
(DELAY
(ABSOLUTE
(PORT dataa (583:583:583) (615:615:615))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[4\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[5\]\~34\\)
(DELAY
(ABSOLUTE
(PORT datab (342:342:342) (425:425:425))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[5\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[6\]\~36\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (425:425:425))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[6\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[7\]\~38\\)
(DELAY
(ABSOLUTE
(PORT datab (561:561:561) (592:592:592))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[7\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[8\]\~40\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (423:423:423))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[8\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[9\]\~42\\)
(DELAY
(ABSOLUTE
(PORT dataa (343:343:343) (434:434:434))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[9\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1920:1920:1920) (1930:1930:1930))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[10\]\~44\\)
(DELAY
(ABSOLUTE
(PORT datab (341:341:341) (421:421:421))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[10\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[11\]\~46\\)
(DELAY
(ABSOLUTE
(PORT dataa (343:343:343) (434:434:434))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[11\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2413:2413:2413))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (1472:1472:1472) (1612:1612:1612))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[12\]\~48\\)
(DELAY
(ABSOLUTE
(PORT datab (340:340:340) (422:422:422))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[12\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[13\]\~50\\)
(DELAY
(ABSOLUTE
(PORT datab (357:357:357) (434:434:434))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[13\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[14\]\~52\\)
(DELAY
(ABSOLUTE
(PORT datab (358:358:358) (435:435:435))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[14\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[15\]\~54\\)
(DELAY
(ABSOLUTE
(PORT dataa (370:370:370) (460:460:460))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[15\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[16\]\~56\\)
(DELAY
(ABSOLUTE
(PORT datab (359:359:359) (436:436:436))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[16\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[17\]\~58\\)
(DELAY
(ABSOLUTE
(PORT dataa (362:362:362) (447:447:447))
(IOPATH dataa combout (461:461:461) (481:481:481))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[17\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (893:893:893) (866:866:866))
(PORT datab (635:635:635) (645:645:645))
(PORT datac (534:534:534) (562:562:562))
(PORT datad (572:572:572) (584:584:584))
(IOPATH dataa combout (438:438:438) (448:448:448))
(IOPATH datab combout (440:440:440) (462:462:462))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[18\]\~60\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (436:436:436))
(IOPATH dataa combout (471:471:471) (472:472:472))
(IOPATH dataa cout (552:552:552) (416:416:416))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[18\]\\)
(DELAY
(ABSOLUTE
(PORT clk (1919:1919:1919) (1929:1929:1929))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[19\]\~62\\)
(DELAY
(ABSOLUTE
(PORT datab (344:344:344) (425:425:425))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[19\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[20\]\~64\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (426:426:426))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[20\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[21\]\~66\\)
(DELAY
(ABSOLUTE
(PORT datab (344:344:344) (424:424:424))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[21\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[22\]\~68\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (428:428:428))
(IOPATH datab combout (472:472:472) (473:473:473))
(IOPATH datab cout (565:565:565) (421:421:421))
(IOPATH datad combout (177:177:177) (155:155:155))
(IOPATH cin combout (607:607:607) (577:577:577))
(IOPATH cin cout (73:73:73) (73:73:73))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[22\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|counter\[23\]\~70\\)
(DELAY
(ABSOLUTE
(PORT dataa (821:821:821) (810:810:810))
(IOPATH dataa combout (471:471:471) (481:481:481))
(IOPATH cin combout (607:607:607) (577:577:577))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|counter\[23\]\\)
(DELAY
(ABSOLUTE
(PORT clk (2410:2410:2410) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(PORT sclr (951:951:951) (989:989:989))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
(HOLD sclr (posedge clk) (212:212:212))
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~1\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (435:435:435))
(PORT datab (342:342:342) (425:425:425))
(PORT datac (302:302:302) (385:385:385))
(PORT datad (302:302:302) (378:378:378))
(IOPATH dataa combout (420:420:420) (428:428:428))
(IOPATH datab combout (432:432:432) (433:433:433))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~2\\)
(DELAY
(ABSOLUTE
(PORT datab (343:343:343) (427:427:427))
(PORT datac (776:776:776) (761:761:761))
(PORT datad (237:237:237) (256:256:256))
(IOPATH datab combout (473:473:473) (487:487:487))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~5\\)
(DELAY
(ABSOLUTE
(PORT dataa (346:346:346) (434:434:434))
(PORT datab (343:343:343) (424:424:424))
(PORT datac (319:319:319) (396:396:396))
(PORT datad (304:304:304) (379:379:379))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (457:457:457) (489:489:489))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~3\\)
(DELAY
(ABSOLUTE
(PORT dataa (361:361:361) (445:445:445))
(PORT datab (359:359:359) (437:437:437))
(PORT datac (318:318:318) (396:396:396))
(PORT datad (319:319:319) (389:389:389))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (457:457:457) (489:489:489))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~4\\)
(DELAY
(ABSOLUTE
(PORT dataa (583:583:583) (613:613:613))
(PORT datab (342:342:342) (424:424:424))
(PORT datac (301:301:301) (385:385:385))
(PORT datad (237:237:237) (255:255:255))
(IOPATH dataa combout (481:481:481) (491:491:491))
(IOPATH datab combout (494:494:494) (496:496:496))
(IOPATH datac combout (324:324:324) (315:315:315))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~6\\)
(DELAY
(ABSOLUTE
(PORT dataa (348:348:348) (438:438:438))
(PORT datab (344:344:344) (427:427:427))
(PORT datac (235:235:235) (262:262:262))
(PORT datad (237:237:237) (255:255:255))
(IOPATH dataa combout (393:393:393) (398:398:398))
(IOPATH datab combout (393:393:393) (408:408:408))
(IOPATH datac combout (324:324:324) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~7\\)
(DELAY
(ABSOLUTE
(PORT dataa (579:579:579) (617:617:617))
(PORT datab (345:345:345) (429:429:429))
(PORT datac (541:541:541) (559:559:559))
(PORT datad (816:816:816) (741:741:741))
(IOPATH dataa combout (471:471:471) (453:453:453))
(IOPATH datab combout (472:472:472) (452:452:452))
(IOPATH datac combout (327:327:327) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|LessThan0\~8\\)
(DELAY
(ABSOLUTE
(PORT dataa (373:373:373) (464:464:464))
(PORT datab (531:531:531) (492:492:492))
(PORT datac (235:235:235) (262:262:262))
(PORT datad (236:236:236) (255:255:255))
(IOPATH dataa combout (456:456:456) (486:486:486))
(IOPATH datab combout (454:454:454) (473:473:473))
(IOPATH datac combout (327:327:327) (316:316:316))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst2\|ledBuf\~0\\)
(DELAY
(ABSOLUTE
(PORT datad (747:747:747) (674:674:674))
(IOPATH datac combout (462:462:462) (482:482:482))
(IOPATH datad combout (177:177:177) (155:155:155))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE \\inst2\|ledBuf\\)
(DELAY
(ABSOLUTE
(PORT clk (2411:2411:2411) (2414:2414:2414))
(PORT d (99:99:99) (115:115:115))
(IOPATH (posedge clk) q (261:261:261) (261:261:261))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (212:212:212))
)
)
)