diff --git a/MainController/LedBlink.bsf b/MainController/LedBlink.bsf
new file mode 100644
index 0000000..3ebfff5
--- /dev/null
+++ b/MainController/LedBlink.bsf
@@ -0,0 +1,43 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 136 96)
+	(text "LedBlink" (rect 5 0 38 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 120 32)
+		(output)
+		(text "led" (rect 0 0 10 12)(font "Arial" ))
+		(text "led" (rect 89 27 99 39)(font "Arial" ))
+		(line (pt 120 32)(pt 104 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 104 64)(line_width 1))
+	)
+)
diff --git a/MainController/LedBlink.vhd b/MainController/LedBlink.vhd
new file mode 100644
index 0000000..9aae7aa
--- /dev/null
+++ b/MainController/LedBlink.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity LedBlink is
+
+Port ( 
+	clk : in STD_LOGIC;
+	led : out STD_LOGIC
+	);
+end LedBlink;
+
+architecture Behavioral of LedBlink is
+	signal counter : natural range 0 to 16666667 := 0;
+	signal ledBuf : STD_LOGIC := '1';
+begin		
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if counter < 16666667 then
+				counter <= counter + 1;
+			else
+				counter <= 0;
+				ledBuf <= not ledBuf;				
+			end if;
+		end if;	
+	end process;
+	
+	led <= ledBuf;
+	
+end Behavioral;
\ No newline at end of file
diff --git a/MainController/MainController.bdf b/MainController/MainController.bdf
index 8974e2b..246509c 100644
--- a/MainController/MainController.bdf
+++ b/MainController/MainController.bdf
@@ -19,43 +19,11 @@ Altera or its authorized distributors.  Please refer to the
 applicable agreement for further details.
 */
 (header "graphic" (version "1.4"))
-(pin
-	(input)
-	(rect 376 248 544 264)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "WR" (rect 5 0 23 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
 (pin
 	(input)
 	(rect 376 216 544 232)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "Address[7..0]" (rect 5 0 72 12)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 376 264 544 280)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "Clk" (rect 5 0 22 12)(font "Arial" ))
+	(text "Address[7..0]" (rect 5 0 71 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -66,12 +34,13 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 264 104 320 216))
 )
 (pin
 	(input)
 	(rect 376 144 544 160)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "Clk50MHh" (rect 5 0 56 12)(font "Arial" ))
+	(text "FPGA_CLK" (rect 5 0 61 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -82,12 +51,81 @@ applicable agreement for further details.
 		(line (pt 109 12)(pt 113 8))
 	)
 	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 328 144 376 160))
+)
+(pin
+	(input)
+	(rect 376 248 544 264)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "nOE" (rect 5 0 26 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 320 248 376 264))
+)
+(pin
+	(input)
+	(rect 376 264 544 280)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "nWE" (rect 5 0 28 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 320 264 376 280))
+)
+(pin
+	(input)
+	(rect 376 280 544 296)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "nCE" (rect 5 0 26 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 320 280 376 296))
+)
+(pin
+	(output)
+	(rect 1144 40 1320 56)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "FPGA_LED_1" (rect 90 0 158 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1320 40 1376 56))
 )
 (pin
 	(bidir)
 	(rect 368 232 544 248)
 	(text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6)))
-	(text "Data[15..0]" (rect 5 0 61 12)(font "Arial" ))
+	(text "Data[7..0]" (rect 5 0 54 12)(font "Arial" ))
 	(pt 176 8)
 	(drawing
 		(line (pt 120 4)(pt 98 4))
@@ -100,6 +138,7 @@ applicable agreement for further details.
 	)
 	(flipy)
 	(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 200 120 256 232))
 )
 (symbol
 	(rect 632 104 784 216)
@@ -145,9 +184,9 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 848 160 1048 304)
-	(text "RAM" (rect 5 0 28 12)(font "Arial" ))
-	(text "inst1" (rect 24 128 47 140)(font "Arial" ))
+	(rect 632 16 752 96)
+	(text "LedBlink" (rect 5 0 46 12)(font "Arial" ))
+	(text "inst2" (rect 8 64 31 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
@@ -156,63 +195,85 @@ applicable agreement for further details.
 		(line (pt 0 32)(pt 16 32))
 	)
 	(port
-		(pt 0 64)
+		(pt 120 32)
+		(output)
+		(text "led" (rect 0 0 14 12)(font "Arial" ))
+		(text "led" (rect 88 27 102 39)(font "Arial" ))
+		(line (pt 120 32)(pt 104 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 104 64))
+	)
+)
+(symbol
+	(rect 952 176 1152 352)
+	(text "RAM" (rect 5 0 28 12)(font "Arial" ))
+	(text "inst1" (rect 8 160 31 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 27 35 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
 		(input)
 		(text "address0[7..0]" (rect 0 0 70 12)(font "Arial" ))
-		(text "address0[7..0]" (rect 24 56 94 68)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
+		(text "address0[7..0]" (rect 21 43 91 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wr0" (rect 0 0 16 12)(font "Arial" ))
+		(text "wr0" (rect 21 59 37 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "clk0" (rect 0 0 20 12)(font "Arial" ))
+		(text "clk0" (rect 21 75 41 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "wr0" (rect 0 0 16 12)(font "Arial" ))
-		(text "wr0" (rect 24 88 40 100)(font "Arial" ))
-		(line (pt 0 96)(pt 16 96))
+		(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "address1[7..0]" (rect 21 91 91 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "clk0" (rect 0 0 20 12)(font "Arial" ))
-		(text "clk0" (rect 24 104 44 116)(font "Arial" ))
+		(text "wr1" (rect 0 0 16 12)(font "Arial" ))
+		(text "wr1" (rect 21 107 37 119)(font "Arial" ))
 		(line (pt 0 112)(pt 16 112))
 	)
 	(port
-		(pt 200 64)
-		(input)
-		(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
-		(text "address1[7..0]" (rect 120 56 190 68)(font "Arial" ))
-		(line (pt 184 64)(pt 200 64)(line_width 3))
-	)
-	(port
-		(pt 200 96)
-		(input)
-		(text "wr1" (rect 0 0 16 12)(font "Arial" ))
-		(text "wr1" (rect 160 88 176 100)(font "Arial" ))
-		(line (pt 184 96)(pt 200 96))
-	)
-	(port
-		(pt 200 112)
+		(pt 0 128)
 		(input)
 		(text "clk1" (rect 0 0 20 12)(font "Arial" ))
-		(text "clk1" (rect 160 104 180 116)(font "Arial" ))
-		(line (pt 184 112)(pt 200 112))
+		(text "clk1" (rect 21 123 41 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128))
 	)
 	(port
-		(pt 0 80)
+		(pt 200 32)
 		(bidir)
-		(text "data0[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "data0[15..0]" (rect 24 72 83 84)(font "Arial" ))
-		(line (pt 16 80)(pt 0 80)(line_width 3))
+		(text "data0[7..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "data0[7..0]" (rect 138 27 191 39)(font "Arial" ))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
 	)
 	(port
-		(pt 200 80)
+		(pt 200 48)
 		(bidir)
-		(text "data1[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "data1[15..0]" (rect 128 72 187 84)(font "Arial" ))
-		(line (pt 200 80)(pt 184 80)(line_width 3))
+		(text "data1[7..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "data1[7..0]" (rect 139 43 192 55)(font "Arial" ))
+		(line (pt 200 48)(pt 184 48)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 184 128))
+		(rectangle (rect 16 16 184 160))
 	)
 )
 (connector
@@ -229,10 +290,6 @@ applicable agreement for further details.
 	(pt 592 624)
 	(bus)
 )
-(connector
-	(pt 608 152)
-	(pt 608 624)
-)
 (connector
 	(pt 544 152)
 	(pt 608 152)
@@ -257,6 +314,30 @@ applicable agreement for further details.
 	(pt 544 272)
 	(pt 848 272)
 )
+(connector
+	(pt 544 256)
+	(pt 560 256)
+)
+(connector
+	(pt 560 256)
+	(pt 848 256)
+)
+(connector
+	(pt 608 48)
+	(pt 608 152)
+)
+(connector
+	(pt 608 152)
+	(pt 608 624)
+)
+(connector
+	(pt 608 48)
+	(pt 632 48)
+)
+(connector
+	(pt 752 48)
+	(pt 1144 48)
+)
 (connector
 	(pt 544 224)
 	(pt 592 224)
@@ -264,7 +345,12 @@ applicable agreement for further details.
 )
 (connector
 	(pt 592 224)
-	(pt 848 224)
+	(pt 952 224)
+	(bus)
+)
+(connector
+	(pt 936 240)
+	(pt 936 160)
 	(bus)
 )
 (connector
@@ -274,18 +360,29 @@ applicable agreement for further details.
 )
 (connector
 	(pt 576 240)
-	(pt 848 240)
+	(pt 936 240)
 	(bus)
 )
 (connector
-	(pt 544 256)
-	(pt 560 256)
+	(pt 936 160)
+	(pt 1168 160)
+	(bus)
 )
 (connector
-	(pt 560 256)
-	(pt 848 256)
+	(pt 1168 160)
+	(pt 1168 208)
+	(bus)
+)
+(connector
+	(pt 1168 208)
+	(pt 1152 208)
+	(bus)
+)
+(connector
+	(pt 544 288)
+	(pt 848 288)
 )
 (junction (pt 608 152))
 (junction (pt 592 224))
-(junction (pt 576 240))
 (junction (pt 560 256))
+(junction (pt 576 240))
diff --git a/MainController/MainController.qsf b/MainController/MainController.qsf
index 7b7d19f..6613a1b 100644
--- a/MainController/MainController.qsf
+++ b/MainController/MainController.qsf
@@ -55,4 +55,48 @@ set_global_assignment -name VHDL_FILE RAM.vhd
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE LedBlink.vhd
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_166 -to FPGA_LED_1
+set_location_assignment PIN_224 -to Data[5]
+set_location_assignment PIN_223 -to Data[6]
+set_location_assignment PIN_226 -to Data[4]
+set_location_assignment PIN_230 -to Address[6]
+set_location_assignment PIN_231 -to Address[1]
+set_location_assignment PIN_232 -to Address[4]
+set_location_assignment PIN_233 -to Address[3]
+set_location_assignment PIN_234 -to Address[2]
+set_location_assignment PIN_235 -to Address[5]
+set_location_assignment PIN_221 -to Data[7]
+set_location_assignment PIN_196 -to Address[0]
+set_location_assignment PIN_195 -to Address[7]
+set_location_assignment PIN_194 -to Data[0]
+set_location_assignment PIN_189 -to Data[1]
+set_location_assignment PIN_188 -to Data[2]
+set_location_assignment PIN_187 -to Data[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Address[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Data[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_LED_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nOE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nWE
+set_location_assignment PIN_217 -to nOE
+set_location_assignment PIN_218 -to nWE
+set_location_assignment PIN_219 -to nCE
+set_location_assignment PIN_31 -to FPGA_CLK
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/MainController/RAM.bsf b/MainController/RAM.bsf
index c4b9206..4a53d03 100644
--- a/MainController/RAM.bsf
+++ b/MainController/RAM.bsf
@@ -18,75 +18,75 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.2"))
+(header "symbol" (version "1.1"))
 (symbol
-	(rect 64 64 264 208)
-	(text "RAM" (rect 5 0 28 12)(font "Arial" ))
-	(text "inst" (rect 24 128 41 140)(font "Arial" ))
+	(rect 16 16 216 192)
+	(text "RAM" (rect 5 0 29 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clk" (rect 0 0 14 12)(font "Arial" ))
-		(text "clk" (rect 21 27 35 39)(font "Arial" ))
-		(line (pt 0 32)(pt 16 32))
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address0[7..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "address0[7..0]" (rect 21 43 77 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "address0[7..0]" (rect 0 0 70 12)(font "Arial" ))
-		(text "address0[7..0]" (rect 24 56 94 68)(font "Arial" ))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
+		(text "wr0" (rect 0 0 14 12)(font "Arial" ))
+		(text "wr0" (rect 21 59 35 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "clk0" (rect 0 0 15 12)(font "Arial" ))
+		(text "clk0" (rect 21 75 36 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "wr0" (rect 0 0 16 12)(font "Arial" ))
-		(text "wr0" (rect 24 88 40 100)(font "Arial" ))
-		(line (pt 0 96)(pt 16 96))
+		(text "address1[7..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "address1[7..0]" (rect 21 91 76 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "clk0" (rect 0 0 20 12)(font "Arial" ))
-		(text "clk0" (rect 24 104 44 116)(font "Arial" ))
-		(line (pt 0 112)(pt 16 112))
+		(text "wr1" (rect 0 0 12 12)(font "Arial" ))
+		(text "wr1" (rect 21 107 33 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
 	)
 	(port
-		(pt 200 64)
+		(pt 0 128)
 		(input)
-		(text "address1[7..0]" (rect 0 0 70 12)(font "Arial" ))
-		(text "address1[7..0]" (rect 120 56 190 68)(font "Arial" ))
-		(line (pt 184 64)(pt 200 64)(line_width 3))
+		(text "clk1" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk1" (rect 21 123 35 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
 	)
 	(port
-		(pt 200 96)
-		(input)
-		(text "wr1" (rect 0 0 16 12)(font "Arial" ))
-		(text "wr1" (rect 160 88 176 100)(font "Arial" ))
-		(line (pt 184 96)(pt 200 96))
-	)
-	(port
-		(pt 200 112)
-		(input)
-		(text "clk1" (rect 0 0 20 12)(font "Arial" ))
-		(text "clk1" (rect 160 104 180 116)(font "Arial" ))
-		(line (pt 184 112)(pt 200 112))
-	)
-	(port
-		(pt 0 80)
+		(pt 200 32)
 		(bidir)
-		(text "data0[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "data0[15..0]" (rect 24 72 83 84)(font "Arial" ))
-		(line (pt 16 80)(pt 0 80)(line_width 3))
+		(text "data0[7..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "data0[7..0]" (rect 138 27 179 39)(font "Arial" ))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
 	)
 	(port
-		(pt 200 80)
+		(pt 200 48)
 		(bidir)
-		(text "data1[15..0]" (rect 0 0 59 12)(font "Arial" ))
-		(text "data1[15..0]" (rect 128 72 187 84)(font "Arial" ))
-		(line (pt 200 80)(pt 184 80)(line_width 3))
+		(text "data1[7..0]" (rect 0 0 40 12)(font "Arial" ))
+		(text "data1[7..0]" (rect 139 43 179 55)(font "Arial" ))
+		(line (pt 200 48)(pt 184 48)(line_width 3))
 	)
 	(drawing
-		(rectangle (rect 16 16 184 128))
+		(rectangle (rect 16 16 184 160)(line_width 1))
 	)
 )
diff --git a/MainController/RAM.vhd b/MainController/RAM.vhd
index 6a354c6..24832e1 100644
--- a/MainController/RAM.vhd
+++ b/MainController/RAM.vhd
@@ -8,12 +8,12 @@ entity RAM is
 	port(
 		clk : in std_logic;
 		
-		data0 : inout std_logic_vector(15 downto 0);
+		data0 : inout std_logic_vector(7 downto 0);
 		address0 : in std_logic_vector(7 downto 0);
 		wr0 : in std_logic;
 		clk0 : in std_logic;
 		
-		data1 : inout std_logic_vector(15 downto 0);
+		data1 : inout std_logic_vector(7 downto 0);
 		address1 : in std_logic_vector(7 downto 0);
 		wr1 : in std_logic;
 		clk1 : in std_logic		
@@ -22,7 +22,7 @@ end entity;
 
 architecture behavorial of RAM is
 
-type mem is array (255 downto 0) of std_logic_vector(15 downto 0);
+type mem is array (255 downto 0) of std_logic_vector(7 downto 0);
 signal memory : mem;
 
 signal clk0Prev : std_logic := '0';
diff --git a/MainController/greybox_tmp/cbx_args.txt b/MainController/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..b6c9585
--- /dev/null
+++ b/MainController/greybox_tmp/cbx_args.txt
@@ -0,0 +1,66 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=1
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=4
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=1
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=8
+CLK1_PHASE_SHIFT=0
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=40000
+INTENDED_DEVICE_FAMILY="Cyclone III"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_USED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_USED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+SELF_RESET_ON_LOSS_LOCK=OFF
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone III"
+CBX_AUTO_BLACKBOX=ALL
+areset
+inclk
+inclk
+clk
+clk
+locked
diff --git a/MainController/incremental_db/README b/MainController/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/MainController/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/MainController/incremental_db/compiled_partitions/MainController.db_info b/MainController/incremental_db/compiled_partitions/MainController.db_info
new file mode 100644
index 0000000..64aa382
--- /dev/null
+++ b/MainController/incremental_db/compiled_partitions/MainController.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+Version_Index = 318808576
+Creation_Time = Mon Mar 04 15:47:51 2024
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb
new file mode 100644
index 0000000..74bcb72
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.ammdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb
new file mode 100644
index 0000000..e970138
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.cdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.dfp b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.dfp differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb
new file mode 100644
index 0000000..5370598
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.hdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.logdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..4a036e2
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.cmp.rcfdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb
new file mode 100644
index 0000000..9b00d66
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.cdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi
new file mode 100644
index 0000000..0be2cf6
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.dpi differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..577fdb8
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.cdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hb_info differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..9fc9c60
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.hdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb
new file mode 100644
index 0000000..d0f2a76
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.hdb differ
diff --git a/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt
new file mode 100644
index 0000000..6859430
Binary files /dev/null and b/MainController/incremental_db/compiled_partitions/MainController.root_partition.map.kpt differ
diff --git a/MainController/output_file.rbf b/MainController/output_file.rbf
new file mode 100644
index 0000000..2f23e56
Binary files /dev/null and b/MainController/output_file.rbf differ
diff --git a/MainController/output_files/MainController.asm.rpt b/MainController/output_files/MainController.asm.rpt
new file mode 100644
index 0000000..35241b8
--- /dev/null
+++ b/MainController/output_files/MainController.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for MainController
+Tue Mar 12 16:24:24 2024
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: D:/GITEA/altera/MainController/output_files/MainController.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 12 16:24:24 2024 ;
+; Revision Name         ; MainController                        ;
+; Top-level Entity Name ; MainController                        ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C25Q240C8                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------------------+
+; Assembler Generated Files                                      ;
++----------------------------------------------------------------+
+; File Name                                                      ;
++----------------------------------------------------------------+
+; D:/GITEA/altera/MainController/output_files/MainController.sof ;
++----------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Assembler Device Options: D:/GITEA/altera/MainController/output_files/MainController.sof ;
++----------------+-------------------------------------------------------------------------+
+; Option         ; Setting                                                                 ;
++----------------+-------------------------------------------------------------------------+
+; Device         ; EP3C25Q240C8                                                            ;
+; JTAG usercode  ; 0x0013959E                                                              ;
+; Checksum       ; 0x0013959E                                                              ;
++----------------+-------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Tue Mar 12 16:24:23 2024
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off MainController -c MainController
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4610 megabytes
+    Info: Processing ended: Tue Mar 12 16:24:24 2024
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/MainController/output_files/MainController.done b/MainController/output_files/MainController.done
new file mode 100644
index 0000000..63617f0
--- /dev/null
+++ b/MainController/output_files/MainController.done
@@ -0,0 +1 @@
+Tue Mar 12 16:24:29 2024
diff --git a/MainController/output_files/MainController.eda.rpt b/MainController/output_files/MainController.eda.rpt
new file mode 100644
index 0000000..39ab5c2
--- /dev/null
+++ b/MainController/output_files/MainController.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for MainController
+Tue Mar 12 16:24:29 2024
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Tue Mar 12 16:24:29 2024 ;
+; Revision Name             ; MainController                        ;
+; Top-level Entity Name     ; MainController                        ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                   ;
++----------------------------------------------------------------------------------------------+
+; Generated Files                                                                              ;
++----------------------------------------------------------------------------------------------+
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho      ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho       ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho     ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController.vho                        ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo  ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo   ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo ;
+; D:/GITEA/altera/MainController/simulation/modelsim/MainController_vhd.sdo                    ;
++----------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Tue Mar 12 16:24:28 2024
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController
+Info (204019): Generated file MainController_8_1200mv_85c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_8_1200mv_0c_slow.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_min_1200mv_0c_fast.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController.vho in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_8_1200mv_85c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_8_1200mv_0c_vhd_slow.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_min_1200mv_0c_vhd_fast.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file MainController_vhd.sdo in folder "D:/GITEA/altera/MainController/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 4567 megabytes
+    Info: Processing ended: Tue Mar 12 16:24:29 2024
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/MainController/output_files/MainController.fit.rpt b/MainController/output_files/MainController.fit.rpt
new file mode 100644
index 0000000..7f87d40
--- /dev/null
+++ b/MainController/output_files/MainController.fit.rpt
@@ -0,0 +1,1192 @@
+Fitter report for MainController
+Tue Mar 12 16:24:22 2024
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Bidir Pins
+ 15. Dual Purpose and Dedicated Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Non-Global High Fan-Out Signals
+ 24. Routing Usage Summary
+ 25. LAB Logic Elements
+ 26. LAB-wide Signals
+ 27. LAB Signals Sourced
+ 28. LAB Signals Sourced Out
+ 29. LAB Distinct Inputs
+ 30. I/O Rules Summary
+ 31. I/O Rules Details
+ 32. I/O Rules Matrix
+ 33. Fitter Device Options
+ 34. Operating Settings and Conditions
+ 35. Fitter Messages
+ 36. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 12 16:24:21 2024       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; MainController                              ;
+; Top-level Entity Name              ; MainController                              ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C25Q240C8                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 34 / 24,624 ( < 1 % )                       ;
+;     Total combinational functions  ; 34 / 24,624 ( < 1 % )                       ;
+;     Dedicated logic registers      ; 25 / 24,624 ( < 1 % )                       ;
+; Total registers                    ; 25                                          ;
+; Total pins                         ; 21 / 149 ( 14 % )                           ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0 / 608,256 ( 0 % )                         ;
+; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                             ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                               ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C25Q240C8                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------+
+; I/O Assignment Warnings             ;
++------------+------------------------+
+; Pin Name   ; Reason                 ;
++------------+------------------------+
+; FPGA_LED_1 ; Missing drive strength ;
+; Data[7]    ; Missing drive strength ;
+; Data[6]    ; Missing drive strength ;
+; Data[5]    ; Missing drive strength ;
+; Data[4]    ; Missing drive strength ;
+; Data[3]    ; Missing drive strength ;
+; Data[2]    ; Missing drive strength ;
+; Data[1]    ; Missing drive strength ;
+; Data[0]    ; Missing drive strength ;
++------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 )         ; 0.00 % ( 0 / 121 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 121 ) ; 0.00 % ( 0 / 121 )         ; 0.00 % ( 0 / 121 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 111 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in D:/GITEA/altera/MainController/output_files/MainController.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 34 / 24,624 ( < 1 % ) ;
+;     -- Combinational with no register       ; 9                     ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 25                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 8                     ;
+;     -- 3 input functions                    ; 1                     ;
+;     -- <=2 input functions                  ; 25                    ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 11                    ;
+;     -- arithmetic mode                      ; 23                    ;
+;                                             ;                       ;
+; Total registers*                            ; 25 / 25,294 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 25 / 24,624 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 670 ( 0 % )       ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 4 / 1,539 ( < 1 % )   ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 21 / 149 ( 14 % )     ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 66 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 608,256 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 608,256 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
+; Maximum fan-out                             ; 25                    ;
+; Highest non-global fan-out                  ; 25                    ;
+; Total fan-out                               ; 194                   ;
+; Average fan-out                             ; 1.62                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 34 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % )              ;
+;     -- Combinational with no register       ; 9                    ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 25                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 8                    ; 0                              ;
+;     -- 3 input functions                    ; 1                    ; 0                              ;
+;     -- <=2 input functions                  ; 25                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 11                   ; 0                              ;
+;     -- arithmetic mode                      ; 23                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 25                   ; 0                              ;
+;     -- Dedicated logic registers            ; 25 / 24624 ( < 1 % ) ; 0 / 24624 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 4 / 1539 ( < 1 % )   ; 0 / 1539 ( 0 % )               ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 21                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )      ; 0 / 132 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+; Clock control block                         ; 1 / 24 ( 4 % )       ; 0 / 24 ( 0 % )                 ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 8                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 8                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 189                  ; 5                              ;
+;     -- Registered Connections               ; 53                   ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 16                   ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 12                   ; 0                              ;
+;     -- Output Ports                         ; 1                    ; 0                              ;
+;     -- Bidir Ports                          ; 8                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                      ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Address[0] ; 196   ; 7        ; 38           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[1] ; 231   ; 8        ; 14           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[2] ; 234   ; 8        ; 7            ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[3] ; 233   ; 8        ; 7            ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[4] ; 232   ; 8        ; 14           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[5] ; 235   ; 8        ; 7            ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[6] ; 230   ; 8        ; 14           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; Address[7] ; 195   ; 7        ; 38           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; FPGA_CLK   ; 31    ; 1        ; 0            ; 16           ; 0            ; 25                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nCE        ; 219   ; 8        ; 20           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nOE        ; 217   ; 8        ; 20           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nWE        ; 218   ; 8        ; 20           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; FPGA_LED_1 ; 166   ; 6        ; 53           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+
+; Data[0] ; 194   ; 7        ; 40           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[1] ; 189   ; 7        ; 45           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[2] ; 188   ; 7        ; 45           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[3] ; 187   ; 7        ; 45           ; 34           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[4] ; 226   ; 8        ; 16           ; 34           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[5] ; 224   ; 8        ; 16           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[6] ; 223   ; 8        ; 18           ; 34           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
+; Data[7] ; 221   ; 8        ; 18           ; 34           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                     ;
++----------+-----------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------------------+--------------------------+-------------------------+---------------------------+
+; 12       ; DIFFIO_L3n, DATA1, ASDO                 ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; 14       ; DIFFIO_L4p, FLASH_nCE, nCSO             ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; 17       ; nSTATUS                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; 23       ; DCLK                                    ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; 24       ; DATA0                                   ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; 25       ; nCONFIG                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; 30       ; nCE                                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; 153      ; CONF_DONE                               ; -                        ; -                       ; Dedicated Programming Pin ;
+; 155      ; MSEL0                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; 157      ; MSEL1                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; 158      ; MSEL2                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; 158      ; MSEL3                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; 162      ; DIFFIO_R4n, nCEO                        ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; 194      ; DIFFIO_T20p, PADD0                      ; Use as regular IO        ; Data[0]                 ; Dual Purpose Pin          ;
+; 196      ; DIFFIO_T19n, PADD1                      ; Use as regular IO        ; Address[0]              ; Dual Purpose Pin          ;
+; 218      ; DIFFIO_T10n, DATA2                      ; Use as regular IO        ; nWE                     ; Dual Purpose Pin          ;
+; 219      ; DIFFIO_T10p, DATA3                      ; Use as regular IO        ; nCE                     ; Dual Purpose Pin          ;
+; 221      ; DIFFIO_T9p, DATA4                       ; Use as regular IO        ; Data[7]                 ; Dual Purpose Pin          ;
+; 224      ; DIFFIO_T7n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO        ; Data[5]                 ; Dual Purpose Pin          ;
+; 226      ; DATA5                                   ; Use as regular IO        ; Data[4]                 ; Dual Purpose Pin          ;
+; 231      ; DIFFIO_T6p, DATA6                       ; Use as regular IO        ; Address[1]              ; Dual Purpose Pin          ;
+; 232      ; DIFFIO_T5n, DATA7                       ; Use as regular IO        ; Address[4]              ; Dual Purpose Pin          ;
+; 233      ; DIFFIO_T3p, DATA11                      ; Use as regular IO        ; Address[3]              ; Dual Purpose Pin          ;
++----------+-----------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 5 / 14 ( 36 % )  ; 3.3V          ; --           ;
+; 2        ; 0 / 17 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 20 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 2 / 15 ( 13 % )  ; 3.3V          ; --           ;
+; 7        ; 6 / 20 ( 30 % )  ; 3.3V          ; --           ;
+; 8        ; 13 / 22 ( 59 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1        ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 2        ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 3        ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 4        ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 5        ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 6        ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 7        ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 8        ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 9        ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 10       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 11       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 12       ; 7          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; 13       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 14       ; 9          ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; 15       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 16       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 17       ; 11         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 18       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 19       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 20       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 21       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 22       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 23       ; 17         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; 24       ; 18         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; 25       ; 19         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 26       ; 20         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 27       ; 21         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 28       ; 22         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; 29       ; 23         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; 30       ; 24         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 31       ; 25         ; 1        ; FPGA_CLK                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 32       ; 26         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 33       ; 27         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 34       ; 28         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 35       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 36       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 37       ; 31         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 38       ; 32         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 39       ; 35         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 40       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 41       ; 36         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 42       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 43       ; 37         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 44       ; 38         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 45       ; 39         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 46       ; 40         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 47       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 48       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 49       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 50       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 51       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 52       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 53       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 54       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 55       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 56       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 57       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 58       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 59       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 60       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 61       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 62       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 63       ; 54         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 64       ; 55         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 65       ; 56         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 66       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 67       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 68       ; 59         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 69       ; 60         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 70       ; 61         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 71       ; 62         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 72       ; 63         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 73       ; 64         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 74       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 75       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 76       ; 67         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 77       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 78       ; 68         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 79       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 80       ; 72         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 81       ; 73         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 82       ; 74         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 83       ; 77         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 84       ; 79         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 85       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 86       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 87       ; 81         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 88       ; 82         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 89       ; 86         ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 90       ; 87         ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 91       ; 88         ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 92       ; 89         ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 93       ; 90         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 94       ; 91         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 95       ; 93         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 96       ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 97       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 98       ; 96         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 99       ; 97         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 100      ; 99         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 101      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 102      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 103      ; 101        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 104      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 105      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 106      ; 105        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 107      ; 106        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 108      ; 107        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 109      ; 108        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 110      ; 110        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 111      ; 111        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 112      ; 112        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 113      ; 116        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 114      ; 117        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 115      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 116      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 117      ; 119        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 118      ; 120        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 119      ; 121        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 120      ; 122        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 121      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 122      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 123      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 124      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 125      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 126      ; 126        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 127      ; 127        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 128      ; 128        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 129      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 130      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 131      ; 132        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 132      ; 133        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 133      ; 134        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 134      ; 135        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 135      ; 136        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 136      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 137      ; 137        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 138      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 139      ; 138        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 140      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 141      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 142      ; 140        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 143      ; 141        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 144      ; 142        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 145      ; 143        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 146      ; 144        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 147      ; 146        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 148      ; 147        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 149      ; 148        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 150      ; 149        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 151      ; 150        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 152      ; 151        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 153      ; 152        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 154      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 155      ; 153        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 156      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 157      ; 154        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 158      ; 155        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 158      ; 156        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; 159      ; 159        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 160      ; 160        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 161      ; 161        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 162      ; 162        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; 163      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 164      ; 163        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 165      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 166      ; 164        ; 6        ; FPGA_LED_1                                                ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; 167      ; 165        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 168      ; 166        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 169      ; 167        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; 170      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 171      ; 169        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 172      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 173      ; 170        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 174      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 175      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 176      ; 173        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 177      ; 174        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; 178      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; 179      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 180      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 181      ; 176        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 182      ; 177        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 183      ; 178        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 184      ; 180        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 185      ; 181        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 186      ; 182        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 187      ; 183        ; 7        ; Data[3]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 188      ; 184        ; 7        ; Data[2]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 189      ; 185        ; 7        ; Data[1]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 190      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 191      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 192      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 193      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 194      ; 189        ; 7        ; Data[0]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 195      ; 190        ; 7        ; Address[7]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 196      ; 191        ; 7        ; Address[0]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 197      ; 192        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 198      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 199      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 200      ; 197        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 201      ; 198        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 202      ; 200        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 203      ; 201        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 204      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 205      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 206      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 207      ; 205        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 208      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 209      ; 209        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 210      ; 210        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 211      ; 211        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 212      ; 212        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; 213      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 214      ; 215        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 215      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 216      ; 216        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 217      ; 217        ; 8        ; nOE                                                       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 218      ; 218        ; 8        ; nWE                                                       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 219      ; 219        ; 8        ; nCE                                                       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 220      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 221      ; 221        ; 8        ; Data[7]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 222      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 223      ; 224        ; 8        ; Data[6]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 224      ; 225        ; 8        ; Data[5]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 225      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; 226      ; 227        ; 8        ; Data[4]                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 227      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 228      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; 229      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; 230      ; 230        ; 8        ; Address[6]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 231      ; 231        ; 8        ; Address[1]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 232      ; 232        ; 8        ; Address[4]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 233      ; 237        ; 8        ; Address[3]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 234      ; 238        ; 8        ; Address[2]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 235      ; 239        ; 8        ; Address[5]                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; 236      ; 242        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 237      ; 243        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 238      ; 244        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 239      ; 245        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; 240      ; 246        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                      ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name            ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+
+; |MainController            ; 34 (0)      ; 25 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 21   ; 0            ; 9 (0)        ; 0 (0)             ; 25 (0)           ; |MainController                ; work         ;
+;    |LedBlink:inst2|        ; 34 (34)     ; 25 (25)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 25 (25)          ; |MainController|LedBlink:inst2 ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                        ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; FPGA_LED_1 ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Address[7] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[6] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[5] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[4] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[3] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[2] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[1] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Address[0] ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; nOE        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; nWE        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; nCE        ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[7]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[6]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[5]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[4]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[3]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[2]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[1]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; Data[0]    ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; FPGA_CLK   ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; Address[7]          ;                   ;         ;
+; Address[6]          ;                   ;         ;
+; Address[5]          ;                   ;         ;
+; Address[4]          ;                   ;         ;
+; Address[3]          ;                   ;         ;
+; Address[2]          ;                   ;         ;
+; Address[1]          ;                   ;         ;
+; Address[0]          ;                   ;         ;
+; nOE                 ;                   ;         ;
+; nWE                 ;                   ;         ;
+; nCE                 ;                   ;         ;
+; Data[7]             ;                   ;         ;
+; Data[6]             ;                   ;         ;
+; Data[5]             ;                   ;         ;
+; Data[4]             ;                   ;         ;
+; Data[3]             ;                   ;         ;
+; Data[2]             ;                   ;         ;
+; Data[1]             ;                   ;         ;
+; Data[0]             ;                   ;         ;
+; FPGA_CLK            ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                        ;
++----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+
+; Name                       ; Location           ; Fan-Out ; Usage       ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+
+; FPGA_CLK                   ; PIN_31             ; 25      ; Clock       ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; LedBlink:inst2|LessThan0~8 ; LCCOMB_X51_Y13_N26 ; 25      ; Sync. clear ; no     ; --                   ; --               ; --                        ;
++----------------------------+--------------------+---------+-------------+--------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                ;
++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; FPGA_CLK ; PIN_31   ; 25      ; 13                                   ; Global Clock         ; GCLK4            ; --                        ;
++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------+
+; Non-Global High Fan-Out Signals         ;
++-------------------------------+---------+
+; Name                          ; Fan-Out ;
++-------------------------------+---------+
+; LedBlink:inst2|LessThan0~8    ; 25      ;
+; LedBlink:inst2|counter[4]     ; 3       ;
+; LedBlink:inst2|counter[16]    ; 3       ;
+; LedBlink:inst2|counter[15]    ; 3       ;
+; LedBlink:inst2|ledBuf         ; 2       ;
+; LedBlink:inst2|counter[11]    ; 2       ;
+; LedBlink:inst2|counter[10]    ; 2       ;
+; LedBlink:inst2|counter[9]     ; 2       ;
+; LedBlink:inst2|counter[8]     ; 2       ;
+; LedBlink:inst2|counter[7]     ; 2       ;
+; LedBlink:inst2|counter[5]     ; 2       ;
+; LedBlink:inst2|counter[3]     ; 2       ;
+; LedBlink:inst2|counter[2]     ; 2       ;
+; LedBlink:inst2|counter[1]     ; 2       ;
+; LedBlink:inst2|counter[0]     ; 2       ;
+; LedBlink:inst2|counter[6]     ; 2       ;
+; LedBlink:inst2|counter[12]    ; 2       ;
+; LedBlink:inst2|counter[13]    ; 2       ;
+; LedBlink:inst2|counter[23]    ; 2       ;
+; LedBlink:inst2|counter[22]    ; 2       ;
+; LedBlink:inst2|counter[21]    ; 2       ;
+; LedBlink:inst2|counter[20]    ; 2       ;
+; LedBlink:inst2|counter[19]    ; 2       ;
+; LedBlink:inst2|counter[18]    ; 2       ;
+; LedBlink:inst2|counter[17]    ; 2       ;
+; LedBlink:inst2|counter[14]    ; 2       ;
+; LedBlink:inst2|ledBuf~0       ; 1       ;
+; LedBlink:inst2|LessThan0~7    ; 1       ;
+; LedBlink:inst2|LessThan0~6    ; 1       ;
+; LedBlink:inst2|LessThan0~5    ; 1       ;
+; LedBlink:inst2|LessThan0~4    ; 1       ;
+; LedBlink:inst2|LessThan0~3    ; 1       ;
+; LedBlink:inst2|LessThan0~2    ; 1       ;
+; LedBlink:inst2|LessThan0~1    ; 1       ;
+; LedBlink:inst2|LessThan0~0    ; 1       ;
+; LedBlink:inst2|counter[23]~70 ; 1       ;
+; LedBlink:inst2|counter[22]~69 ; 1       ;
+; LedBlink:inst2|counter[22]~68 ; 1       ;
+; LedBlink:inst2|counter[21]~67 ; 1       ;
+; LedBlink:inst2|counter[21]~66 ; 1       ;
+; LedBlink:inst2|counter[20]~65 ; 1       ;
+; LedBlink:inst2|counter[20]~64 ; 1       ;
+; LedBlink:inst2|counter[19]~63 ; 1       ;
+; LedBlink:inst2|counter[19]~62 ; 1       ;
+; LedBlink:inst2|counter[18]~61 ; 1       ;
+; LedBlink:inst2|counter[18]~60 ; 1       ;
+; LedBlink:inst2|counter[17]~59 ; 1       ;
+; LedBlink:inst2|counter[17]~58 ; 1       ;
+; LedBlink:inst2|counter[16]~57 ; 1       ;
+; LedBlink:inst2|counter[16]~56 ; 1       ;
+; LedBlink:inst2|counter[15]~55 ; 1       ;
+; LedBlink:inst2|counter[15]~54 ; 1       ;
+; LedBlink:inst2|counter[14]~53 ; 1       ;
+; LedBlink:inst2|counter[14]~52 ; 1       ;
+; LedBlink:inst2|counter[13]~51 ; 1       ;
+; LedBlink:inst2|counter[13]~50 ; 1       ;
+; LedBlink:inst2|counter[12]~49 ; 1       ;
+; LedBlink:inst2|counter[12]~48 ; 1       ;
+; LedBlink:inst2|counter[11]~47 ; 1       ;
+; LedBlink:inst2|counter[11]~46 ; 1       ;
+; LedBlink:inst2|counter[10]~45 ; 1       ;
+; LedBlink:inst2|counter[10]~44 ; 1       ;
+; LedBlink:inst2|counter[9]~43  ; 1       ;
+; LedBlink:inst2|counter[9]~42  ; 1       ;
+; LedBlink:inst2|counter[8]~41  ; 1       ;
+; LedBlink:inst2|counter[8]~40  ; 1       ;
+; LedBlink:inst2|counter[7]~39  ; 1       ;
+; LedBlink:inst2|counter[7]~38  ; 1       ;
+; LedBlink:inst2|counter[6]~37  ; 1       ;
+; LedBlink:inst2|counter[6]~36  ; 1       ;
+; LedBlink:inst2|counter[5]~35  ; 1       ;
+; LedBlink:inst2|counter[5]~34  ; 1       ;
+; LedBlink:inst2|counter[4]~33  ; 1       ;
+; LedBlink:inst2|counter[4]~32  ; 1       ;
+; LedBlink:inst2|counter[3]~31  ; 1       ;
+; LedBlink:inst2|counter[3]~30  ; 1       ;
+; LedBlink:inst2|counter[2]~29  ; 1       ;
+; LedBlink:inst2|counter[2]~28  ; 1       ;
+; LedBlink:inst2|counter[1]~27  ; 1       ;
+; LedBlink:inst2|counter[1]~26  ; 1       ;
+; LedBlink:inst2|counter[0]~25  ; 1       ;
+; LedBlink:inst2|counter[0]~24  ; 1       ;
++-------------------------------+---------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary                         ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage                 ;
++-----------------------+-----------------------+
+; Block interconnects   ; 20 / 71,559 ( < 1 % ) ;
+; C16 interconnects     ; 0 / 2,597 ( 0 % )     ;
+; C4 interconnects      ; 4 / 46,848 ( < 1 % )  ;
+; Direct links          ; 11 / 71,559 ( < 1 % ) ;
+; Global clocks         ; 1 / 20 ( 5 % )        ;
+; Local interconnects   ; 30 / 24,624 ( < 1 % ) ;
+; R24 interconnects     ; 0 / 2,496 ( 0 % )     ;
+; R4 interconnects      ; 4 / 62,424 ( < 1 % )  ;
++-----------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements                                                       ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 8.50) ; Number of LABs  (Total = 4) ;
++--------------------------------------------+-----------------------------+
+; 1                                          ; 2                           ;
+; 2                                          ; 0                           ;
+; 3                                          ; 0                           ;
+; 4                                          ; 0                           ;
+; 5                                          ; 0                           ;
+; 6                                          ; 0                           ;
+; 7                                          ; 0                           ;
+; 8                                          ; 0                           ;
+; 9                                          ; 0                           ;
+; 10                                         ; 0                           ;
+; 11                                         ; 0                           ;
+; 12                                         ; 0                           ;
+; 13                                         ; 0                           ;
+; 14                                         ; 0                           ;
+; 15                                         ; 0                           ;
+; 16                                         ; 2                           ;
++--------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 4) ;
++------------------------------------+-----------------------------+
+; 1 Clock                            ; 3                           ;
+; 1 Sync. clear                      ; 1                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 14.75) ; Number of LABs  (Total = 4) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 1                           ;
+; 2                                            ; 1                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 0                           ;
+; 20                                           ; 0                           ;
+; 21                                           ; 0                           ;
+; 22                                           ; 0                           ;
+; 23                                           ; 0                           ;
+; 24                                           ; 0                           ;
+; 25                                           ; 0                           ;
+; 26                                           ; 0                           ;
+; 27                                           ; 0                           ;
+; 28                                           ; 2                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 2.00) ; Number of LABs  (Total = 4) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 3                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 3.00) ; Number of LABs  (Total = 4) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 2                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 2                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 21        ; 0            ; 21        ; 0            ; 0            ; 21        ; 21        ; 0            ; 21        ; 21        ; 0            ; 0            ; 0            ; 0            ; 20           ; 0            ; 0            ; 20           ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 21        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 21           ; 0         ; 21           ; 21           ; 0         ; 0         ; 21           ; 0         ; 0         ; 21           ; 21           ; 21           ; 21           ; 1            ; 21           ; 21           ; 1            ; 21           ; 21           ; 13           ; 21           ; 21           ; 21           ; 21           ; 21           ; 21           ; 0         ; 21           ; 21           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; FPGA_LED_1         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[7]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[6]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[5]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[4]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[3]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[2]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[1]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Address[0]         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nOE                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nWE                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nCE                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Data[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FPGA_CLK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C25Q240C8 for design "MainController"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C16Q240C8 is compatible
+    Info (176445): Device EP3C40Q240C8 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 12
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 14
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 23
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 24
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 162
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'MainController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node FPGA_CLK~input (placed in PIN 31 (CLK0, DIFFCLK_0p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X43_Y11 to location X53_Y22
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.34 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Warning (169177): 20 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin Address[7] uses I/O standard 3.3-V LVTTL at 195
+    Info (169178): Pin Address[6] uses I/O standard 3.3-V LVTTL at 230
+    Info (169178): Pin Address[5] uses I/O standard 3.3-V LVTTL at 235
+    Info (169178): Pin Address[4] uses I/O standard 3.3-V LVTTL at 232
+    Info (169178): Pin Address[3] uses I/O standard 3.3-V LVTTL at 233
+    Info (169178): Pin Address[2] uses I/O standard 3.3-V LVTTL at 234
+    Info (169178): Pin Address[1] uses I/O standard 3.3-V LVTTL at 231
+    Info (169178): Pin Address[0] uses I/O standard 3.3-V LVTTL at 196
+    Info (169178): Pin nOE uses I/O standard 3.3-V LVTTL at 217
+    Info (169178): Pin nWE uses I/O standard 3.3-V LVTTL at 218
+    Info (169178): Pin nCE uses I/O standard 3.3-V LVTTL at 219
+    Info (169178): Pin Data[7] uses I/O standard 3.3-V LVTTL at 221
+    Info (169178): Pin Data[6] uses I/O standard 3.3-V LVTTL at 223
+    Info (169178): Pin Data[5] uses I/O standard 3.3-V LVTTL at 224
+    Info (169178): Pin Data[4] uses I/O standard 3.3-V LVTTL at 226
+    Info (169178): Pin Data[3] uses I/O standard 3.3-V LVTTL at 187
+    Info (169178): Pin Data[2] uses I/O standard 3.3-V LVTTL at 188
+    Info (169178): Pin Data[1] uses I/O standard 3.3-V LVTTL at 189
+    Info (169178): Pin Data[0] uses I/O standard 3.3-V LVTTL at 194
+    Info (169178): Pin FPGA_CLK uses I/O standard 3.3-V LVTTL at 31
+Warning (169064): Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin Data[7] has a permanently disabled output enable
+    Info (169065): Pin Data[6] has a permanently disabled output enable
+    Info (169065): Pin Data[5] has a permanently disabled output enable
+    Info (169065): Pin Data[4] has a permanently disabled output enable
+    Info (169065): Pin Data[3] has a permanently disabled output enable
+    Info (169065): Pin Data[2] has a permanently disabled output enable
+    Info (169065): Pin Data[1] has a permanently disabled output enable
+    Info (169065): Pin Data[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file D:/GITEA/altera/MainController/output_files/MainController.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 5391 megabytes
+    Info: Processing ended: Tue Mar 12 16:24:22 2024
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in D:/GITEA/altera/MainController/output_files/MainController.fit.smsg.
+
+
diff --git a/MainController/output_files/MainController.fit.smsg b/MainController/output_files/MainController.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/MainController/output_files/MainController.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/MainController/output_files/MainController.fit.summary b/MainController/output_files/MainController.fit.summary
new file mode 100644
index 0000000..97c41d7
--- /dev/null
+++ b/MainController/output_files/MainController.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 12 16:24:21 2024
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : MainController
+Top-level Entity Name : MainController
+Family : Cyclone III
+Device : EP3C25Q240C8
+Timing Models : Final
+Total logic elements : 34 / 24,624 ( < 1 % )
+    Total combinational functions : 34 / 24,624 ( < 1 % )
+    Dedicated logic registers : 25 / 24,624 ( < 1 % )
+Total registers : 25
+Total pins : 21 / 149 ( 14 % )
+Total virtual pins : 0
+Total memory bits : 0 / 608,256 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/MainController/output_files/MainController.flow.rpt b/MainController/output_files/MainController.flow.rpt
new file mode 100644
index 0000000..f92f1d4
--- /dev/null
+++ b/MainController/output_files/MainController.flow.rpt
@@ -0,0 +1,132 @@
+Flow report for MainController
+Tue Mar 12 16:24:29 2024
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 12 16:24:29 2024       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; MainController                              ;
+; Top-level Entity Name              ; MainController                              ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C25Q240C8                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 34 / 24,624 ( < 1 % )                       ;
+;     Total combinational functions  ; 34 / 24,624 ( < 1 % )                       ;
+;     Dedicated logic registers      ; 25 / 24,624 ( < 1 % )                       ;
+; Total registers                    ; 25                                          ;
+; Total pins                         ; 21 / 149 ( 14 % )                           ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0 / 608,256 ( 0 % )                         ;
+; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                             ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                               ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/12/2024 16:24:14 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; MainController      ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                    ;
++-------------------------------------+--------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                          ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+--------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 30902508249626.171024985402028 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                           ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)         ; <None>        ; --          ; --             ;
+; IP_TOOL_NAME                        ; ALTPLL                         ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                     ; 13.1                           ; --            ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                             ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                              ; --            ; --          ; --             ;
+; MISC_FILE                           ; AlteraPLL.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                           ; AlteraPLL.ppf                  ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                           ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                       ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING          ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                         ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                   ; --            ; --          ; --             ;
++-------------------------------------+--------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 4707 MB             ; 00:00:02                           ;
+; Fitter                    ; 00:00:04     ; 1.0                     ; 5391 MB             ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 4590 MB             ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 4700 MB             ; 00:00:01                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 4550 MB             ; 00:00:01                           ;
+; Total                     ; 00:00:09     ; --                      ; --                  ; 00:00:11                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; STAS-W10         ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; STAS-W10         ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; STAS-W10         ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; STAS-W10         ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; STAS-W10         ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController
+quartus_fit --read_settings_files=off --write_settings_files=off MainController -c MainController
+quartus_asm --read_settings_files=off --write_settings_files=off MainController -c MainController
+quartus_sta MainController -c MainController
+quartus_eda --read_settings_files=off --write_settings_files=off MainController -c MainController
+
+
+
diff --git a/MainController/output_files/MainController.jdi b/MainController/output_files/MainController.jdi
new file mode 100644
index 0000000..e8b8caf
--- /dev/null
+++ b/MainController/output_files/MainController.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="9c3406557f2dade88a26"/>
+  </project>
+  <file_info>
+    <file device="EP3C25Q240C8" path="MainController.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/MainController/output_files/MainController.map.rpt b/MainController/output_files/MainController.map.rpt
index 9c11b71..c05a413 100644
--- a/MainController/output_files/MainController.map.rpt
+++ b/MainController/output_files/MainController.map.rpt
@@ -1,5 +1,5 @@
 Analysis & Synthesis report for MainController
-Mon Mar 04 16:44:59 2024
+Tue Mar 12 16:24:16 2024
 Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
 
 
@@ -14,11 +14,14 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
   6. Analysis & Synthesis Resource Usage Summary
   7. Analysis & Synthesis Resource Utilization by Entity
   8. Analysis & Synthesis IP Cores Summary
-  9. General Register Statistics
- 10. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component
- 11. altpll Parameter Settings by Entity Instance
- 12. Elapsed Time Per Partition
- 13. Analysis & Synthesis Messages
+  9. Registers Removed During Synthesis
+ 10. Removed Registers Triggering Further Register Optimizations
+ 11. General Register Statistics
+ 12. Inverted Register Statistics
+ 13. Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component
+ 14. altpll Parameter Settings by Entity Instance
+ 15. Elapsed Time Per Partition
+ 16. Analysis & Synthesis Messages
 
 
 
@@ -44,16 +47,16 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Mon Mar 04 16:44:59 2024       ;
+; Analysis & Synthesis Status        ; Successful - Tue Mar 12 16:24:16 2024       ;
 ; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
 ; Revision Name                      ; MainController                              ;
 ; Top-level Entity Name              ; MainController                              ;
 ; Family                             ; Cyclone III                                 ;
-; Total logic elements               ; 0                                           ;
-;     Total combinational functions  ; 0                                           ;
-;     Dedicated logic registers      ; 0                                           ;
-; Total registers                    ; 0                                           ;
-; Total pins                         ; 27                                          ;
+; Total logic elements               ; 34                                          ;
+;     Total combinational functions  ; 34                                          ;
+;     Dedicated logic registers      ; 25                                          ;
+; Total registers                    ; 25                                          ;
+; Total pins                         ; 21                                          ;
 ; Total virtual pins                 ; 0                                           ;
 ; Total memory bits                  ; 0                                           ;
 ; Embedded Multiplier 9-bit elements ; 0                                           ;
@@ -173,6 +176,7 @@ applicable agreement for further details.
 ; MainController.bdf               ; yes             ; User Block Diagram/Schematic File  ; D:/GITEA/altera/MainController/MainController.bdf                   ;         ;
 ; AlteraPLL.vhd                    ; yes             ; User Wizard-Generated File         ; D:/GITEA/altera/MainController/AlteraPLL.vhd                        ;         ;
 ; RAM.vhd                          ; yes             ; User VHDL File                     ; D:/GITEA/altera/MainController/RAM.vhd                              ;         ;
+; LedBlink.vhd                     ; yes             ; User VHDL File                     ; D:/GITEA/altera/MainController/LedBlink.vhd                         ;         ;
 ; altpll.tdf                       ; yes             ; Megafunction                       ; d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf        ;         ;
 ; aglobal131.inc                   ; yes             ; Megafunction                       ; d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc    ;         ;
 ; stratix_pll.inc                  ; yes             ; Megafunction                       ; d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc   ;         ;
@@ -182,42 +186,44 @@ applicable agreement for further details.
 +----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+---------+
 
 
-+-----------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary         ;
-+---------------------------------------------+-------+
-; Resource                                    ; Usage ;
-+---------------------------------------------+-------+
-;                                             ;       ;
-; Total combinational functions               ; 0     ;
-; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 0     ;
-;     -- 3 input functions                    ; 0     ;
-;     -- <=2 input functions                  ; 0     ;
-;                                             ;       ;
-; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 0     ;
-;     -- arithmetic mode                      ; 0     ;
-;                                             ;       ;
-; Total registers                             ; 0     ;
-;     -- Dedicated logic registers            ; 0     ;
-;     -- I/O registers                        ; 0     ;
-;                                             ;       ;
-; I/O pins                                    ; 27    ;
-; Embedded Multiplier 9-bit elements          ; 0     ;
-; Maximum fan-out node                        ; Clk   ;
-; Maximum fan-out                             ; 1     ;
-; Total fan-out                               ; 27    ;
-; Average fan-out                             ; 0.50  ;
-+---------------------------------------------+-------+
++--------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                              ;
++---------------------------------------------+----------------------------+
+; Resource                                    ; Usage                      ;
++---------------------------------------------+----------------------------+
+; Estimated Total logic elements              ; 34                         ;
+;                                             ;                            ;
+; Total combinational functions               ; 34                         ;
+; Logic element usage by number of LUT inputs ;                            ;
+;     -- 4 input functions                    ; 8                          ;
+;     -- 3 input functions                    ; 1                          ;
+;     -- <=2 input functions                  ; 25                         ;
+;                                             ;                            ;
+; Logic elements by mode                      ;                            ;
+;     -- normal mode                          ; 11                         ;
+;     -- arithmetic mode                      ; 23                         ;
+;                                             ;                            ;
+; Total registers                             ; 25                         ;
+;     -- Dedicated logic registers            ; 25                         ;
+;     -- I/O registers                        ; 0                          ;
+;                                             ;                            ;
+; I/O pins                                    ; 21                         ;
+; Embedded Multiplier 9-bit elements          ; 0                          ;
+; Maximum fan-out node                        ; LedBlink:inst2|LessThan0~8 ;
+; Maximum fan-out                             ; 25                         ;
+; Total fan-out                               ; 188                        ;
+; Average fan-out                             ; 1.72                       ;
++---------------------------------------------+----------------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
-; |MainController            ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 27   ; 0            ; |MainController     ; work         ;
-+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                    ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
+; |MainController            ; 34 (0)            ; 25 (0)       ; 0           ; 0            ; 0       ; 0         ; 21   ; 0            ; |MainController                ; work         ;
+;    |LedBlink:inst2|        ; 34 (34)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |MainController|LedBlink:inst2 ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
@@ -230,13 +236,2203 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------+--------------+---------+--------------+--------------+--------------------------------+----------------------------------------------+
 
 
++---------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                              ;
++------------------------------------------+--------------------------------------+
+; Register name                            ; Reason for Removal                   ;
++------------------------------------------+--------------------------------------+
+; RAM:inst1|data0[2]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data1[7]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[7]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[6]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[6]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[5]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[5]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[4]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[4]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[3]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[3]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[2]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[2]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[1]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[1]~en                    ; Lost fanout                          ;
+; RAM:inst1|data1[0]~reg0                  ; Lost fanout                          ;
+; RAM:inst1|data1[0]~en                    ; Lost fanout                          ;
+; RAM:inst1|clk1Prev                       ; Lost fanout                          ;
+; RAM:inst1|memory[0][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[7]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[6]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[5]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[4]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[3]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[2]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[1]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[1]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[0]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[0]~reg0                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|clk0Prev                       ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[3]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[4]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[5]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[6]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|data0[7]~en                    ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[0][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[1][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[2][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[3][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[4][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[5][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[6][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[7][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[8][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][0]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][1]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][2]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][3]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][4]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][5]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][6]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[9][7]                   ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[10][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[11][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[12][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[13][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[14][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[15][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[16][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[17][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[18][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[19][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[20][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[21][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[22][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[23][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[24][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[25][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[26][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[27][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[28][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[29][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[30][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[31][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[32][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[33][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[34][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[35][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[36][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[37][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[38][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[39][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[40][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[41][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[42][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[43][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[44][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[45][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[46][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[47][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[48][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[49][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[50][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[51][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[52][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[53][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[54][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[55][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[56][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[57][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[58][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[59][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[60][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[61][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[62][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[63][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[64][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[65][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[66][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[67][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[68][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[69][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[70][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[71][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[72][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[73][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[74][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[75][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[76][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[77][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[78][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[79][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[80][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[81][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[82][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[83][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[84][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[85][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[86][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[87][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[88][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[89][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[90][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[91][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[92][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[93][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[94][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[95][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[96][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[97][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[98][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][0]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][1]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][2]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][3]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][4]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][5]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][6]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[99][7]                  ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[100][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[101][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[102][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[103][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[104][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[105][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[106][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[107][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[108][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[109][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[110][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[111][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[112][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[113][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[114][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[115][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[116][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[117][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[118][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[119][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[120][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[121][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[122][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[123][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[124][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[125][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[126][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[127][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[128][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[129][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[130][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[131][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[132][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[133][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[134][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[135][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[136][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[137][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[138][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[139][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[140][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[141][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[142][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[143][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[144][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[145][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[146][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[147][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[148][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[149][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[150][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[151][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[152][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[153][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[154][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[155][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[156][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[157][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[158][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[159][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[160][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[161][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[162][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[163][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[164][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[165][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[166][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[167][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[168][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[169][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[170][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[171][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[172][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[173][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[174][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[175][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[176][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[177][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[178][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[179][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[180][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[181][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[182][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[183][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[184][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[185][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[186][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[187][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[188][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[189][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[190][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[191][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[192][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[193][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[194][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[195][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[196][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[197][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[198][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[199][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[200][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[201][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[202][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[203][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[204][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[205][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[206][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[207][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[208][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[209][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[210][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[211][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[212][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[213][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[214][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[215][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[216][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[217][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[218][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[219][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[220][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[221][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[222][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[223][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[224][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[225][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[226][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[227][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[228][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[229][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[230][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[231][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[232][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[233][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[234][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[235][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[236][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[237][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[238][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[239][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[240][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[241][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[242][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[243][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[244][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[245][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[246][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[247][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[248][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[249][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[250][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[251][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[252][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[253][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[254][7]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][0]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][1]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][2]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][3]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][4]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][5]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][6]                 ; Stuck at GND due to stuck port clock ;
+; RAM:inst1|memory[255][7]                 ; Stuck at GND due to stuck port clock ;
+; Total Number of Removed Registers = 2082 ;                                      ;
++------------------------------------------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                       ;
++-------------------------+-------------------------+-------------------------------------------------------------------------------+
+; Register name           ; Reason for Removal      ; Registers Removed due to This Register                                        ;
++-------------------------+-------------------------+-------------------------------------------------------------------------------+
+; RAM:inst1|data0[2]~en   ; Stuck at GND            ; RAM:inst1|memory[0][2], RAM:inst1|memory[1][2], RAM:inst1|memory[2][2],       ;
+;                         ; due to stuck port clock ; RAM:inst1|memory[3][2], RAM:inst1|memory[4][2], RAM:inst1|memory[5][2],       ;
+;                         ;                         ; RAM:inst1|memory[6][2], RAM:inst1|memory[7][2], RAM:inst1|memory[8][2],       ;
+;                         ;                         ; RAM:inst1|memory[9][2], RAM:inst1|memory[10][2], RAM:inst1|memory[11][2],     ;
+;                         ;                         ; RAM:inst1|memory[12][2], RAM:inst1|memory[13][2], RAM:inst1|memory[14][2],    ;
+;                         ;                         ; RAM:inst1|memory[15][2], RAM:inst1|memory[16][2], RAM:inst1|memory[17][2],    ;
+;                         ;                         ; RAM:inst1|memory[18][2], RAM:inst1|memory[19][2], RAM:inst1|memory[20][2],    ;
+;                         ;                         ; RAM:inst1|memory[21][2], RAM:inst1|memory[22][2], RAM:inst1|memory[23][2],    ;
+;                         ;                         ; RAM:inst1|memory[24][2], RAM:inst1|memory[25][2], RAM:inst1|memory[26][2],    ;
+;                         ;                         ; RAM:inst1|memory[27][2], RAM:inst1|memory[28][2], RAM:inst1|memory[29][2],    ;
+;                         ;                         ; RAM:inst1|memory[30][2], RAM:inst1|memory[31][2], RAM:inst1|memory[32][2],    ;
+;                         ;                         ; RAM:inst1|memory[33][2], RAM:inst1|memory[34][2], RAM:inst1|memory[35][2],    ;
+;                         ;                         ; RAM:inst1|memory[36][2], RAM:inst1|memory[37][2], RAM:inst1|memory[38][2],    ;
+;                         ;                         ; RAM:inst1|memory[39][2], RAM:inst1|memory[40][2], RAM:inst1|memory[41][2],    ;
+;                         ;                         ; RAM:inst1|memory[42][2], RAM:inst1|memory[43][2], RAM:inst1|memory[44][2],    ;
+;                         ;                         ; RAM:inst1|memory[45][2], RAM:inst1|memory[46][2], RAM:inst1|memory[47][2],    ;
+;                         ;                         ; RAM:inst1|memory[48][2], RAM:inst1|memory[49][2], RAM:inst1|memory[50][2],    ;
+;                         ;                         ; RAM:inst1|memory[51][2], RAM:inst1|memory[52][2], RAM:inst1|memory[53][2],    ;
+;                         ;                         ; RAM:inst1|memory[54][2], RAM:inst1|memory[55][2], RAM:inst1|memory[56][2],    ;
+;                         ;                         ; RAM:inst1|memory[57][2], RAM:inst1|memory[58][2], RAM:inst1|memory[59][2],    ;
+;                         ;                         ; RAM:inst1|memory[60][2], RAM:inst1|memory[61][2], RAM:inst1|memory[62][2],    ;
+;                         ;                         ; RAM:inst1|memory[63][2], RAM:inst1|memory[64][2], RAM:inst1|memory[65][2],    ;
+;                         ;                         ; RAM:inst1|memory[66][2], RAM:inst1|memory[67][2], RAM:inst1|memory[68][2],    ;
+;                         ;                         ; RAM:inst1|memory[69][2], RAM:inst1|memory[70][2], RAM:inst1|memory[71][2],    ;
+;                         ;                         ; RAM:inst1|memory[72][2], RAM:inst1|memory[73][2], RAM:inst1|memory[74][2],    ;
+;                         ;                         ; RAM:inst1|memory[75][2], RAM:inst1|memory[76][2], RAM:inst1|memory[77][2],    ;
+;                         ;                         ; RAM:inst1|memory[78][2], RAM:inst1|memory[79][2], RAM:inst1|memory[80][2],    ;
+;                         ;                         ; RAM:inst1|memory[81][2], RAM:inst1|memory[82][2], RAM:inst1|memory[83][2],    ;
+;                         ;                         ; RAM:inst1|memory[84][2], RAM:inst1|memory[85][2], RAM:inst1|memory[86][2],    ;
+;                         ;                         ; RAM:inst1|memory[87][2], RAM:inst1|memory[88][2], RAM:inst1|memory[89][2],    ;
+;                         ;                         ; RAM:inst1|memory[90][2], RAM:inst1|memory[91][2], RAM:inst1|memory[92][2],    ;
+;                         ;                         ; RAM:inst1|memory[93][2], RAM:inst1|memory[94][2], RAM:inst1|memory[95][2],    ;
+;                         ;                         ; RAM:inst1|memory[96][2], RAM:inst1|memory[97][2], RAM:inst1|memory[98][2],    ;
+;                         ;                         ; RAM:inst1|memory[99][2], RAM:inst1|memory[100][2], RAM:inst1|memory[101][2],  ;
+;                         ;                         ; RAM:inst1|memory[102][2], RAM:inst1|memory[103][2], RAM:inst1|memory[104][2], ;
+;                         ;                         ; RAM:inst1|memory[105][2], RAM:inst1|memory[106][2], RAM:inst1|memory[107][2], ;
+;                         ;                         ; RAM:inst1|memory[108][2], RAM:inst1|memory[109][2], RAM:inst1|memory[110][2], ;
+;                         ;                         ; RAM:inst1|memory[111][2], RAM:inst1|memory[112][2], RAM:inst1|memory[113][2], ;
+;                         ;                         ; RAM:inst1|memory[114][2], RAM:inst1|memory[115][2], RAM:inst1|memory[116][2], ;
+;                         ;                         ; RAM:inst1|memory[117][2], RAM:inst1|memory[118][2], RAM:inst1|memory[119][2], ;
+;                         ;                         ; RAM:inst1|memory[120][2], RAM:inst1|memory[121][2], RAM:inst1|memory[122][2], ;
+;                         ;                         ; RAM:inst1|memory[123][2], RAM:inst1|memory[124][2], RAM:inst1|memory[125][2], ;
+;                         ;                         ; RAM:inst1|memory[126][2], RAM:inst1|memory[127][2], RAM:inst1|memory[128][2], ;
+;                         ;                         ; RAM:inst1|memory[129][2], RAM:inst1|memory[130][2], RAM:inst1|memory[131][2], ;
+;                         ;                         ; RAM:inst1|memory[132][2], RAM:inst1|memory[133][2], RAM:inst1|memory[134][2], ;
+;                         ;                         ; RAM:inst1|memory[135][2], RAM:inst1|memory[136][2], RAM:inst1|memory[137][2], ;
+;                         ;                         ; RAM:inst1|memory[138][2], RAM:inst1|memory[139][2], RAM:inst1|memory[140][2], ;
+;                         ;                         ; RAM:inst1|memory[141][2], RAM:inst1|memory[142][2], RAM:inst1|memory[143][2], ;
+;                         ;                         ; RAM:inst1|memory[144][2], RAM:inst1|memory[145][2], RAM:inst1|memory[146][2], ;
+;                         ;                         ; RAM:inst1|memory[147][2], RAM:inst1|memory[148][2], RAM:inst1|memory[149][2], ;
+;                         ;                         ; RAM:inst1|memory[150][2], RAM:inst1|memory[151][2], RAM:inst1|memory[152][2], ;
+;                         ;                         ; RAM:inst1|memory[153][2], RAM:inst1|memory[154][2], RAM:inst1|memory[155][2], ;
+;                         ;                         ; RAM:inst1|memory[156][2], RAM:inst1|memory[157][2], RAM:inst1|memory[158][2], ;
+;                         ;                         ; RAM:inst1|memory[159][2], RAM:inst1|memory[160][2], RAM:inst1|memory[161][2], ;
+;                         ;                         ; RAM:inst1|memory[162][2], RAM:inst1|memory[163][2], RAM:inst1|memory[164][2], ;
+;                         ;                         ; RAM:inst1|memory[165][2], RAM:inst1|memory[166][2], RAM:inst1|memory[167][2], ;
+;                         ;                         ; RAM:inst1|memory[168][2], RAM:inst1|memory[169][2], RAM:inst1|memory[170][2], ;
+;                         ;                         ; RAM:inst1|memory[171][2], RAM:inst1|memory[172][2], RAM:inst1|memory[173][2], ;
+;                         ;                         ; RAM:inst1|memory[174][2], RAM:inst1|memory[175][2], RAM:inst1|memory[176][2], ;
+;                         ;                         ; RAM:inst1|memory[177][2], RAM:inst1|memory[178][2], RAM:inst1|memory[179][2], ;
+;                         ;                         ; RAM:inst1|memory[180][2], RAM:inst1|memory[181][2], RAM:inst1|memory[182][2], ;
+;                         ;                         ; RAM:inst1|memory[183][2], RAM:inst1|memory[184][2], RAM:inst1|memory[185][2], ;
+;                         ;                         ; RAM:inst1|memory[186][2], RAM:inst1|memory[187][2], RAM:inst1|memory[188][2], ;
+;                         ;                         ; RAM:inst1|memory[189][2], RAM:inst1|memory[190][2], RAM:inst1|memory[191][2], ;
+;                         ;                         ; RAM:inst1|memory[192][2], RAM:inst1|memory[193][2], RAM:inst1|memory[194][2], ;
+;                         ;                         ; RAM:inst1|memory[195][2], RAM:inst1|memory[196][2], RAM:inst1|memory[197][2], ;
+;                         ;                         ; RAM:inst1|memory[198][2], RAM:inst1|memory[199][2], RAM:inst1|memory[200][2], ;
+;                         ;                         ; RAM:inst1|memory[201][2], RAM:inst1|memory[202][2], RAM:inst1|memory[203][2], ;
+;                         ;                         ; RAM:inst1|memory[204][2], RAM:inst1|memory[205][2], RAM:inst1|memory[206][2], ;
+;                         ;                         ; RAM:inst1|memory[207][2], RAM:inst1|memory[208][2], RAM:inst1|memory[209][2], ;
+;                         ;                         ; RAM:inst1|memory[210][2], RAM:inst1|memory[211][2], RAM:inst1|memory[212][2], ;
+;                         ;                         ; RAM:inst1|memory[213][2], RAM:inst1|memory[214][2], RAM:inst1|memory[215][2], ;
+;                         ;                         ; RAM:inst1|memory[216][2], RAM:inst1|memory[217][2], RAM:inst1|memory[218][2], ;
+;                         ;                         ; RAM:inst1|memory[219][2], RAM:inst1|memory[220][2], RAM:inst1|memory[221][2], ;
+;                         ;                         ; RAM:inst1|memory[222][2], RAM:inst1|memory[223][2], RAM:inst1|memory[224][2], ;
+;                         ;                         ; RAM:inst1|memory[225][2], RAM:inst1|memory[226][2], RAM:inst1|memory[227][2], ;
+;                         ;                         ; RAM:inst1|memory[228][2], RAM:inst1|memory[229][2], RAM:inst1|memory[230][2], ;
+;                         ;                         ; RAM:inst1|memory[231][2], RAM:inst1|memory[232][2], RAM:inst1|memory[233][2], ;
+;                         ;                         ; RAM:inst1|memory[234][2], RAM:inst1|memory[235][2], RAM:inst1|memory[236][2], ;
+;                         ;                         ; RAM:inst1|memory[237][2], RAM:inst1|memory[238][2], RAM:inst1|memory[239][2], ;
+;                         ;                         ; RAM:inst1|memory[240][2], RAM:inst1|memory[241][2], RAM:inst1|memory[242][2], ;
+;                         ;                         ; RAM:inst1|memory[243][2], RAM:inst1|memory[244][2], RAM:inst1|memory[245][2], ;
+;                         ;                         ; RAM:inst1|memory[246][2], RAM:inst1|memory[247][2], RAM:inst1|memory[248][2], ;
+;                         ;                         ; RAM:inst1|memory[249][2], RAM:inst1|memory[250][2], RAM:inst1|memory[251][2], ;
+;                         ;                         ; RAM:inst1|memory[252][2], RAM:inst1|memory[253][2], RAM:inst1|memory[254][2], ;
+;                         ;                         ; RAM:inst1|memory[255][2]                                                      ;
+; RAM:inst1|clk0Prev      ; Stuck at GND            ; RAM:inst1|data0[3]~en, RAM:inst1|data0[4]~en, RAM:inst1|data0[5]~en,          ;
+;                         ; due to stuck port clock ; RAM:inst1|data0[6]~en, RAM:inst1|data0[7]~en                                  ;
+; RAM:inst1|data1[7]~reg0 ; Lost Fanouts            ; RAM:inst1|clk1Prev                                                            ;
+; RAM:inst1|memory[0][0]  ; Stuck at GND            ; RAM:inst1|data0[0]~reg0                                                       ;
+;                         ; due to stuck port clock ;                                                                               ;
++-------------------------+-------------------------+-------------------------------------------------------------------------------+
+
+
 +------------------------------------------------------+
 ; General Register Statistics                          ;
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 0     ;
-; Number of registers using Synchronous Clear  ; 0     ;
+; Total registers                              ; 25    ;
+; Number of registers using Synchronous Clear  ; 24    ;
 ; Number of registers using Synchronous Load   ; 0     ;
 ; Number of registers using Asynchronous Clear ; 0     ;
 ; Number of registers using Asynchronous Load  ; 0     ;
@@ -245,6 +2441,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------------------------------------+-------+
 
 
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; LedBlink:inst2|ledBuf                  ; 2       ;
+; Total number of inverted registers = 1 ;         ;
++----------------------------------------+---------+
+
+
 +-------------------------------------------------------------------------------------+
 ; Parameter Settings for User Entity Instance: AlteraPLL:inst|altpll:altpll_component ;
 +-------------------------------+-----------------------------+-----------------------+
@@ -651,7 +2857,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus II 64-Bit Analysis & Synthesis
     Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
-    Info: Processing started: Mon Mar 04 16:44:57 2024
+    Info: Processing started: Tue Mar 12 16:24:14 2024
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MainController -c MainController
 Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
 Info (12021): Found 1 design units, including 1 entities, in source file maincontroller.bdf
@@ -662,7 +2868,16 @@ Info (12021): Found 2 design units, including 1 entities, in source file alterap
 Info (12021): Found 2 design units, including 1 entities, in source file ram.vhd
     Info (12022): Found design unit 1: RAM-behavorial
     Info (12023): Found entity 1: RAM
+Info (12021): Found 2 design units, including 1 entities, in source file ledblink.vhd
+    Info (12022): Found design unit 1: LedBlink-Behavioral
+    Info (12023): Found entity 1: LedBlink
 Info (12127): Elaborating entity "MainController" for the top level hierarchy
+Warning (275013): Port "clk" of type RAM and instance "inst1" is missing source signal
+Warning (275009): Pin "nOE" not connected
+Warning (275009): Pin "nWE" not connected
+Warning (275009): Pin "nCE" not connected
+Info (12128): Elaborating entity "LedBlink" for hierarchy "LedBlink:inst2"
+Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst1"
 Info (12128): Elaborating entity "AlteraPLL" for hierarchy "AlteraPLL:inst"
 Info (12128): Elaborating entity "altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component"
 Info (12130): Elaborated megafunction instantiation "AlteraPLL:inst|altpll:altpll_component"
@@ -729,47 +2944,34 @@ Info (12133): Instantiated megafunction "AlteraPLL:inst|altpll:altpll_component"
 Info (12021): Found 1 design units, including 1 entities, in source file db/alterapll_altpll.v
     Info (12023): Found entity 1: AlteraPLL_altpll
 Info (12128): Elaborating entity "AlteraPLL_altpll" for hierarchy "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated"
-Info (12128): Elaborating entity "RAM" for hierarchy "RAM:inst4"
 Warning (14284): Synthesized away the following node(s):
     Warning (14285): Synthesized away the following PLL node(s):
         Warning (14320): Synthesized away node "AlteraPLL:inst|altpll:altpll_component|AlteraPLL_altpll:auto_generated|wire_pll1_clk[0]"
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 17 registers lost all their fanouts during netlist optimizations.
 Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
     Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 27 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "Clk"
-    Warning (15610): No output dependent on input pin "ClkRAM"
-    Warning (15610): No output dependent on input pin "WR"
-    Warning (15610): No output dependent on input pin "AddressRAM[7]"
-    Warning (15610): No output dependent on input pin "AddressRAM[6]"
-    Warning (15610): No output dependent on input pin "AddressRAM[5]"
-    Warning (15610): No output dependent on input pin "AddressRAM[4]"
-    Warning (15610): No output dependent on input pin "AddressRAM[3]"
-    Warning (15610): No output dependent on input pin "AddressRAM[2]"
-    Warning (15610): No output dependent on input pin "AddressRAM[1]"
-    Warning (15610): No output dependent on input pin "AddressRAM[0]"
-    Warning (15610): No output dependent on input pin "DataRAM[15]"
-    Warning (15610): No output dependent on input pin "DataRAM[14]"
-    Warning (15610): No output dependent on input pin "DataRAM[13]"
-    Warning (15610): No output dependent on input pin "DataRAM[12]"
-    Warning (15610): No output dependent on input pin "DataRAM[11]"
-    Warning (15610): No output dependent on input pin "DataRAM[10]"
-    Warning (15610): No output dependent on input pin "DataRAM[9]"
-    Warning (15610): No output dependent on input pin "DataRAM[8]"
-    Warning (15610): No output dependent on input pin "DataRAM[7]"
-    Warning (15610): No output dependent on input pin "DataRAM[6]"
-    Warning (15610): No output dependent on input pin "DataRAM[5]"
-    Warning (15610): No output dependent on input pin "DataRAM[4]"
-    Warning (15610): No output dependent on input pin "DataRAM[3]"
-    Warning (15610): No output dependent on input pin "DataRAM[2]"
-    Warning (15610): No output dependent on input pin "DataRAM[1]"
-    Warning (15610): No output dependent on input pin "DataRAM[0]"
-Info (21057): Implemented 27 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 27 input pins
-    Info (21059): Implemented 0 output pins
-Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 31 warnings
-    Info: Peak virtual memory: 4684 megabytes
-    Info: Processing ended: Mon Mar 04 16:44:59 2024
+Warning (21074): Design contains 11 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "Address[7]"
+    Warning (15610): No output dependent on input pin "Address[6]"
+    Warning (15610): No output dependent on input pin "Address[5]"
+    Warning (15610): No output dependent on input pin "Address[4]"
+    Warning (15610): No output dependent on input pin "Address[3]"
+    Warning (15610): No output dependent on input pin "Address[2]"
+    Warning (15610): No output dependent on input pin "Address[1]"
+    Warning (15610): No output dependent on input pin "Address[0]"
+    Warning (15610): No output dependent on input pin "nOE"
+    Warning (15610): No output dependent on input pin "nWE"
+    Warning (15610): No output dependent on input pin "nCE"
+Info (21057): Implemented 55 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 12 input pins
+    Info (21059): Implemented 1 output pins
+    Info (21060): Implemented 8 bidirectional pins
+    Info (21061): Implemented 34 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 19 warnings
+    Info: Peak virtual memory: 4707 megabytes
+    Info: Processing ended: Tue Mar 12 16:24:16 2024
     Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:01
+    Info: Total CPU time (on all processors): 00:00:02
 
 
diff --git a/MainController/output_files/MainController.map.summary b/MainController/output_files/MainController.map.summary
new file mode 100644
index 0000000..3d15480
--- /dev/null
+++ b/MainController/output_files/MainController.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 12 16:24:16 2024
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : MainController
+Top-level Entity Name : MainController
+Family : Cyclone III
+Total logic elements : 34
+    Total combinational functions : 34
+    Dedicated logic registers : 25
+Total registers : 25
+Total pins : 21
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/MainController/output_files/MainController.pin b/MainController/output_files/MainController.pin
new file mode 100644
index 0000000..09c6f59
--- /dev/null
+++ b/MainController/output_files/MainController.pin
@@ -0,0 +1,310 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "MainController"  ASSIGNED TO AN: EP3C25Q240C8
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCD_PLL3                    : 1         : power  :                   : 1.2V    :           :                
+GNDA3                        : 2         : gnd    :                   :         :           :                
+VCCA3                        : 3         : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 4         :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 5         :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 6         :        :                   :         : 1         :                
+VCCIO1                       : 7         : power  :                   : 3.3V    : 1         :                
+GND                          : 8         : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 9         :        :                   :         : 1         :                
+VCCINT                       : 10        : power  :                   : 1.2V    :           :                
+GND                          : 11        : gnd    :                   :         :           :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 12        : input  : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 13        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 14        : input  : 3.3-V LVTTL       :         : 1         : N              
+VCCIO1                       : 15        : power  :                   : 3.3V    : 1         :                
+GND                          : 16        : gnd    :                   :         :           :                
+nSTATUS                      : 17        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 18        :        :                   :         : 1         :                
+VCCINT                       : 19        : power  :                   : 1.2V    :           :                
+GND                          : 20        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 21        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 22        :        :                   :         : 1         :                
+~ALTERA_DCLK~                : 23        : output : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24        : input  : 3.3-V LVTTL       :         : 1         : N              
+nCONFIG                      : 25        :        :                   :         : 1         :                
+TDI                          : 26        : input  :                   :         : 1         :                
+TCK                          : 27        : input  :                   :         : 1         :                
+TMS                          : 28        : input  :                   :         : 1         :                
+TDO                          : 29        : output :                   :         : 1         :                
+nCE                          : 30        :        :                   :         : 1         :                
+FPGA_CLK                     : 31        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND+                         : 32        :        :                   :         : 1         :                
+GND+                         : 33        :        :                   :         : 2         :                
+GND+                         : 34        :        :                   :         : 2         :                
+VCCIO2                       : 35        : power  :                   : 2.5V    : 2         :                
+GND                          : 36        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 37        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 38        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 39        :        :                   :         : 2         :                
+VCCINT                       : 40        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 41        :        :                   :         : 2         :                
+GND                          : 42        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 43        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 44        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 45        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 46        :        :                   :         : 2         :                
+VCCIO2                       : 47        : power  :                   : 2.5V    : 2         :                
+GND                          : 48        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 49        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 50        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 51        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 52        :        :                   :         : 2         :                
+VCCINT                       : 53        : power  :                   : 1.2V    :           :                
+GND                          : 54        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 55        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 56        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 57        :        :                   :         : 2         :                
+VCCA1                        : 58        : power  :                   : 2.5V    :           :                
+GNDA1                        : 59        : gnd    :                   :         :           :                
+VCCD_PLL1                    : 60        : power  :                   : 1.2V    :           :                
+VCCINT                       : 61        : power  :                   : 1.2V    :           :                
+GND                          : 62        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 63        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 64        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 65        :        :                   :         : 3         :                
+VCCIO3                       : 66        : power  :                   : 2.5V    : 3         :                
+GND                          : 67        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 68        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 69        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 70        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 71        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 72        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 73        :        :                   :         : 3         :                
+VCCINT                       : 74        : power  :                   : 1.2V    :           :                
+GND                          : 75        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 76        :        :                   :         : 3         :                
+VCCIO3                       : 77        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 78        :        :                   :         : 3         :                
+GND                          : 79        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 80        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 81        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 82        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 83        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 84        :        :                   :         : 3         :                
+VCCINT                       : 85        : power  :                   : 1.2V    :           :                
+GND                          : 86        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 87        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 88        :        :                   :         : 3         :                
+GND+                         : 89        :        :                   :         : 3         :                
+GND+                         : 90        :        :                   :         : 3         :                
+GND+                         : 91        :        :                   :         : 4         :                
+GND+                         : 92        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 93        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 94        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 95        :        :                   :         : 4         :                
+VCCIO4                       : 96        : power  :                   : 2.5V    : 4         :                
+GND                          : 97        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 98        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 99        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 100       :        :                   :         : 4         :                
+VCCINT                       : 101       : power  :                   : 1.2V    :           :                
+GND                          : 102       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 103       :        :                   :         : 4         :                
+VCCIO4                       : 104       : power  :                   : 2.5V    : 4         :                
+GND                          : 105       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 106       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 107       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 108       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 109       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 110       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 111       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 112       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 113       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 114       :        :                   :         : 4         :                
+VCCINT                       : 115       : power  :                   : 1.2V    :           :                
+GND                          : 116       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 117       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 118       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 119       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 120       :        :                   :         : 4         :                
+VCCD_PLL4                    : 121       : power  :                   : 1.2V    :           :                
+GNDA4                        : 122       : gnd    :                   :         :           :                
+VCCA4                        : 123       : power  :                   : 2.5V    :           :                
+VCCIO5                       : 124       : power  :                   : 2.5V    : 5         :                
+GND                          : 125       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 126       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 127       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 128       :        :                   :         : 5         :                
+VCCINT                       : 129       : power  :                   : 1.2V    :           :                
+GND                          : 130       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 131       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 132       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 133       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 134       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 135       :        :                   :         : 5         :                
+VCCIO5                       : 136       : power  :                   : 2.5V    : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 137       :        :                   :         : 5         :                
+GND                          : 138       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 139       :        :                   :         : 5         :                
+VCCINT                       : 140       : power  :                   : 1.2V    :           :                
+GND                          : 141       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 142       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 143       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 144       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 145       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 146       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 147       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 148       :        :                   :         : 5         :                
+GND+                         : 149       :        :                   :         : 5         :                
+GND+                         : 150       :        :                   :         : 5         :                
+GND+                         : 151       :        :                   :         : 6         :                
+GND+                         : 152       :        :                   :         : 6         :                
+CONF_DONE                    : 153       :        :                   :         : 6         :                
+VCCIO6                       : 154       : power  :                   : 3.3V    : 6         :                
+MSEL0                        : 155       :        :                   :         : 6         :                
+GND                          : 156       : gnd    :                   :         :           :                
+MSEL1                        : 157       :        :                   :         : 6         :                
+MSEL2                        : 158       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 159       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 160       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 161       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 162       : output : 3.3-V LVTTL       :         : 6         : N              
+VCCINT                       : 163       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 164       :        :                   :         : 6         :                
+GND                          : 165       : gnd    :                   :         :           :                
+FPGA_LED_1                   : 166       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 167       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 168       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 169       :        :                   :         : 6         :                
+VCCIO6                       : 170       : power  :                   : 3.3V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 171       :        :                   :         : 6         :                
+GND                          : 172       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 173       :        :                   :         : 6         :                
+VCCINT                       : 174       : power  :                   : 1.2V    :           :                
+GND                          : 175       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 176       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 177       :        :                   :         : 6         :                
+VCCA2                        : 178       : power  :                   : 2.5V    :           :                
+GNDA2                        : 179       : gnd    :                   :         :           :                
+VCCD_PLL2                    : 180       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 181       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 182       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 183       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 184       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 185       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 186       :        :                   :         : 7         :                
+Data[3]                      : 187       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+Data[2]                      : 188       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+Data[1]                      : 189       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+VCCINT                       : 190       : power  :                   : 1.2V    :           :                
+GND                          : 191       : gnd    :                   :         :           :                
+VCCIO7                       : 192       : power  :                   : 3.3V    : 7         :                
+GND                          : 193       : gnd    :                   :         :           :                
+Data[0]                      : 194       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+Address[7]                   : 195       : input  : 3.3-V LVTTL       :         : 7         : Y              
+Address[0]                   : 196       : input  : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 197       :        :                   :         : 7         :                
+VCCINT                       : 198       : power  :                   : 1.2V    :           :                
+GND                          : 199       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 200       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 201       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 202       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 203       :        :                   :         : 7         :                
+VCCINT                       : 204       : power  :                   : 1.2V    :           :                
+GND                          : 205       : gnd    :                   :         :           :                
+VCCIO7                       : 206       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 207       :        :                   :         : 7         :                
+GND                          : 208       : gnd    :                   :         :           :                
+GND+                         : 209       :        :                   :         : 7         :                
+GND+                         : 210       :        :                   :         : 7         :                
+GND+                         : 211       :        :                   :         : 8         :                
+GND+                         : 212       :        :                   :         : 8         :                
+VCCIO8                       : 213       : power  :                   : 3.3V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 214       :        :                   :         : 8         :                
+GND                          : 215       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 216       :        :                   :         : 8         :                
+nOE                          : 217       : input  : 3.3-V LVTTL       :         : 8         : Y              
+nWE                          : 218       : input  : 3.3-V LVTTL       :         : 8         : Y              
+nCE                          : 219       : input  : 3.3-V LVTTL       :         : 8         : Y              
+VCCINT                       : 220       : power  :                   : 1.2V    :           :                
+Data[7]                      : 221       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : 222       : gnd    :                   :         :           :                
+Data[6]                      : 223       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+Data[5]                      : 224       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : 225       : power  :                   : 3.3V    : 8         :                
+Data[4]                      : 226       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : 227       : gnd    :                   :         :           :                
+VCCINT                       : 228       : power  :                   : 1.2V    :           :                
+GND                          : 229       : gnd    :                   :         :           :                
+Address[6]                   : 230       : input  : 3.3-V LVTTL       :         : 8         : Y              
+Address[1]                   : 231       : input  : 3.3-V LVTTL       :         : 8         : Y              
+Address[4]                   : 232       : input  : 3.3-V LVTTL       :         : 8         : Y              
+Address[3]                   : 233       : input  : 3.3-V LVTTL       :         : 8         : Y              
+Address[2]                   : 234       : input  : 3.3-V LVTTL       :         : 8         : Y              
+Address[5]                   : 235       : input  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 236       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 237       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 238       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 239       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 240       :        :                   :         : 8         :                
diff --git a/MainController/output_files/MainController.sof b/MainController/output_files/MainController.sof
new file mode 100644
index 0000000..d61fb47
Binary files /dev/null and b/MainController/output_files/MainController.sof differ
diff --git a/MainController/output_files/MainController.sta.rpt b/MainController/output_files/MainController.sta.rpt
new file mode 100644
index 0000000..4e1e56d
--- /dev/null
+++ b/MainController/output_files/MainController.sta.rpt
@@ -0,0 +1,1558 @@
+TimeQuest Timing Analyzer report for MainController
+Tue Mar 12 16:24:27 2024
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
+ 13. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
+ 15. Clock to Output Times
+ 16. Minimum Clock to Output Times
+ 17. Slow 1200mV 85C Model Metastability Report
+ 18. Slow 1200mV 0C Model Fmax Summary
+ 19. Slow 1200mV 0C Model Setup Summary
+ 20. Slow 1200mV 0C Model Hold Summary
+ 21. Slow 1200mV 0C Model Recovery Summary
+ 22. Slow 1200mV 0C Model Removal Summary
+ 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 24. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
+ 25. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
+ 26. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
+ 27. Clock to Output Times
+ 28. Minimum Clock to Output Times
+ 29. Slow 1200mV 0C Model Metastability Report
+ 30. Fast 1200mV 0C Model Setup Summary
+ 31. Fast 1200mV 0C Model Hold Summary
+ 32. Fast 1200mV 0C Model Recovery Summary
+ 33. Fast 1200mV 0C Model Removal Summary
+ 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 35. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
+ 36. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
+ 37. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
+ 38. Clock to Output Times
+ 39. Minimum Clock to Output Times
+ 40. Fast 1200mV 0C Model Metastability Report
+ 41. Multicorner Timing Analysis Summary
+ 42. Clock to Output Times
+ 43. Minimum Clock to Output Times
+ 44. Board Trace Model Assignments
+ 45. Input Transition Times
+ 46. Slow Corner Signal Integrity Metrics
+ 47. Fast Corner Signal Integrity Metrics
+ 48. Setup Transfers
+ 49. Hold Transfers
+ 50. Report TCCS
+ 51. Report RSKM
+ 52. Unconstrained Paths
+ 53. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                        ;
++--------------------+-----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name      ; MainController                                      ;
+; Device Family      ; Cyclone III                                         ;
+; Device Name        ; EP3C25Q240C8                                        ;
+; Timing Models      ; Final                                               ;
+; Delay Model        ; Combined                                            ;
+; Rise/Fall Delays   ; Enabled                                             ;
++--------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                               ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; FPGA_CLK   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { FPGA_CLK } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+
+
++--------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary               ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 201.86 MHz ; 201.86 MHz      ; FPGA_CLK   ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; FPGA_CLK ; -3.954 ; -84.790         ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; FPGA_CLK ; 0.435 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++----------+--------+-------------------------------+
+; Clock    ; Slack  ; End Point TNS                 ;
++----------+--------+-------------------------------+
+; FPGA_CLK ; -3.000 ; -40.175                       ;
++----------+--------+-------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.954 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.876      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.947 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.869      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.253      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.809 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 4.241      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.743 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.665      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.674 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.596      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.665 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.587      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.610 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.532      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.557 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.479      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.978      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.535 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.569     ; 3.967      ;
+; -3.484 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.876      ;
+; -3.484 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.876      ;
+; -3.484 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.876      ;
+; -3.484 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.876      ;
+; -3.477 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.869      ;
+; -3.477 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.869      ;
+; -3.477 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.869      ;
+; -3.477 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.391      ; 4.869      ;
+; -3.475 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.397      ;
+; -3.475 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.397      ;
+; -3.475 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.397      ;
+; -3.475 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.079     ; 4.397      ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; 0.435 ; LedBlink:inst2|ledBuf      ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 0.746      ;
+; 0.611 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.392      ;
+; 0.612 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.393      ;
+; 0.620 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.402      ;
+; 0.629 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.411      ;
+; 0.629 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.410      ;
+; 0.726 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.037      ;
+; 0.729 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.040      ;
+; 0.729 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.039      ;
+; 0.730 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.041      ;
+; 0.730 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.041      ;
+; 0.731 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.041      ;
+; 0.731 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.041      ;
+; 0.732 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.042      ;
+; 0.733 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.043      ;
+; 0.742 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.523      ;
+; 0.744 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.054      ;
+; 0.746 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.037      ;
+; 0.746 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.056      ;
+; 0.748 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
+; 0.749 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
+; 0.750 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.041      ;
+; 0.751 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.532      ;
+; 0.758 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.540      ;
+; 0.760 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.541      ;
+; 0.760 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.542      ;
+; 0.763 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.054      ;
+; 0.766 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.057      ;
+; 0.767 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.549      ;
+; 0.769 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.551      ;
+; 0.769 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.550      ;
+; 0.771 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.062      ;
+; 0.776 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.558      ;
+; 0.785 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.567      ;
+; 0.809 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.590      ;
+; 0.858 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.639      ;
+; 0.882 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.663      ;
+; 0.891 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.672      ;
+; 0.892 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.673      ;
+; 0.898 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.680      ;
+; 0.900 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.682      ;
+; 0.900 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.681      ;
+; 0.906 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.688      ;
+; 0.907 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.689      ;
+; 0.909 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.690      ;
+; 0.915 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.697      ;
+; 0.916 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.697      ;
+; 0.916 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.698      ;
+; 0.925 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.707      ;
+; 0.959 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.250      ;
+; 0.960 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.741      ;
+; 0.963 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.744      ;
+; 0.966 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.257      ;
+; 0.973 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.264      ;
+; 0.978 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.269      ;
+; 0.979 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.270      ;
+; 0.986 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.767      ;
+; 1.023 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.804      ;
+; 1.032 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.813      ;
+; 1.038 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.820      ;
+; 1.046 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.828      ;
+; 1.055 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.837      ;
+; 1.056 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.838      ;
+; 1.057 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.838      ;
+; 1.081 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.392      ;
+; 1.085 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.395      ;
+; 1.085 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.395      ;
+; 1.090 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.400      ;
+; 1.091 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.402      ;
+; 1.093 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.403      ;
+; 1.094 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.404      ;
+; 1.098 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.408      ;
+; 1.099 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.409      ;
+; 1.100 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.411      ;
+; 1.103 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.413      ;
+; 1.103 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.884      ;
+; 1.110 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
+; 1.117 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.898      ;
+; 1.118 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
+; 1.122 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.903      ;
+; 1.126 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.417      ;
+; 1.127 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.418      ;
+; 1.136 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.427      ;
+; 1.138 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.919      ;
+; 1.163 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.944      ;
+; 1.165 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.571      ; 1.948      ;
+; 1.167 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.477      ;
+; 1.172 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.953      ;
+; 1.186 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.968      ;
+; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.977      ;
+; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.977      ;
+; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.570      ; 1.977      ;
+; 1.197 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.569      ; 1.978      ;
+; 1.212 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.523      ;
+; 1.216 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.526      ;
+; 1.216 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.526      ;
+; 1.221 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.532      ;
+; 1.223 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.534      ;
+; 1.225 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.098      ; 1.535      ;
+; 1.231 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.099      ; 1.542      ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                              ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                         ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                       ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; 0.258  ; 0.446        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; 0.265  ; 0.453        ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.325  ; 0.545        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; 0.325  ; 0.545        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; 0.325  ; 0.545        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; 0.325  ; 0.545        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; 0.325  ; 0.545        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; 0.326  ; 0.546        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; 0.332  ; 0.552        ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; 0.385  ; 0.385        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o               ;
+; 0.395  ; 0.395        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0] ;
+; 0.395  ; 0.395        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk   ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[0]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[15]|clk          ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[16]|clk          ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[17]|clk          ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[18]|clk          ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[1]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[2]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[4]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[5]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[7]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[8]|clk           ;
+; 0.398  ; 0.398        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[9]|clk           ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[10]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[11]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[12]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[13]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[14]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[19]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[20]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[21]|clk          ;
+; 0.405  ; 0.405        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[22]|clk          ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 7.359 ; 7.560 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 7.176 ; 7.373 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary               ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 214.5 MHz ; 214.5 MHz       ; FPGA_CLK   ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; FPGA_CLK ; -3.662 ; -77.889        ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; FPGA_CLK ; 0.384 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++----------+--------+------------------------------+
+; Clock    ; Slack  ; End Point TNS                ;
++----------+--------+------------------------------+
+; FPGA_CLK ; -3.000 ; -40.175                      ;
++----------+--------+------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                 ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.662 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.593      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.657 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.588      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.023      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.553 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 4.014      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.484 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.415      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.394 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.325      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.386 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.317      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.361 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.292      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.750      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.285 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.216      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.279 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.541     ; 3.740      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.227 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.071     ; 4.158      ;
+; -3.210 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.381      ; 4.593      ;
+; -3.210 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.381      ; 4.593      ;
+; -3.210 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.381      ; 4.593      ;
+; -3.210 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.381      ; 4.593      ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                 ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; 0.384 ; LedBlink:inst2|ledBuf      ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.669      ;
+; 0.545 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.283      ;
+; 0.546 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.282      ;
+; 0.551 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.287      ;
+; 0.560 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.298      ;
+; 0.563 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.299      ;
+; 0.643 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.379      ;
+; 0.651 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.389      ;
+; 0.667 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.404      ;
+; 0.667 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.405      ;
+; 0.670 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.406      ;
+; 0.676 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.089      ; 0.960      ;
+; 0.678 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.963      ;
+; 0.679 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.089      ; 0.963      ;
+; 0.679 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.964      ;
+; 0.679 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.964      ;
+; 0.680 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.089      ; 0.964      ;
+; 0.680 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.418      ;
+; 0.680 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.418      ;
+; 0.682 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.420      ;
+; 0.682 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.089      ; 0.966      ;
+; 0.682 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.967      ;
+; 0.683 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.968      ;
+; 0.684 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.421      ;
+; 0.689 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.974      ;
+; 0.693 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 0.978      ;
+; 0.694 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.960      ;
+; 0.694 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.430      ;
+; 0.697 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
+; 0.697 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.435      ;
+; 0.698 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.964      ;
+; 0.699 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.965      ;
+; 0.708 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.974      ;
+; 0.713 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.979      ;
+; 0.716 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.982      ;
+; 0.764 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.501      ;
+; 0.773 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.511      ;
+; 0.785 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.523      ;
+; 0.789 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.527      ;
+; 0.789 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.526      ;
+; 0.789 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.525      ;
+; 0.791 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.527      ;
+; 0.791 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.528      ;
+; 0.795 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.531      ;
+; 0.802 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.540      ;
+; 0.802 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.540      ;
+; 0.806 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.543      ;
+; 0.810 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.548      ;
+; 0.819 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.557      ;
+; 0.826 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.562      ;
+; 0.868 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.134      ;
+; 0.872 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.138      ;
+; 0.872 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.138      ;
+; 0.884 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.150      ;
+; 0.886 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.622      ;
+; 0.892 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.158      ;
+; 0.892 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.628      ;
+; 0.895 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.633      ;
+; 0.899 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.635      ;
+; 0.907 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.645      ;
+; 0.911 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.647      ;
+; 0.916 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.653      ;
+; 0.924 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.662      ;
+; 0.932 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.670      ;
+; 0.997 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.282      ;
+; 0.998 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.283      ;
+; 0.999 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.089      ; 1.283      ;
+; 1.001 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.286      ;
+; 1.002 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.287      ;
+; 1.002 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.287      ;
+; 1.003 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.288      ;
+; 1.007 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.744      ;
+; 1.013 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.298      ;
+; 1.013 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.298      ;
+; 1.013 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.298      ;
+; 1.013 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.750      ;
+; 1.016 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.301      ;
+; 1.018 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.284      ;
+; 1.018 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.754      ;
+; 1.020 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.756      ;
+; 1.029 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.767      ;
+; 1.030 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
+; 1.030 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
+; 1.031 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.316      ;
+; 1.032 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.769      ;
+; 1.035 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.771      ;
+; 1.038 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.304      ;
+; 1.038 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.542      ; 1.775      ;
+; 1.039 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.777      ;
+; 1.047 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.313      ;
+; 1.084 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.541      ; 1.820      ;
+; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.823      ;
+; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.823      ;
+; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.543      ; 1.823      ;
+; 1.094 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.379      ;
+; 1.100 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.385      ;
+; 1.100 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.385      ;
+; 1.118 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.384      ;
+; 1.119 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.404      ;
+; 1.120 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.090      ; 1.405      ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                               ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                         ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                       ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; -1.487 ; 1.000        ; 2.487          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; 0.253  ; 0.437        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; 0.293  ; 0.509        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; 0.343  ; 0.559        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; 0.385  ; 0.385        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o               ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[0]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[15]|clk          ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[16]|clk          ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[17]|clk          ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[18]|clk          ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[1]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[2]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[4]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[5]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[7]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[8]|clk           ;
+; 0.386  ; 0.386        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[9]|clk           ;
+; 0.388  ; 0.388        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0] ;
+; 0.388  ; 0.388        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk   ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[10]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[11]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[12]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[13]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[14]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[19]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[20]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[21]|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[22]|clk          ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 6.960 ; 7.231 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 6.795 ; 7.059 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; FPGA_CLK ; -1.072 ; -20.939        ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; FPGA_CLK ; 0.179 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++----------+--------+------------------------------+
+; Clock    ; Slack  ; End Point TNS                ;
++----------+--------+------------------------------+
+; FPGA_CLK ; -3.000 ; -35.949                      ;
++----------+--------+------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                 ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.072 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.022      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.071 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 2.021      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.775      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -1.004 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.757      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.985 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.935      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.969 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.919      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.927 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.877      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.906 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.856      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.894 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.647      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.234     ; 1.645      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.889 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; -0.037     ; 1.839      ;
+; -0.883 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.152      ; 2.022      ;
+; -0.883 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.152      ; 2.022      ;
+; -0.883 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.152      ; 2.022      ;
+; -0.883 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 1.000        ; 0.152      ; 2.022      ;
++--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                 ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                  ; To Node                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+; 0.179 ; LedBlink:inst2|ledBuf      ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.044      ; 0.307      ;
+; 0.248 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.566      ;
+; 0.250 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.568      ;
+; 0.259 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.577      ;
+; 0.262 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.580      ;
+; 0.263 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.581      ;
+; 0.288 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.417      ;
+; 0.289 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.418      ;
+; 0.289 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.418      ;
+; 0.290 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.419      ;
+; 0.290 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.419      ;
+; 0.291 ; LedBlink:inst2|counter[6]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.420      ;
+; 0.291 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.420      ;
+; 0.292 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.421      ;
+; 0.292 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.421      ;
+; 0.296 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.417      ;
+; 0.296 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.425      ;
+; 0.298 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[5]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.419      ;
+; 0.298 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.427      ;
+; 0.299 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.420      ;
+; 0.299 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.305 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.308 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.429      ;
+; 0.311 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.629      ;
+; 0.314 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.632      ;
+; 0.319 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.637      ;
+; 0.322 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.640      ;
+; 0.325 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.643      ;
+; 0.326 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.644      ;
+; 0.328 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.646      ;
+; 0.329 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.647      ;
+; 0.332 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.650      ;
+; 0.334 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.652      ;
+; 0.337 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.655      ;
+; 0.340 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.658      ;
+; 0.371 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[2]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.492      ;
+; 0.371 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.492      ;
+; 0.373 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[1]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.494      ;
+; 0.376 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[4]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.497      ;
+; 0.377 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.695      ;
+; 0.380 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[0]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.501      ;
+; 0.380 ; LedBlink:inst2|counter[9]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.698      ;
+; 0.382 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.700      ;
+; 0.385 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.703      ;
+; 0.388 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.706      ;
+; 0.388 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.706      ;
+; 0.389 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.707      ;
+; 0.389 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.707      ;
+; 0.391 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.709      ;
+; 0.392 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.710      ;
+; 0.392 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.710      ;
+; 0.395 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.713      ;
+; 0.398 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[3]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.716      ;
+; 0.400 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.718      ;
+; 0.401 ; LedBlink:inst2|counter[2]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.719      ;
+; 0.403 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.721      ;
+; 0.437 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.566      ;
+; 0.439 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.568      ;
+; 0.440 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.569      ;
+; 0.445 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.763      ;
+; 0.445 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.574      ;
+; 0.447 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.576      ;
+; 0.447 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.576      ;
+; 0.448 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.766      ;
+; 0.450 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.579      ;
+; 0.450 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.579      ;
+; 0.450 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.579      ;
+; 0.450 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.579      ;
+; 0.450 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.579      ;
+; 0.451 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.769      ;
+; 0.452 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[11] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.770      ;
+; 0.453 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.582      ;
+; 0.454 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.574      ;
+; 0.455 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.773      ;
+; 0.455 ; LedBlink:inst2|counter[7]  ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.773      ;
+; 0.457 ; LedBlink:inst2|counter[8]  ; LedBlink:inst2|counter[9]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.578      ;
+; 0.457 ; LedBlink:inst2|counter[1]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.775      ;
+; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.578      ;
+; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.776      ;
+; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.586      ;
+; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.784      ;
+; 0.467 ; LedBlink:inst2|counter[0]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.785      ;
+; 0.469 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.589      ;
+; 0.472 ; LedBlink:inst2|counter[4]  ; LedBlink:inst2|counter[10] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.790      ;
+; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.813      ;
+; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.813      ;
+; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.813      ;
+; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.813      ;
+; 0.500 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.629      ;
+; 0.502 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.631      ;
+; 0.503 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.632      ;
+; 0.503 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.632      ;
+; 0.505 ; LedBlink:inst2|counter[3]  ; LedBlink:inst2|counter[6]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.634      ;
+; 0.506 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.635      ;
+; 0.510 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[7]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.631      ;
+; 0.511 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.829      ;
+; 0.513 ; LedBlink:inst2|counter[5]  ; LedBlink:inst2|counter[8]  ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.634      ;
+; 0.513 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.045      ; 0.642      ;
+; 0.514 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.234      ; 0.832      ;
++-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                               ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                         ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; -0.261 ; -0.077       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[14]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[19]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[20]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[21]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[22]     ;
+; -0.260 ; -0.076       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[23]     ;
+; -0.259 ; -0.075       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; -0.259 ; -0.075       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; -0.259 ; -0.075       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; -0.259 ; -0.075       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; -0.232 ; -0.048       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; -0.232 ; -0.048       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; -0.232 ; -0.048       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; -0.232 ; -0.048       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; -0.231 ; -0.047       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; -0.081 ; -0.081       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|ledBuf|clk               ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[12]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[13]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[14]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[19]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[20]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[21]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[22]|clk          ;
+; -0.080 ; -0.080       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[23]|clk          ;
+; -0.079 ; -0.079       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[10]|clk          ;
+; -0.079 ; -0.079       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[11]|clk          ;
+; -0.079 ; -0.079       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[3]|clk           ;
+; -0.079 ; -0.079       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[6]|clk           ;
+; -0.053 ; -0.053       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o               ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[0]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[15]|clk          ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[16]|clk          ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[17]|clk          ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[18]|clk          ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[1]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[2]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[4]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[5]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[7]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[8]|clk           ;
+; -0.052 ; -0.052       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; inst2|counter[9]|clk           ;
+; -0.041 ; -0.041       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0] ;
+; -0.041 ; -0.041       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i               ;
+; 0.829  ; 1.045        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[15]     ;
+; 0.829  ; 1.045        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[16]     ;
+; 0.829  ; 1.045        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[17]     ;
+; 0.829  ; 1.045        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[18]     ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[0]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[1]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[2]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[4]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[5]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[7]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[8]      ;
+; 0.830  ; 1.046        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[9]      ;
+; 0.857  ; 1.073        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[10]     ;
+; 0.857  ; 1.073        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[11]     ;
+; 0.857  ; 1.073        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[3]      ;
+; 0.857  ; 1.073        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[6]      ;
+; 0.857  ; 1.073        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|ledBuf          ;
+; 0.858  ; 1.074        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[12]     ;
+; 0.858  ; 1.074        ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; LedBlink:inst2|counter[13]     ;
++--------+--------------+----------------+------------------+----------+------------+--------------------------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 3.617 ; 3.589 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 3.532 ; 3.507 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+---------+-------+----------+---------+---------------------+
+; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -3.954  ; 0.179 ; N/A      ; N/A     ; -3.000              ;
+;  FPGA_CLK        ; -3.954  ; 0.179 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -84.79  ; 0.0   ; 0.0      ; 0.0     ; -40.175             ;
+;  FPGA_CLK        ; -84.790 ; 0.000 ; N/A      ; N/A     ; -40.175             ;
++------------------+---------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 7.359 ; 7.560 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; FPGA_LED_1 ; FPGA_CLK   ; 3.532 ; 3.507 ; Rise       ; FPGA_CLK        ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; FPGA_LED_1    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Data[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; Address[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Address[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nOE                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nWE                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nCE                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[7]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[6]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[5]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[4]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[3]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; Data[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FPGA_CLK                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; FPGA_LED_1    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
+; Data[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
+; Data[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; Data[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0964 V           ; 0.164 V                              ; 0.127 V                              ; 3.14e-10 s                  ; 3.99e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0964 V          ; 0.164 V                             ; 0.127 V                             ; 3.14e-10 s                 ; 3.99e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; FPGA_LED_1    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
+; Data[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
+; Data[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; Data[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.53e-08 V                   ; 3.65 V              ; -0.246 V            ; 0.406 V                              ; 0.305 V                              ; 1.57e-10 s                  ; 2.13e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.53e-08 V                  ; 3.65 V             ; -0.246 V           ; 0.406 V                             ; 0.305 V                             ; 1.57e-10 s                 ; 2.13e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; FPGA_CLK   ; FPGA_CLK ; 976      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; FPGA_CLK   ; FPGA_CLK ; 976      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 0     ; 0    ;
+; Unconstrained Input Port Paths  ; 0     ; 0    ;
+; Unconstrained Output Ports      ; 1     ; 1    ;
+; Unconstrained Output Port Paths ; 1     ; 1    ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Tue Mar 12 16:24:25 2024
+Info: Command: quartus_sta MainController -c MainController
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'MainController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name FPGA_CLK FPGA_CLK
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.954
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.954             -84.790 FPGA_CLK 
+Info (332146): Worst-case hold slack is 0.435
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.435               0.000 FPGA_CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -40.175 FPGA_CLK 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.662
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.662             -77.889 FPGA_CLK 
+Info (332146): Worst-case hold slack is 0.384
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.384               0.000 FPGA_CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -40.175 FPGA_CLK 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.072
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.072             -20.939 FPGA_CLK 
+Info (332146): Worst-case hold slack is 0.179
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.179               0.000 FPGA_CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -35.949 FPGA_CLK 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 4700 megabytes
+    Info: Processing ended: Tue Mar 12 16:24:27 2024
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/MainController/output_files/MainController.sta.summary b/MainController/output_files/MainController.sta.summary
new file mode 100644
index 0000000..2d5126c
--- /dev/null
+++ b/MainController/output_files/MainController.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'FPGA_CLK'
+Slack : -3.954
+TNS   : -84.790
+
+Type  : Slow 1200mV 85C Model Hold 'FPGA_CLK'
+Slack : 0.435
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'FPGA_CLK'
+Slack : -3.000
+TNS   : -40.175
+
+Type  : Slow 1200mV 0C Model Setup 'FPGA_CLK'
+Slack : -3.662
+TNS   : -77.889
+
+Type  : Slow 1200mV 0C Model Hold 'FPGA_CLK'
+Slack : 0.384
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
+Slack : -3.000
+TNS   : -40.175
+
+Type  : Fast 1200mV 0C Model Setup 'FPGA_CLK'
+Slack : -1.072
+TNS   : -20.939
+
+Type  : Fast 1200mV 0C Model Hold 'FPGA_CLK'
+Slack : 0.179
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'FPGA_CLK'
+Slack : -3.000
+TNS   : -35.949
+
+------------------------------------------------------------
diff --git a/MainController/simulation/modelsim/MainController.sft b/MainController/simulation/modelsim/MainController.sft
new file mode 100644
index 0000000..ff6cea1
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -8 1.2V 85 Model"} {MainController_8_1200mv_85c_slow.vho MainController_8_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -8 1.2V 0 Model"} {MainController_8_1200mv_0c_slow.vho MainController_8_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {MainController_min_1200mv_0c_fast.vho MainController_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/MainController/simulation/modelsim/MainController.vho b/MainController/simulation/modelsim/MainController.vho
index ef7443d..d2c6f05 100644
--- a/MainController/simulation/modelsim/MainController.vho
+++ b/MainController/simulation/modelsim/MainController.vho
@@ -16,7 +16,7 @@
 -- PROGRAM "Quartus II 64-Bit"
 -- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
 
--- DATE "03/04/2024 16:45:11"
+-- DATE "03/12/2024 16:24:29"
 
 -- 
 -- Device: Altera EP3C25Q240C8 Package PQFP240
@@ -26,49 +26,47 @@
 -- This VHDL file should be used for ModelSim-Altera (VHDL) only
 -- 
 
+LIBRARY ALTERA;
 LIBRARY CYCLONEIII;
 LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
 USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
 USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY 	MainController IS
     PORT (
-	Clk : IN std_logic;
-	ClkRAM : IN std_logic;
-	WR : IN std_logic;
-	AddressRAM : IN std_logic_vector(7 DOWNTO 0);
-	DataRAM : IN std_logic_vector(15 DOWNTO 0)
+	FPGA_LED_1 : OUT std_logic;
+	FPGA_CLK : IN std_logic;
+	Data : INOUT std_logic_vector(7 DOWNTO 0);
+	Address : IN std_logic_vector(7 DOWNTO 0);
+	nOE : IN std_logic;
+	nWE : IN std_logic;
+	nCE : IN std_logic
 	);
 END MainController;
 
 -- Design Ports Information
--- Clk	=>  Location: PIN_81,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- ClkRAM	=>  Location: PIN_127,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- WR	=>  Location: PIN_98,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[7]	=>  Location: PIN_41,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[6]	=>  Location: PIN_132,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[5]	=>  Location: PIN_230,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[4]	=>  Location: PIN_135,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[3]	=>  Location: PIN_65,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[2]	=>  Location: PIN_181,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[1]	=>  Location: PIN_64,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- AddressRAM[0]	=>  Location: PIN_173,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[15]	=>  Location: PIN_103,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[14]	=>  Location: PIN_145,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[13]	=>  Location: PIN_38,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[12]	=>  Location: PIN_144,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[11]	=>  Location: PIN_160,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[10]	=>  Location: PIN_149,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[9]	=>  Location: PIN_150,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[8]	=>  Location: PIN_133,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[7]	=>  Location: PIN_151,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[6]	=>  Location: PIN_152,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[5]	=>  Location: PIN_197,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[4]	=>  Location: PIN_113,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[3]	=>  Location: PIN_161,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[2]	=>  Location: PIN_168,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[1]	=>  Location: PIN_166,	 I/O Standard: 2.5 V,	 Current Strength: Default
--- DataRAM[0]	=>  Location: PIN_119,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- FPGA_LED_1	=>  Location: PIN_166,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Address[7]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[6]	=>  Location: PIN_230,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[5]	=>  Location: PIN_235,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[4]	=>  Location: PIN_232,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[3]	=>  Location: PIN_233,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[2]	=>  Location: PIN_234,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[1]	=>  Location: PIN_231,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[0]	=>  Location: PIN_196,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nOE	=>  Location: PIN_217,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nWE	=>  Location: PIN_218,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nCE	=>  Location: PIN_219,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Data[7]	=>  Location: PIN_221,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[6]	=>  Location: PIN_223,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[5]	=>  Location: PIN_224,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[4]	=>  Location: PIN_226,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[3]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[2]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[1]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[0]	=>  Location: PIN_194,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- FPGA_CLK	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
 
 
 ARCHITECTURE structure OF MainController IS
@@ -81,346 +79,1448 @@ SIGNAL devpor : std_logic := '1';
 SIGNAL ww_devoe : std_logic;
 SIGNAL ww_devclrn : std_logic;
 SIGNAL ww_devpor : std_logic;
-SIGNAL ww_Clk : std_logic;
-SIGNAL ww_ClkRAM : std_logic;
-SIGNAL ww_WR : std_logic;
-SIGNAL ww_AddressRAM : std_logic_vector(7 DOWNTO 0);
-SIGNAL ww_DataRAM : std_logic_vector(15 DOWNTO 0);
-SIGNAL \Clk~input_o\ : std_logic;
-SIGNAL \ClkRAM~input_o\ : std_logic;
-SIGNAL \WR~input_o\ : std_logic;
-SIGNAL \AddressRAM[7]~input_o\ : std_logic;
-SIGNAL \AddressRAM[6]~input_o\ : std_logic;
-SIGNAL \AddressRAM[5]~input_o\ : std_logic;
-SIGNAL \AddressRAM[4]~input_o\ : std_logic;
-SIGNAL \AddressRAM[3]~input_o\ : std_logic;
-SIGNAL \AddressRAM[2]~input_o\ : std_logic;
-SIGNAL \AddressRAM[1]~input_o\ : std_logic;
-SIGNAL \AddressRAM[0]~input_o\ : std_logic;
-SIGNAL \DataRAM[15]~input_o\ : std_logic;
-SIGNAL \DataRAM[14]~input_o\ : std_logic;
-SIGNAL \DataRAM[13]~input_o\ : std_logic;
-SIGNAL \DataRAM[12]~input_o\ : std_logic;
-SIGNAL \DataRAM[11]~input_o\ : std_logic;
-SIGNAL \DataRAM[10]~input_o\ : std_logic;
-SIGNAL \DataRAM[9]~input_o\ : std_logic;
-SIGNAL \DataRAM[8]~input_o\ : std_logic;
-SIGNAL \DataRAM[7]~input_o\ : std_logic;
-SIGNAL \DataRAM[6]~input_o\ : std_logic;
-SIGNAL \DataRAM[5]~input_o\ : std_logic;
-SIGNAL \DataRAM[4]~input_o\ : std_logic;
-SIGNAL \DataRAM[3]~input_o\ : std_logic;
-SIGNAL \DataRAM[2]~input_o\ : std_logic;
-SIGNAL \DataRAM[1]~input_o\ : std_logic;
-SIGNAL \DataRAM[0]~input_o\ : std_logic;
+SIGNAL ww_FPGA_LED_1 : std_logic;
+SIGNAL ww_FPGA_CLK : std_logic;
+SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_nOE : std_logic;
+SIGNAL ww_nWE : std_logic;
+SIGNAL ww_nCE : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Address[7]~input_o\ : std_logic;
+SIGNAL \Address[6]~input_o\ : std_logic;
+SIGNAL \Address[5]~input_o\ : std_logic;
+SIGNAL \Address[4]~input_o\ : std_logic;
+SIGNAL \Address[3]~input_o\ : std_logic;
+SIGNAL \Address[2]~input_o\ : std_logic;
+SIGNAL \Address[1]~input_o\ : std_logic;
+SIGNAL \Address[0]~input_o\ : std_logic;
+SIGNAL \nOE~input_o\ : std_logic;
+SIGNAL \nWE~input_o\ : std_logic;
+SIGNAL \nCE~input_o\ : std_logic;
+SIGNAL \Data[7]~input_o\ : std_logic;
+SIGNAL \Data[6]~input_o\ : std_logic;
+SIGNAL \Data[5]~input_o\ : std_logic;
+SIGNAL \Data[4]~input_o\ : std_logic;
+SIGNAL \Data[3]~input_o\ : std_logic;
+SIGNAL \Data[2]~input_o\ : std_logic;
+SIGNAL \Data[1]~input_o\ : std_logic;
+SIGNAL \Data[0]~input_o\ : std_logic;
+SIGNAL \Data[7]~output_o\ : std_logic;
+SIGNAL \Data[6]~output_o\ : std_logic;
+SIGNAL \Data[5]~output_o\ : std_logic;
+SIGNAL \Data[4]~output_o\ : std_logic;
+SIGNAL \Data[3]~output_o\ : std_logic;
+SIGNAL \Data[2]~output_o\ : std_logic;
+SIGNAL \Data[1]~output_o\ : std_logic;
+SIGNAL \Data[0]~output_o\ : std_logic;
+SIGNAL \FPGA_LED_1~output_o\ : std_logic;
+SIGNAL \FPGA_CLK~input_o\ : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
+SIGNAL \inst2|counter[0]~25\ : std_logic;
+SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
+SIGNAL \inst2|counter[1]~27\ : std_logic;
+SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
+SIGNAL \inst2|counter[2]~29\ : std_logic;
+SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
+SIGNAL \inst2|counter[3]~31\ : std_logic;
+SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
+SIGNAL \inst2|counter[4]~33\ : std_logic;
+SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
+SIGNAL \inst2|counter[5]~35\ : std_logic;
+SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
+SIGNAL \inst2|counter[6]~37\ : std_logic;
+SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
+SIGNAL \inst2|counter[7]~39\ : std_logic;
+SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
+SIGNAL \inst2|counter[8]~41\ : std_logic;
+SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
+SIGNAL \inst2|counter[9]~43\ : std_logic;
+SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
+SIGNAL \inst2|counter[10]~45\ : std_logic;
+SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
+SIGNAL \inst2|counter[11]~47\ : std_logic;
+SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
+SIGNAL \inst2|counter[12]~49\ : std_logic;
+SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
+SIGNAL \inst2|counter[13]~51\ : std_logic;
+SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
+SIGNAL \inst2|counter[14]~53\ : std_logic;
+SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
+SIGNAL \inst2|counter[15]~55\ : std_logic;
+SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
+SIGNAL \inst2|counter[16]~57\ : std_logic;
+SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
+SIGNAL \inst2|counter[17]~59\ : std_logic;
+SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
+SIGNAL \inst2|counter[18]~61\ : std_logic;
+SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
+SIGNAL \inst2|counter[19]~63\ : std_logic;
+SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
+SIGNAL \inst2|counter[20]~65\ : std_logic;
+SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
+SIGNAL \inst2|counter[21]~67\ : std_logic;
+SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
+SIGNAL \inst2|counter[22]~69\ : std_logic;
+SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~q\ : std_logic;
+SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
+SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;
 
 BEGIN
 
-ww_Clk <= Clk;
-ww_ClkRAM <= ClkRAM;
-ww_WR <= WR;
-ww_AddressRAM <= AddressRAM;
-ww_DataRAM <= DataRAM;
+FPGA_LED_1 <= ww_FPGA_LED_1;
+ww_FPGA_CLK <= FPGA_CLK;
+ww_Address <= Address;
+ww_nOE <= nOE;
+ww_nWE <= nWE;
+ww_nCE <= nCE;
 ww_devoe <= devoe;
 ww_devclrn <= devclrn;
 ww_devpor <= devpor;
 
--- Location: IOIBUF_X14_Y0_N8
-\Clk~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_Clk,
-	o => \Clk~input_o\);
+\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
+\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\;
+\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;
 
--- Location: IOIBUF_X53_Y6_N15
-\ClkRAM~input\ : cycloneiii_io_ibuf
+-- Location: IOOBUF_X18_Y34_N2
+\Data[7]~output\ : cycloneiii_io_obuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
-	simulate_z_as => "z")
+	open_drain_output => "true")
 -- pragma translate_on
 PORT MAP (
-	i => ww_ClkRAM,
-	o => \ClkRAM~input_o\);
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[7]~output_o\);
 
--- Location: IOIBUF_X34_Y0_N22
-\WR~input\ : cycloneiii_io_ibuf
+-- Location: IOOBUF_X18_Y34_N23
+\Data[6]~output\ : cycloneiii_io_obuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
-	simulate_z_as => "z")
+	open_drain_output => "true")
 -- pragma translate_on
 PORT MAP (
-	i => ww_WR,
-	o => \WR~input_o\);
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[6]~output_o\);
 
--- Location: IOIBUF_X0_Y12_N1
-\AddressRAM[7]~input\ : cycloneiii_io_ibuf
+-- Location: IOOBUF_X16_Y34_N2
+\Data[5]~output\ : cycloneiii_io_obuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
-	simulate_z_as => "z")
+	open_drain_output => "true")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(7),
-	o => \AddressRAM[7]~input_o\);
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[5]~output_o\);
 
--- Location: IOIBUF_X53_Y9_N15
-\AddressRAM[6]~input\ : cycloneiii_io_ibuf
+-- Location: IOOBUF_X16_Y34_N16
+\Data[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[4]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N9
+\Data[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[3]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N16
+\Data[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[2]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N23
+\Data[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[1]~output_o\);
+
+-- Location: IOOBUF_X40_Y34_N9
+\Data[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[0]~output_o\);
+
+-- Location: IOOBUF_X53_Y22_N2
+\FPGA_LED_1~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|ALT_INV_ledBuf~q\,
+	devoe => ww_devoe,
+	o => \FPGA_LED_1~output_o\);
+
+-- Location: IOIBUF_X0_Y16_N1
+\FPGA_CLK~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(6),
-	o => \AddressRAM[6]~input_o\);
+	i => ww_FPGA_CLK,
+	o => \FPGA_CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \FPGA_CLK~inputclkctrl_outclk\);
+
+-- Location: LCCOMB_X51_Y14_N8
+\inst2|counter[0]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
+-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101010110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(0),
+	datad => VCC,
+	combout => \inst2|counter[0]~24_combout\,
+	cout => \inst2|counter[0]~25\);
+
+-- Location: FF_X51_Y14_N9
+\inst2|counter[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[0]~24_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(0));
+
+-- Location: LCCOMB_X51_Y14_N10
+\inst2|counter[1]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
+-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(1),
+	datad => VCC,
+	cin => \inst2|counter[0]~25\,
+	combout => \inst2|counter[1]~26_combout\,
+	cout => \inst2|counter[1]~27\);
+
+-- Location: FF_X51_Y14_N11
+\inst2|counter[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[1]~26_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(1));
+
+-- Location: LCCOMB_X51_Y14_N12
+\inst2|counter[2]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
+-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(2),
+	datad => VCC,
+	cin => \inst2|counter[1]~27\,
+	combout => \inst2|counter[2]~28_combout\,
+	cout => \inst2|counter[2]~29\);
+
+-- Location: FF_X51_Y14_N13
+\inst2|counter[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[2]~28_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(2));
+
+-- Location: LCCOMB_X51_Y14_N14
+\inst2|counter[3]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
+-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(3),
+	datad => VCC,
+	cin => \inst2|counter[2]~29\,
+	combout => \inst2|counter[3]~30_combout\,
+	cout => \inst2|counter[3]~31\);
+
+-- Location: FF_X51_Y14_N15
+\inst2|counter[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[3]~30_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(3));
+
+-- Location: LCCOMB_X51_Y14_N16
+\inst2|counter[4]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
+-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datad => VCC,
+	cin => \inst2|counter[3]~31\,
+	combout => \inst2|counter[4]~32_combout\,
+	cout => \inst2|counter[4]~33\);
+
+-- Location: FF_X51_Y14_N17
+\inst2|counter[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[4]~32_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(4));
+
+-- Location: LCCOMB_X51_Y14_N18
+\inst2|counter[5]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
+-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(5),
+	datad => VCC,
+	cin => \inst2|counter[4]~33\,
+	combout => \inst2|counter[5]~34_combout\,
+	cout => \inst2|counter[5]~35\);
+
+-- Location: FF_X51_Y14_N19
+\inst2|counter[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[5]~34_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(5));
+
+-- Location: LCCOMB_X51_Y14_N20
+\inst2|counter[6]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
+-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(6),
+	datad => VCC,
+	cin => \inst2|counter[5]~35\,
+	combout => \inst2|counter[6]~36_combout\,
+	cout => \inst2|counter[6]~37\);
+
+-- Location: FF_X51_Y14_N21
+\inst2|counter[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[6]~36_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(6));
+
+-- Location: LCCOMB_X51_Y14_N22
+\inst2|counter[7]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
+-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(7),
+	datad => VCC,
+	cin => \inst2|counter[6]~37\,
+	combout => \inst2|counter[7]~38_combout\,
+	cout => \inst2|counter[7]~39\);
+
+-- Location: FF_X51_Y14_N23
+\inst2|counter[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[7]~38_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(7));
+
+-- Location: LCCOMB_X51_Y14_N24
+\inst2|counter[8]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
+-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(8),
+	datad => VCC,
+	cin => \inst2|counter[7]~39\,
+	combout => \inst2|counter[8]~40_combout\,
+	cout => \inst2|counter[8]~41\);
+
+-- Location: FF_X51_Y14_N25
+\inst2|counter[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[8]~40_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(8));
+
+-- Location: LCCOMB_X51_Y14_N26
+\inst2|counter[9]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
+-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datad => VCC,
+	cin => \inst2|counter[8]~41\,
+	combout => \inst2|counter[9]~42_combout\,
+	cout => \inst2|counter[9]~43\);
+
+-- Location: FF_X51_Y14_N27
+\inst2|counter[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[9]~42_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(9));
+
+-- Location: LCCOMB_X51_Y14_N28
+\inst2|counter[10]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
+-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(10),
+	datad => VCC,
+	cin => \inst2|counter[9]~43\,
+	combout => \inst2|counter[10]~44_combout\,
+	cout => \inst2|counter[10]~45\);
+
+-- Location: FF_X51_Y14_N29
+\inst2|counter[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[10]~44_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(10));
+
+-- Location: LCCOMB_X51_Y14_N30
+\inst2|counter[11]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
+-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datad => VCC,
+	cin => \inst2|counter[10]~45\,
+	combout => \inst2|counter[11]~46_combout\,
+	cout => \inst2|counter[11]~47\);
+
+-- Location: FF_X51_Y14_N31
+\inst2|counter[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[11]~46_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(11));
+
+-- Location: LCCOMB_X51_Y13_N0
+\inst2|counter[12]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
+-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(12),
+	datad => VCC,
+	cin => \inst2|counter[11]~47\,
+	combout => \inst2|counter[12]~48_combout\,
+	cout => \inst2|counter[12]~49\);
+
+-- Location: FF_X51_Y13_N1
+\inst2|counter[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[12]~48_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(12));
+
+-- Location: LCCOMB_X51_Y13_N2
+\inst2|counter[13]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
+-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(13),
+	datad => VCC,
+	cin => \inst2|counter[12]~49\,
+	combout => \inst2|counter[13]~50_combout\,
+	cout => \inst2|counter[13]~51\);
+
+-- Location: FF_X51_Y13_N3
+\inst2|counter[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[13]~50_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(13));
+
+-- Location: LCCOMB_X51_Y13_N4
+\inst2|counter[14]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
+-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(14),
+	datad => VCC,
+	cin => \inst2|counter[13]~51\,
+	combout => \inst2|counter[14]~52_combout\,
+	cout => \inst2|counter[14]~53\);
+
+-- Location: FF_X51_Y13_N5
+\inst2|counter[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[14]~52_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(14));
+
+-- Location: LCCOMB_X51_Y13_N6
+\inst2|counter[15]~54\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
+-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datad => VCC,
+	cin => \inst2|counter[14]~53\,
+	combout => \inst2|counter[15]~54_combout\,
+	cout => \inst2|counter[15]~55\);
+
+-- Location: FF_X51_Y13_N7
+\inst2|counter[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[15]~54_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(15));
+
+-- Location: LCCOMB_X51_Y13_N8
+\inst2|counter[16]~56\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
+-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(16),
+	datad => VCC,
+	cin => \inst2|counter[15]~55\,
+	combout => \inst2|counter[16]~56_combout\,
+	cout => \inst2|counter[16]~57\);
+
+-- Location: FF_X51_Y13_N9
+\inst2|counter[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[16]~56_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(16));
+
+-- Location: LCCOMB_X51_Y13_N10
+\inst2|counter[17]~58\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
+-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(17),
+	datad => VCC,
+	cin => \inst2|counter[16]~57\,
+	combout => \inst2|counter[17]~58_combout\,
+	cout => \inst2|counter[17]~59\);
+
+-- Location: FF_X51_Y13_N11
+\inst2|counter[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[17]~58_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(17));
+
+-- Location: LCCOMB_X50_Y13_N20
+\inst2|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|counter\(16),
+	datac => \inst2|counter\(17),
+	datad => \inst2|counter\(14),
+	combout => \inst2|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X51_Y13_N12
+\inst2|counter[18]~60\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
+-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datad => VCC,
+	cin => \inst2|counter[17]~59\,
+	combout => \inst2|counter[18]~60_combout\,
+	cout => \inst2|counter[18]~61\);
+
+-- Location: FF_X51_Y13_N13
+\inst2|counter[18]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[18]~60_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(18));
+
+-- Location: LCCOMB_X51_Y13_N14
+\inst2|counter[19]~62\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
+-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(19),
+	datad => VCC,
+	cin => \inst2|counter[18]~61\,
+	combout => \inst2|counter[19]~62_combout\,
+	cout => \inst2|counter[19]~63\);
+
+-- Location: FF_X51_Y13_N15
+\inst2|counter[19]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[19]~62_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(19));
+
+-- Location: LCCOMB_X51_Y13_N16
+\inst2|counter[20]~64\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
+-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(20),
+	datad => VCC,
+	cin => \inst2|counter[19]~63\,
+	combout => \inst2|counter[20]~64_combout\,
+	cout => \inst2|counter[20]~65\);
+
+-- Location: FF_X51_Y13_N17
+\inst2|counter[20]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[20]~64_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(20));
+
+-- Location: LCCOMB_X51_Y13_N18
+\inst2|counter[21]~66\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
+-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(21),
+	datad => VCC,
+	cin => \inst2|counter[20]~65\,
+	combout => \inst2|counter[21]~66_combout\,
+	cout => \inst2|counter[21]~67\);
+
+-- Location: FF_X51_Y13_N19
+\inst2|counter[21]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[21]~66_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(21));
+
+-- Location: LCCOMB_X51_Y13_N20
+\inst2|counter[22]~68\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
+-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datad => VCC,
+	cin => \inst2|counter[21]~67\,
+	combout => \inst2|counter[22]~68_combout\,
+	cout => \inst2|counter[22]~69\);
+
+-- Location: FF_X51_Y13_N21
+\inst2|counter[22]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[22]~68_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(22));
+
+-- Location: LCCOMB_X51_Y13_N22
+\inst2|counter[23]~70\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(23),
+	cin => \inst2|counter[22]~69\,
+	combout => \inst2|counter[23]~70_combout\);
+
+-- Location: FF_X51_Y13_N23
+\inst2|counter[23]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[23]~70_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(23));
+
+-- Location: LCCOMB_X51_Y13_N24
+\inst2|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datab => \inst2|counter\(20),
+	datac => \inst2|counter\(19),
+	datad => \inst2|counter\(21),
+	combout => \inst2|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X51_Y13_N30
+\inst2|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datac => \inst2|counter\(23),
+	datad => \inst2|LessThan0~1_combout\,
+	combout => \inst2|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X51_Y14_N4
+\inst2|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datab => \inst2|counter\(8),
+	datac => \inst2|counter\(7),
+	datad => \inst2|counter\(10),
+	combout => \inst2|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X51_Y14_N0
+\inst2|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(2),
+	datab => \inst2|counter\(4),
+	datac => \inst2|counter\(0),
+	datad => \inst2|counter\(1),
+	combout => \inst2|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X51_Y14_N6
+\inst2|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100110111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datab => \inst2|counter\(5),
+	datac => \inst2|counter\(3),
+	datad => \inst2|LessThan0~3_combout\,
+	combout => \inst2|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X51_Y14_N2
+\inst2|LessThan0~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datab => \inst2|counter\(6),
+	datac => \inst2|LessThan0~5_combout\,
+	datad => \inst2|LessThan0~4_combout\,
+	combout => \inst2|LessThan0~6_combout\);
+
+-- Location: LCCOMB_X51_Y13_N28
+\inst2|LessThan0~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(16),
+	datab => \inst2|counter\(12),
+	datac => \inst2|counter\(13),
+	datad => \inst2|LessThan0~6_combout\,
+	combout => \inst2|LessThan0~7_combout\);
+
+-- Location: LCCOMB_X51_Y13_N26
+\inst2|LessThan0~8\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|LessThan0~0_combout\,
+	datac => \inst2|LessThan0~2_combout\,
+	datad => \inst2|LessThan0~7_combout\,
+	combout => \inst2|LessThan0~8_combout\);
+
+-- Location: LCCOMB_X52_Y13_N0
+\inst2|ledBuf~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst2|ledBuf~q\,
+	datad => \inst2|LessThan0~8_combout\,
+	combout => \inst2|ledBuf~0_combout\);
+
+-- Location: FF_X52_Y13_N1
+\inst2|ledBuf\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|ledBuf~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|ledBuf~q\);
+
+-- Location: IOIBUF_X38_Y34_N1
+\Address[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(7),
+	o => \Address[7]~input_o\);
 
 -- Location: IOIBUF_X14_Y34_N8
-\AddressRAM[5]~input\ : cycloneiii_io_ibuf
+\Address[6]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(5),
-	o => \AddressRAM[5]~input_o\);
+	i => ww_Address(6),
+	o => \Address[6]~input_o\);
 
--- Location: IOIBUF_X53_Y10_N15
-\AddressRAM[4]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X7_Y34_N15
+\Address[5]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(4),
-	o => \AddressRAM[4]~input_o\);
+	i => ww_Address(5),
+	o => \Address[5]~input_o\);
 
--- Location: IOIBUF_X3_Y0_N22
-\AddressRAM[3]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X14_Y34_N22
+\Address[4]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(3),
-	o => \AddressRAM[3]~input_o\);
+	i => ww_Address(4),
+	o => \Address[4]~input_o\);
 
--- Location: IOIBUF_X51_Y34_N8
-\AddressRAM[2]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X7_Y34_N1
+\Address[3]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(2),
-	o => \AddressRAM[2]~input_o\);
+	i => ww_Address(3),
+	o => \Address[3]~input_o\);
 
--- Location: IOIBUF_X1_Y0_N1
-\AddressRAM[1]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X7_Y34_N8
+\Address[2]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(1),
-	o => \AddressRAM[1]~input_o\);
+	i => ww_Address(2),
+	o => \Address[2]~input_o\);
 
--- Location: IOIBUF_X53_Y26_N22
-\AddressRAM[0]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X14_Y34_N15
+\Address[1]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_AddressRAM(0),
-	o => \AddressRAM[0]~input_o\);
+	i => ww_Address(1),
+	o => \Address[1]~input_o\);
 
--- Location: IOIBUF_X36_Y0_N8
-\DataRAM[15]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X38_Y34_N15
+\Address[0]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(15),
-	o => \DataRAM[15]~input_o\);
+	i => ww_Address(0),
+	o => \Address[0]~input_o\);
 
--- Location: IOIBUF_X53_Y14_N1
-\DataRAM[14]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X20_Y34_N1
+\nOE~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(14),
-	o => \DataRAM[14]~input_o\);
+	i => ww_nOE,
+	o => \nOE~input_o\);
 
--- Location: IOIBUF_X0_Y14_N8
-\DataRAM[13]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X20_Y34_N8
+\nWE~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(13),
-	o => \DataRAM[13]~input_o\);
+	i => ww_nWE,
+	o => \nWE~input_o\);
 
--- Location: IOIBUF_X53_Y14_N8
-\DataRAM[12]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X20_Y34_N15
+\nCE~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(12),
-	o => \DataRAM[12]~input_o\);
+	i => ww_nCE,
+	o => \nCE~input_o\);
 
--- Location: IOIBUF_X53_Y20_N15
-\DataRAM[11]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X18_Y34_N1
+\Data[7]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(11),
-	o => \DataRAM[11]~input_o\);
+	i => Data(7),
+	o => \Data[7]~input_o\);
 
--- Location: IOIBUF_X53_Y17_N22
-\DataRAM[10]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X18_Y34_N22
+\Data[6]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(10),
-	o => \DataRAM[10]~input_o\);
+	i => Data(6),
+	o => \Data[6]~input_o\);
 
--- Location: IOIBUF_X53_Y17_N15
-\DataRAM[9]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X16_Y34_N1
+\Data[5]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(9),
-	o => \DataRAM[9]~input_o\);
+	i => Data(5),
+	o => \Data[5]~input_o\);
 
--- Location: IOIBUF_X53_Y9_N8
-\DataRAM[8]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X16_Y34_N15
+\Data[4]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(8),
-	o => \DataRAM[8]~input_o\);
+	i => Data(4),
+	o => \Data[4]~input_o\);
 
--- Location: IOIBUF_X53_Y17_N8
-\DataRAM[7]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X45_Y34_N8
+\Data[3]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(7),
-	o => \DataRAM[7]~input_o\);
+	i => Data(3),
+	o => \Data[3]~input_o\);
 
--- Location: IOIBUF_X53_Y17_N1
-\DataRAM[6]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X45_Y34_N15
+\Data[2]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(6),
-	o => \DataRAM[6]~input_o\);
+	i => Data(2),
+	o => \Data[2]~input_o\);
 
--- Location: IOIBUF_X38_Y34_N22
-\DataRAM[5]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X45_Y34_N22
+\Data[1]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(5),
-	o => \DataRAM[5]~input_o\);
+	i => Data(1),
+	o => \Data[1]~input_o\);
 
--- Location: IOIBUF_X45_Y0_N15
-\DataRAM[4]~input\ : cycloneiii_io_ibuf
+-- Location: IOIBUF_X40_Y34_N8
+\Data[0]~input\ : cycloneiii_io_ibuf
 -- pragma translate_off
 GENERIC MAP (
 	bus_hold => "false",
 	simulate_z_as => "z")
 -- pragma translate_on
 PORT MAP (
-	i => ww_DataRAM(4),
-	o => \DataRAM[4]~input_o\);
+	i => Data(0),
+	o => \Data[0]~input_o\);
 
--- Location: IOIBUF_X53_Y21_N22
-\DataRAM[3]~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_DataRAM(3),
-	o => \DataRAM[3]~input_o\);
+ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\;
 
--- Location: IOIBUF_X53_Y23_N15
-\DataRAM[2]~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_DataRAM(2),
-	o => \DataRAM[2]~input_o\);
+Data(7) <= \Data[7]~output_o\;
 
--- Location: IOIBUF_X53_Y22_N1
-\DataRAM[1]~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_DataRAM(1),
-	o => \DataRAM[1]~input_o\);
+Data(6) <= \Data[6]~output_o\;
 
--- Location: IOIBUF_X51_Y0_N15
-\DataRAM[0]~input\ : cycloneiii_io_ibuf
--- pragma translate_off
-GENERIC MAP (
-	bus_hold => "false",
-	simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
-	i => ww_DataRAM(0),
-	o => \DataRAM[0]~input_o\);
+Data(5) <= \Data[5]~output_o\;
+
+Data(4) <= \Data[4]~output_o\;
+
+Data(3) <= \Data[3]~output_o\;
+
+Data(2) <= \Data[2]~output_o\;
+
+Data(1) <= \Data[1]~output_o\;
+
+Data(0) <= \Data[0]~output_o\;
 END structure;
 
 
diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho b/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho
new file mode 100644
index 0000000..d2c6f05
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_8_1200mv_0c_slow.vho
@@ -0,0 +1,1526 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
+
+-- DATE "03/12/2024 16:24:29"
+
+-- 
+-- Device: Altera EP3C25Q240C8 Package PQFP240
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	MainController IS
+    PORT (
+	FPGA_LED_1 : OUT std_logic;
+	FPGA_CLK : IN std_logic;
+	Data : INOUT std_logic_vector(7 DOWNTO 0);
+	Address : IN std_logic_vector(7 DOWNTO 0);
+	nOE : IN std_logic;
+	nWE : IN std_logic;
+	nCE : IN std_logic
+	);
+END MainController;
+
+-- Design Ports Information
+-- FPGA_LED_1	=>  Location: PIN_166,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Address[7]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[6]	=>  Location: PIN_230,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[5]	=>  Location: PIN_235,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[4]	=>  Location: PIN_232,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[3]	=>  Location: PIN_233,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[2]	=>  Location: PIN_234,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[1]	=>  Location: PIN_231,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[0]	=>  Location: PIN_196,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nOE	=>  Location: PIN_217,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nWE	=>  Location: PIN_218,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nCE	=>  Location: PIN_219,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Data[7]	=>  Location: PIN_221,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[6]	=>  Location: PIN_223,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[5]	=>  Location: PIN_224,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[4]	=>  Location: PIN_226,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[3]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[2]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[1]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[0]	=>  Location: PIN_194,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- FPGA_CLK	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF MainController IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_FPGA_LED_1 : std_logic;
+SIGNAL ww_FPGA_CLK : std_logic;
+SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_nOE : std_logic;
+SIGNAL ww_nWE : std_logic;
+SIGNAL ww_nCE : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Address[7]~input_o\ : std_logic;
+SIGNAL \Address[6]~input_o\ : std_logic;
+SIGNAL \Address[5]~input_o\ : std_logic;
+SIGNAL \Address[4]~input_o\ : std_logic;
+SIGNAL \Address[3]~input_o\ : std_logic;
+SIGNAL \Address[2]~input_o\ : std_logic;
+SIGNAL \Address[1]~input_o\ : std_logic;
+SIGNAL \Address[0]~input_o\ : std_logic;
+SIGNAL \nOE~input_o\ : std_logic;
+SIGNAL \nWE~input_o\ : std_logic;
+SIGNAL \nCE~input_o\ : std_logic;
+SIGNAL \Data[7]~input_o\ : std_logic;
+SIGNAL \Data[6]~input_o\ : std_logic;
+SIGNAL \Data[5]~input_o\ : std_logic;
+SIGNAL \Data[4]~input_o\ : std_logic;
+SIGNAL \Data[3]~input_o\ : std_logic;
+SIGNAL \Data[2]~input_o\ : std_logic;
+SIGNAL \Data[1]~input_o\ : std_logic;
+SIGNAL \Data[0]~input_o\ : std_logic;
+SIGNAL \Data[7]~output_o\ : std_logic;
+SIGNAL \Data[6]~output_o\ : std_logic;
+SIGNAL \Data[5]~output_o\ : std_logic;
+SIGNAL \Data[4]~output_o\ : std_logic;
+SIGNAL \Data[3]~output_o\ : std_logic;
+SIGNAL \Data[2]~output_o\ : std_logic;
+SIGNAL \Data[1]~output_o\ : std_logic;
+SIGNAL \Data[0]~output_o\ : std_logic;
+SIGNAL \FPGA_LED_1~output_o\ : std_logic;
+SIGNAL \FPGA_CLK~input_o\ : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
+SIGNAL \inst2|counter[0]~25\ : std_logic;
+SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
+SIGNAL \inst2|counter[1]~27\ : std_logic;
+SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
+SIGNAL \inst2|counter[2]~29\ : std_logic;
+SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
+SIGNAL \inst2|counter[3]~31\ : std_logic;
+SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
+SIGNAL \inst2|counter[4]~33\ : std_logic;
+SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
+SIGNAL \inst2|counter[5]~35\ : std_logic;
+SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
+SIGNAL \inst2|counter[6]~37\ : std_logic;
+SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
+SIGNAL \inst2|counter[7]~39\ : std_logic;
+SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
+SIGNAL \inst2|counter[8]~41\ : std_logic;
+SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
+SIGNAL \inst2|counter[9]~43\ : std_logic;
+SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
+SIGNAL \inst2|counter[10]~45\ : std_logic;
+SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
+SIGNAL \inst2|counter[11]~47\ : std_logic;
+SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
+SIGNAL \inst2|counter[12]~49\ : std_logic;
+SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
+SIGNAL \inst2|counter[13]~51\ : std_logic;
+SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
+SIGNAL \inst2|counter[14]~53\ : std_logic;
+SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
+SIGNAL \inst2|counter[15]~55\ : std_logic;
+SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
+SIGNAL \inst2|counter[16]~57\ : std_logic;
+SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
+SIGNAL \inst2|counter[17]~59\ : std_logic;
+SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
+SIGNAL \inst2|counter[18]~61\ : std_logic;
+SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
+SIGNAL \inst2|counter[19]~63\ : std_logic;
+SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
+SIGNAL \inst2|counter[20]~65\ : std_logic;
+SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
+SIGNAL \inst2|counter[21]~67\ : std_logic;
+SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
+SIGNAL \inst2|counter[22]~69\ : std_logic;
+SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~q\ : std_logic;
+SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
+SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;
+
+BEGIN
+
+FPGA_LED_1 <= ww_FPGA_LED_1;
+ww_FPGA_CLK <= FPGA_CLK;
+ww_Address <= Address;
+ww_nOE <= nOE;
+ww_nWE <= nWE;
+ww_nCE <= nCE;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
+\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\;
+\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;
+
+-- Location: IOOBUF_X18_Y34_N2
+\Data[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[7]~output_o\);
+
+-- Location: IOOBUF_X18_Y34_N23
+\Data[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[6]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N2
+\Data[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[5]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N16
+\Data[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[4]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N9
+\Data[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[3]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N16
+\Data[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[2]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N23
+\Data[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[1]~output_o\);
+
+-- Location: IOOBUF_X40_Y34_N9
+\Data[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[0]~output_o\);
+
+-- Location: IOOBUF_X53_Y22_N2
+\FPGA_LED_1~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|ALT_INV_ledBuf~q\,
+	devoe => ww_devoe,
+	o => \FPGA_LED_1~output_o\);
+
+-- Location: IOIBUF_X0_Y16_N1
+\FPGA_CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_FPGA_CLK,
+	o => \FPGA_CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \FPGA_CLK~inputclkctrl_outclk\);
+
+-- Location: LCCOMB_X51_Y14_N8
+\inst2|counter[0]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
+-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101010110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(0),
+	datad => VCC,
+	combout => \inst2|counter[0]~24_combout\,
+	cout => \inst2|counter[0]~25\);
+
+-- Location: FF_X51_Y14_N9
+\inst2|counter[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[0]~24_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(0));
+
+-- Location: LCCOMB_X51_Y14_N10
+\inst2|counter[1]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
+-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(1),
+	datad => VCC,
+	cin => \inst2|counter[0]~25\,
+	combout => \inst2|counter[1]~26_combout\,
+	cout => \inst2|counter[1]~27\);
+
+-- Location: FF_X51_Y14_N11
+\inst2|counter[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[1]~26_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(1));
+
+-- Location: LCCOMB_X51_Y14_N12
+\inst2|counter[2]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
+-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(2),
+	datad => VCC,
+	cin => \inst2|counter[1]~27\,
+	combout => \inst2|counter[2]~28_combout\,
+	cout => \inst2|counter[2]~29\);
+
+-- Location: FF_X51_Y14_N13
+\inst2|counter[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[2]~28_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(2));
+
+-- Location: LCCOMB_X51_Y14_N14
+\inst2|counter[3]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
+-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(3),
+	datad => VCC,
+	cin => \inst2|counter[2]~29\,
+	combout => \inst2|counter[3]~30_combout\,
+	cout => \inst2|counter[3]~31\);
+
+-- Location: FF_X51_Y14_N15
+\inst2|counter[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[3]~30_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(3));
+
+-- Location: LCCOMB_X51_Y14_N16
+\inst2|counter[4]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
+-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datad => VCC,
+	cin => \inst2|counter[3]~31\,
+	combout => \inst2|counter[4]~32_combout\,
+	cout => \inst2|counter[4]~33\);
+
+-- Location: FF_X51_Y14_N17
+\inst2|counter[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[4]~32_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(4));
+
+-- Location: LCCOMB_X51_Y14_N18
+\inst2|counter[5]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
+-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(5),
+	datad => VCC,
+	cin => \inst2|counter[4]~33\,
+	combout => \inst2|counter[5]~34_combout\,
+	cout => \inst2|counter[5]~35\);
+
+-- Location: FF_X51_Y14_N19
+\inst2|counter[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[5]~34_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(5));
+
+-- Location: LCCOMB_X51_Y14_N20
+\inst2|counter[6]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
+-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(6),
+	datad => VCC,
+	cin => \inst2|counter[5]~35\,
+	combout => \inst2|counter[6]~36_combout\,
+	cout => \inst2|counter[6]~37\);
+
+-- Location: FF_X51_Y14_N21
+\inst2|counter[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[6]~36_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(6));
+
+-- Location: LCCOMB_X51_Y14_N22
+\inst2|counter[7]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
+-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(7),
+	datad => VCC,
+	cin => \inst2|counter[6]~37\,
+	combout => \inst2|counter[7]~38_combout\,
+	cout => \inst2|counter[7]~39\);
+
+-- Location: FF_X51_Y14_N23
+\inst2|counter[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[7]~38_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(7));
+
+-- Location: LCCOMB_X51_Y14_N24
+\inst2|counter[8]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
+-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(8),
+	datad => VCC,
+	cin => \inst2|counter[7]~39\,
+	combout => \inst2|counter[8]~40_combout\,
+	cout => \inst2|counter[8]~41\);
+
+-- Location: FF_X51_Y14_N25
+\inst2|counter[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[8]~40_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(8));
+
+-- Location: LCCOMB_X51_Y14_N26
+\inst2|counter[9]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
+-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datad => VCC,
+	cin => \inst2|counter[8]~41\,
+	combout => \inst2|counter[9]~42_combout\,
+	cout => \inst2|counter[9]~43\);
+
+-- Location: FF_X51_Y14_N27
+\inst2|counter[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[9]~42_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(9));
+
+-- Location: LCCOMB_X51_Y14_N28
+\inst2|counter[10]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
+-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(10),
+	datad => VCC,
+	cin => \inst2|counter[9]~43\,
+	combout => \inst2|counter[10]~44_combout\,
+	cout => \inst2|counter[10]~45\);
+
+-- Location: FF_X51_Y14_N29
+\inst2|counter[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[10]~44_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(10));
+
+-- Location: LCCOMB_X51_Y14_N30
+\inst2|counter[11]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
+-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datad => VCC,
+	cin => \inst2|counter[10]~45\,
+	combout => \inst2|counter[11]~46_combout\,
+	cout => \inst2|counter[11]~47\);
+
+-- Location: FF_X51_Y14_N31
+\inst2|counter[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[11]~46_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(11));
+
+-- Location: LCCOMB_X51_Y13_N0
+\inst2|counter[12]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
+-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(12),
+	datad => VCC,
+	cin => \inst2|counter[11]~47\,
+	combout => \inst2|counter[12]~48_combout\,
+	cout => \inst2|counter[12]~49\);
+
+-- Location: FF_X51_Y13_N1
+\inst2|counter[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[12]~48_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(12));
+
+-- Location: LCCOMB_X51_Y13_N2
+\inst2|counter[13]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
+-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(13),
+	datad => VCC,
+	cin => \inst2|counter[12]~49\,
+	combout => \inst2|counter[13]~50_combout\,
+	cout => \inst2|counter[13]~51\);
+
+-- Location: FF_X51_Y13_N3
+\inst2|counter[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[13]~50_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(13));
+
+-- Location: LCCOMB_X51_Y13_N4
+\inst2|counter[14]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
+-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(14),
+	datad => VCC,
+	cin => \inst2|counter[13]~51\,
+	combout => \inst2|counter[14]~52_combout\,
+	cout => \inst2|counter[14]~53\);
+
+-- Location: FF_X51_Y13_N5
+\inst2|counter[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[14]~52_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(14));
+
+-- Location: LCCOMB_X51_Y13_N6
+\inst2|counter[15]~54\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
+-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datad => VCC,
+	cin => \inst2|counter[14]~53\,
+	combout => \inst2|counter[15]~54_combout\,
+	cout => \inst2|counter[15]~55\);
+
+-- Location: FF_X51_Y13_N7
+\inst2|counter[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[15]~54_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(15));
+
+-- Location: LCCOMB_X51_Y13_N8
+\inst2|counter[16]~56\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
+-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(16),
+	datad => VCC,
+	cin => \inst2|counter[15]~55\,
+	combout => \inst2|counter[16]~56_combout\,
+	cout => \inst2|counter[16]~57\);
+
+-- Location: FF_X51_Y13_N9
+\inst2|counter[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[16]~56_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(16));
+
+-- Location: LCCOMB_X51_Y13_N10
+\inst2|counter[17]~58\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
+-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(17),
+	datad => VCC,
+	cin => \inst2|counter[16]~57\,
+	combout => \inst2|counter[17]~58_combout\,
+	cout => \inst2|counter[17]~59\);
+
+-- Location: FF_X51_Y13_N11
+\inst2|counter[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[17]~58_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(17));
+
+-- Location: LCCOMB_X50_Y13_N20
+\inst2|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|counter\(16),
+	datac => \inst2|counter\(17),
+	datad => \inst2|counter\(14),
+	combout => \inst2|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X51_Y13_N12
+\inst2|counter[18]~60\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
+-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datad => VCC,
+	cin => \inst2|counter[17]~59\,
+	combout => \inst2|counter[18]~60_combout\,
+	cout => \inst2|counter[18]~61\);
+
+-- Location: FF_X51_Y13_N13
+\inst2|counter[18]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[18]~60_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(18));
+
+-- Location: LCCOMB_X51_Y13_N14
+\inst2|counter[19]~62\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
+-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(19),
+	datad => VCC,
+	cin => \inst2|counter[18]~61\,
+	combout => \inst2|counter[19]~62_combout\,
+	cout => \inst2|counter[19]~63\);
+
+-- Location: FF_X51_Y13_N15
+\inst2|counter[19]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[19]~62_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(19));
+
+-- Location: LCCOMB_X51_Y13_N16
+\inst2|counter[20]~64\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
+-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(20),
+	datad => VCC,
+	cin => \inst2|counter[19]~63\,
+	combout => \inst2|counter[20]~64_combout\,
+	cout => \inst2|counter[20]~65\);
+
+-- Location: FF_X51_Y13_N17
+\inst2|counter[20]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[20]~64_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(20));
+
+-- Location: LCCOMB_X51_Y13_N18
+\inst2|counter[21]~66\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
+-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(21),
+	datad => VCC,
+	cin => \inst2|counter[20]~65\,
+	combout => \inst2|counter[21]~66_combout\,
+	cout => \inst2|counter[21]~67\);
+
+-- Location: FF_X51_Y13_N19
+\inst2|counter[21]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[21]~66_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(21));
+
+-- Location: LCCOMB_X51_Y13_N20
+\inst2|counter[22]~68\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
+-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datad => VCC,
+	cin => \inst2|counter[21]~67\,
+	combout => \inst2|counter[22]~68_combout\,
+	cout => \inst2|counter[22]~69\);
+
+-- Location: FF_X51_Y13_N21
+\inst2|counter[22]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[22]~68_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(22));
+
+-- Location: LCCOMB_X51_Y13_N22
+\inst2|counter[23]~70\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(23),
+	cin => \inst2|counter[22]~69\,
+	combout => \inst2|counter[23]~70_combout\);
+
+-- Location: FF_X51_Y13_N23
+\inst2|counter[23]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[23]~70_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(23));
+
+-- Location: LCCOMB_X51_Y13_N24
+\inst2|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datab => \inst2|counter\(20),
+	datac => \inst2|counter\(19),
+	datad => \inst2|counter\(21),
+	combout => \inst2|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X51_Y13_N30
+\inst2|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datac => \inst2|counter\(23),
+	datad => \inst2|LessThan0~1_combout\,
+	combout => \inst2|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X51_Y14_N4
+\inst2|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datab => \inst2|counter\(8),
+	datac => \inst2|counter\(7),
+	datad => \inst2|counter\(10),
+	combout => \inst2|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X51_Y14_N0
+\inst2|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(2),
+	datab => \inst2|counter\(4),
+	datac => \inst2|counter\(0),
+	datad => \inst2|counter\(1),
+	combout => \inst2|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X51_Y14_N6
+\inst2|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100110111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datab => \inst2|counter\(5),
+	datac => \inst2|counter\(3),
+	datad => \inst2|LessThan0~3_combout\,
+	combout => \inst2|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X51_Y14_N2
+\inst2|LessThan0~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datab => \inst2|counter\(6),
+	datac => \inst2|LessThan0~5_combout\,
+	datad => \inst2|LessThan0~4_combout\,
+	combout => \inst2|LessThan0~6_combout\);
+
+-- Location: LCCOMB_X51_Y13_N28
+\inst2|LessThan0~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(16),
+	datab => \inst2|counter\(12),
+	datac => \inst2|counter\(13),
+	datad => \inst2|LessThan0~6_combout\,
+	combout => \inst2|LessThan0~7_combout\);
+
+-- Location: LCCOMB_X51_Y13_N26
+\inst2|LessThan0~8\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|LessThan0~0_combout\,
+	datac => \inst2|LessThan0~2_combout\,
+	datad => \inst2|LessThan0~7_combout\,
+	combout => \inst2|LessThan0~8_combout\);
+
+-- Location: LCCOMB_X52_Y13_N0
+\inst2|ledBuf~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst2|ledBuf~q\,
+	datad => \inst2|LessThan0~8_combout\,
+	combout => \inst2|ledBuf~0_combout\);
+
+-- Location: FF_X52_Y13_N1
+\inst2|ledBuf\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|ledBuf~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|ledBuf~q\);
+
+-- Location: IOIBUF_X38_Y34_N1
+\Address[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(7),
+	o => \Address[7]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N8
+\Address[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(6),
+	o => \Address[6]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N15
+\Address[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(5),
+	o => \Address[5]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N22
+\Address[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(4),
+	o => \Address[4]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N1
+\Address[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(3),
+	o => \Address[3]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N8
+\Address[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(2),
+	o => \Address[2]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N15
+\Address[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(1),
+	o => \Address[1]~input_o\);
+
+-- Location: IOIBUF_X38_Y34_N15
+\Address[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(0),
+	o => \Address[0]~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N1
+\nOE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nOE,
+	o => \nOE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N8
+\nWE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nWE,
+	o => \nWE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N15
+\nCE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nCE,
+	o => \nCE~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N1
+\Data[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(7),
+	o => \Data[7]~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N22
+\Data[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(6),
+	o => \Data[6]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N1
+\Data[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(5),
+	o => \Data[5]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N15
+\Data[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(4),
+	o => \Data[4]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N8
+\Data[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(3),
+	o => \Data[3]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N15
+\Data[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(2),
+	o => \Data[2]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N22
+\Data[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(1),
+	o => \Data[1]~input_o\);
+
+-- Location: IOIBUF_X40_Y34_N8
+\Data[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(0),
+	o => \Data[0]~input_o\);
+
+ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\;
+
+Data(7) <= \Data[7]~output_o\;
+
+Data(6) <= \Data[6]~output_o\;
+
+Data(5) <= \Data[5]~output_o\;
+
+Data(4) <= \Data[4]~output_o\;
+
+Data(3) <= \Data[3]~output_o\;
+
+Data(2) <= \Data[2]~output_o\;
+
+Data(1) <= \Data[1]~output_o\;
+
+Data(0) <= \Data[0]~output_o\;
+END structure;
+
+
diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo b/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..afb55df
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_8_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,949 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C25Q240C8 Package PQFP240
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
+// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "MainController")
+  (DATE "03/12/2024 16:24:29")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\FPGA_LED_1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1277:1277:1277) (1446:1446:1446))
+        (IOPATH i o (2195:2195:2195) (2297:2297:2297))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\FPGA_CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (899:899:899) (1014:1014:1014))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\FPGA_CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (166:166:166) (162:162:162))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[0\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (553:553:553) (536:536:536))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[1\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (558:558:558) (530:530:530))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[2\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (548:548:548) (534:534:534))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[3\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2182:2182:2182) (2152:2152:2152))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[4\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (568:568:568) (551:551:551))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[5\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (383:383:383))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[6\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (384:384:384))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2182:2182:2182) (2152:2152:2152))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[7\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (548:548:548) (530:530:530))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[8\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (325:325:325) (382:382:382))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[9\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (392:392:392))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1712:1712:1712) (1732:1732:1732))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[10\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (324:324:324) (381:381:381))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2182:2182:2182) (2152:2152:2152))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[11\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (392:392:392))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2182:2182:2182) (2152:2152:2152))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (1344:1344:1344) (1536:1536:1536))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[12\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (323:323:323) (381:381:381))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[13\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (338:338:338) (392:392:392))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[14\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (339:339:339) (393:393:393))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[15\]\~54\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (414:414:414))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1711:1711:1711) (1731:1731:1731))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[16\]\~56\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (394:394:394))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1711:1711:1711) (1731:1731:1731))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[17\]\~58\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (403:403:403))
+        (IOPATH dataa combout (414:414:414) (444:444:444))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1711:1711:1711) (1731:1731:1731))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (880:880:880) (761:761:761))
+        (PORT datab (618:618:618) (575:575:575))
+        (PORT datac (513:513:513) (507:507:507))
+        (PORT datad (552:552:552) (524:524:524))
+        (IOPATH dataa combout (392:392:392) (419:419:419))
+        (IOPATH datab combout (393:393:393) (431:431:431))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[18\]\~60\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (330:330:330) (394:394:394))
+        (IOPATH dataa combout (435:435:435) (425:425:425))
+        (IOPATH dataa cout (486:486:486) (375:375:375))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[18\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1711:1711:1711) (1731:1731:1731))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[19\]\~62\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[19\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[20\]\~64\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (328:328:328) (384:384:384))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[20\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[21\]\~66\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (326:326:326) (384:384:384))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[21\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[22\]\~68\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (328:328:328) (386:386:386))
+        (IOPATH datab combout (437:437:437) (425:425:425))
+        (IOPATH datab cout (497:497:497) (381:381:381))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+        (IOPATH cin cout (63:63:63) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[22\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[23\]\~70\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (808:808:808) (716:716:716))
+        (IOPATH dataa combout (435:435:435) (444:444:444))
+        (IOPATH cin combout (549:549:549) (519:519:519))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[23\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (PORT sclr (884:884:884) (924:924:924))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+      (HOLD sclr (posedge clk) (195:195:195))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (393:393:393))
+        (PORT datab (326:326:326) (383:383:383))
+        (PORT datac (283:283:283) (349:349:349))
+        (PORT datad (284:284:284) (342:342:342))
+        (IOPATH dataa combout (374:374:374) (392:392:392))
+        (IOPATH datab combout (384:384:384) (398:398:398))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (327:327:327) (384:384:384))
+        (PORT datac (761:761:761) (676:676:676))
+        (PORT datad (225:225:225) (233:233:233))
+        (IOPATH datab combout (423:423:423) (451:451:451))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (392:392:392))
+        (PORT datab (325:325:325) (382:382:382))
+        (PORT datac (297:297:297) (359:359:359))
+        (PORT datad (284:284:284) (343:343:343))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (401:401:401))
+        (PORT datab (339:339:339) (394:394:394))
+        (PORT datac (296:296:296) (359:359:359))
+        (PORT datad (297:297:297) (353:353:353))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (406:406:406) (453:453:453))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (570:570:570) (549:549:549))
+        (PORT datab (326:326:326) (382:382:382))
+        (PORT datac (283:283:283) (348:348:348))
+        (PORT datad (225:225:225) (232:232:232))
+        (IOPATH dataa combout (428:428:428) (449:449:449))
+        (IOPATH datab combout (438:438:438) (455:455:455))
+        (IOPATH datac combout (301:301:301) (283:283:283))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (332:332:332) (396:396:396))
+        (PORT datab (328:328:328) (385:385:385))
+        (PORT datac (224:224:224) (239:239:239))
+        (PORT datad (225:225:225) (233:233:233))
+        (IOPATH dataa combout (350:350:350) (371:371:371))
+        (IOPATH datab combout (354:354:354) (380:380:380))
+        (IOPATH datac combout (301:301:301) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (563:563:563) (549:549:549))
+        (PORT datab (329:329:329) (387:387:387))
+        (PORT datac (522:522:522) (502:502:502))
+        (PORT datad (799:799:799) (654:654:654))
+        (IOPATH dataa combout (435:435:435) (407:407:407))
+        (IOPATH datab combout (437:437:437) (407:407:407))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~8\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (418:418:418))
+        (PORT datab (529:529:529) (432:432:432))
+        (PORT datac (224:224:224) (239:239:239))
+        (PORT datad (224:224:224) (232:232:232))
+        (IOPATH dataa combout (404:404:404) (450:450:450))
+        (IOPATH datab combout (415:415:415) (425:425:425))
+        (IOPATH datac combout (305:305:305) (285:285:285))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|ledBuf\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (737:737:737) (601:601:601))
+        (IOPATH datac combout (415:415:415) (429:429:429))
+        (IOPATH datad combout (167:167:167) (143:143:143))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|ledBuf\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2183:2183:2183) (2153:2153:2153))
+        (PORT d (90:90:90) (101:101:101))
+        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (195:195:195))
+    )
+  )
+)
diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho b/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho
new file mode 100644
index 0000000..d2c6f05
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_8_1200mv_85c_slow.vho
@@ -0,0 +1,1526 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
+
+-- DATE "03/12/2024 16:24:29"
+
+-- 
+-- Device: Altera EP3C25Q240C8 Package PQFP240
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	MainController IS
+    PORT (
+	FPGA_LED_1 : OUT std_logic;
+	FPGA_CLK : IN std_logic;
+	Data : INOUT std_logic_vector(7 DOWNTO 0);
+	Address : IN std_logic_vector(7 DOWNTO 0);
+	nOE : IN std_logic;
+	nWE : IN std_logic;
+	nCE : IN std_logic
+	);
+END MainController;
+
+-- Design Ports Information
+-- FPGA_LED_1	=>  Location: PIN_166,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Address[7]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[6]	=>  Location: PIN_230,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[5]	=>  Location: PIN_235,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[4]	=>  Location: PIN_232,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[3]	=>  Location: PIN_233,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[2]	=>  Location: PIN_234,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[1]	=>  Location: PIN_231,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[0]	=>  Location: PIN_196,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nOE	=>  Location: PIN_217,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nWE	=>  Location: PIN_218,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nCE	=>  Location: PIN_219,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Data[7]	=>  Location: PIN_221,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[6]	=>  Location: PIN_223,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[5]	=>  Location: PIN_224,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[4]	=>  Location: PIN_226,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[3]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[2]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[1]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[0]	=>  Location: PIN_194,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- FPGA_CLK	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF MainController IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_FPGA_LED_1 : std_logic;
+SIGNAL ww_FPGA_CLK : std_logic;
+SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_nOE : std_logic;
+SIGNAL ww_nWE : std_logic;
+SIGNAL ww_nCE : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Address[7]~input_o\ : std_logic;
+SIGNAL \Address[6]~input_o\ : std_logic;
+SIGNAL \Address[5]~input_o\ : std_logic;
+SIGNAL \Address[4]~input_o\ : std_logic;
+SIGNAL \Address[3]~input_o\ : std_logic;
+SIGNAL \Address[2]~input_o\ : std_logic;
+SIGNAL \Address[1]~input_o\ : std_logic;
+SIGNAL \Address[0]~input_o\ : std_logic;
+SIGNAL \nOE~input_o\ : std_logic;
+SIGNAL \nWE~input_o\ : std_logic;
+SIGNAL \nCE~input_o\ : std_logic;
+SIGNAL \Data[7]~input_o\ : std_logic;
+SIGNAL \Data[6]~input_o\ : std_logic;
+SIGNAL \Data[5]~input_o\ : std_logic;
+SIGNAL \Data[4]~input_o\ : std_logic;
+SIGNAL \Data[3]~input_o\ : std_logic;
+SIGNAL \Data[2]~input_o\ : std_logic;
+SIGNAL \Data[1]~input_o\ : std_logic;
+SIGNAL \Data[0]~input_o\ : std_logic;
+SIGNAL \Data[7]~output_o\ : std_logic;
+SIGNAL \Data[6]~output_o\ : std_logic;
+SIGNAL \Data[5]~output_o\ : std_logic;
+SIGNAL \Data[4]~output_o\ : std_logic;
+SIGNAL \Data[3]~output_o\ : std_logic;
+SIGNAL \Data[2]~output_o\ : std_logic;
+SIGNAL \Data[1]~output_o\ : std_logic;
+SIGNAL \Data[0]~output_o\ : std_logic;
+SIGNAL \FPGA_LED_1~output_o\ : std_logic;
+SIGNAL \FPGA_CLK~input_o\ : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
+SIGNAL \inst2|counter[0]~25\ : std_logic;
+SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
+SIGNAL \inst2|counter[1]~27\ : std_logic;
+SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
+SIGNAL \inst2|counter[2]~29\ : std_logic;
+SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
+SIGNAL \inst2|counter[3]~31\ : std_logic;
+SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
+SIGNAL \inst2|counter[4]~33\ : std_logic;
+SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
+SIGNAL \inst2|counter[5]~35\ : std_logic;
+SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
+SIGNAL \inst2|counter[6]~37\ : std_logic;
+SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
+SIGNAL \inst2|counter[7]~39\ : std_logic;
+SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
+SIGNAL \inst2|counter[8]~41\ : std_logic;
+SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
+SIGNAL \inst2|counter[9]~43\ : std_logic;
+SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
+SIGNAL \inst2|counter[10]~45\ : std_logic;
+SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
+SIGNAL \inst2|counter[11]~47\ : std_logic;
+SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
+SIGNAL \inst2|counter[12]~49\ : std_logic;
+SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
+SIGNAL \inst2|counter[13]~51\ : std_logic;
+SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
+SIGNAL \inst2|counter[14]~53\ : std_logic;
+SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
+SIGNAL \inst2|counter[15]~55\ : std_logic;
+SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
+SIGNAL \inst2|counter[16]~57\ : std_logic;
+SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
+SIGNAL \inst2|counter[17]~59\ : std_logic;
+SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
+SIGNAL \inst2|counter[18]~61\ : std_logic;
+SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
+SIGNAL \inst2|counter[19]~63\ : std_logic;
+SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
+SIGNAL \inst2|counter[20]~65\ : std_logic;
+SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
+SIGNAL \inst2|counter[21]~67\ : std_logic;
+SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
+SIGNAL \inst2|counter[22]~69\ : std_logic;
+SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~q\ : std_logic;
+SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
+SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;
+
+BEGIN
+
+FPGA_LED_1 <= ww_FPGA_LED_1;
+ww_FPGA_CLK <= FPGA_CLK;
+ww_Address <= Address;
+ww_nOE <= nOE;
+ww_nWE <= nWE;
+ww_nCE <= nCE;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
+\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\;
+\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;
+
+-- Location: IOOBUF_X18_Y34_N2
+\Data[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[7]~output_o\);
+
+-- Location: IOOBUF_X18_Y34_N23
+\Data[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[6]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N2
+\Data[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[5]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N16
+\Data[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[4]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N9
+\Data[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[3]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N16
+\Data[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[2]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N23
+\Data[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[1]~output_o\);
+
+-- Location: IOOBUF_X40_Y34_N9
+\Data[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[0]~output_o\);
+
+-- Location: IOOBUF_X53_Y22_N2
+\FPGA_LED_1~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|ALT_INV_ledBuf~q\,
+	devoe => ww_devoe,
+	o => \FPGA_LED_1~output_o\);
+
+-- Location: IOIBUF_X0_Y16_N1
+\FPGA_CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_FPGA_CLK,
+	o => \FPGA_CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \FPGA_CLK~inputclkctrl_outclk\);
+
+-- Location: LCCOMB_X51_Y14_N8
+\inst2|counter[0]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
+-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101010110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(0),
+	datad => VCC,
+	combout => \inst2|counter[0]~24_combout\,
+	cout => \inst2|counter[0]~25\);
+
+-- Location: FF_X51_Y14_N9
+\inst2|counter[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[0]~24_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(0));
+
+-- Location: LCCOMB_X51_Y14_N10
+\inst2|counter[1]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
+-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(1),
+	datad => VCC,
+	cin => \inst2|counter[0]~25\,
+	combout => \inst2|counter[1]~26_combout\,
+	cout => \inst2|counter[1]~27\);
+
+-- Location: FF_X51_Y14_N11
+\inst2|counter[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[1]~26_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(1));
+
+-- Location: LCCOMB_X51_Y14_N12
+\inst2|counter[2]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
+-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(2),
+	datad => VCC,
+	cin => \inst2|counter[1]~27\,
+	combout => \inst2|counter[2]~28_combout\,
+	cout => \inst2|counter[2]~29\);
+
+-- Location: FF_X51_Y14_N13
+\inst2|counter[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[2]~28_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(2));
+
+-- Location: LCCOMB_X51_Y14_N14
+\inst2|counter[3]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
+-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(3),
+	datad => VCC,
+	cin => \inst2|counter[2]~29\,
+	combout => \inst2|counter[3]~30_combout\,
+	cout => \inst2|counter[3]~31\);
+
+-- Location: FF_X51_Y14_N15
+\inst2|counter[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[3]~30_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(3));
+
+-- Location: LCCOMB_X51_Y14_N16
+\inst2|counter[4]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
+-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datad => VCC,
+	cin => \inst2|counter[3]~31\,
+	combout => \inst2|counter[4]~32_combout\,
+	cout => \inst2|counter[4]~33\);
+
+-- Location: FF_X51_Y14_N17
+\inst2|counter[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[4]~32_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(4));
+
+-- Location: LCCOMB_X51_Y14_N18
+\inst2|counter[5]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
+-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(5),
+	datad => VCC,
+	cin => \inst2|counter[4]~33\,
+	combout => \inst2|counter[5]~34_combout\,
+	cout => \inst2|counter[5]~35\);
+
+-- Location: FF_X51_Y14_N19
+\inst2|counter[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[5]~34_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(5));
+
+-- Location: LCCOMB_X51_Y14_N20
+\inst2|counter[6]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
+-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(6),
+	datad => VCC,
+	cin => \inst2|counter[5]~35\,
+	combout => \inst2|counter[6]~36_combout\,
+	cout => \inst2|counter[6]~37\);
+
+-- Location: FF_X51_Y14_N21
+\inst2|counter[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[6]~36_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(6));
+
+-- Location: LCCOMB_X51_Y14_N22
+\inst2|counter[7]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
+-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(7),
+	datad => VCC,
+	cin => \inst2|counter[6]~37\,
+	combout => \inst2|counter[7]~38_combout\,
+	cout => \inst2|counter[7]~39\);
+
+-- Location: FF_X51_Y14_N23
+\inst2|counter[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[7]~38_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(7));
+
+-- Location: LCCOMB_X51_Y14_N24
+\inst2|counter[8]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
+-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(8),
+	datad => VCC,
+	cin => \inst2|counter[7]~39\,
+	combout => \inst2|counter[8]~40_combout\,
+	cout => \inst2|counter[8]~41\);
+
+-- Location: FF_X51_Y14_N25
+\inst2|counter[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[8]~40_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(8));
+
+-- Location: LCCOMB_X51_Y14_N26
+\inst2|counter[9]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
+-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datad => VCC,
+	cin => \inst2|counter[8]~41\,
+	combout => \inst2|counter[9]~42_combout\,
+	cout => \inst2|counter[9]~43\);
+
+-- Location: FF_X51_Y14_N27
+\inst2|counter[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[9]~42_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(9));
+
+-- Location: LCCOMB_X51_Y14_N28
+\inst2|counter[10]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
+-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(10),
+	datad => VCC,
+	cin => \inst2|counter[9]~43\,
+	combout => \inst2|counter[10]~44_combout\,
+	cout => \inst2|counter[10]~45\);
+
+-- Location: FF_X51_Y14_N29
+\inst2|counter[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[10]~44_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(10));
+
+-- Location: LCCOMB_X51_Y14_N30
+\inst2|counter[11]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
+-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datad => VCC,
+	cin => \inst2|counter[10]~45\,
+	combout => \inst2|counter[11]~46_combout\,
+	cout => \inst2|counter[11]~47\);
+
+-- Location: FF_X51_Y14_N31
+\inst2|counter[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[11]~46_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(11));
+
+-- Location: LCCOMB_X51_Y13_N0
+\inst2|counter[12]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
+-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(12),
+	datad => VCC,
+	cin => \inst2|counter[11]~47\,
+	combout => \inst2|counter[12]~48_combout\,
+	cout => \inst2|counter[12]~49\);
+
+-- Location: FF_X51_Y13_N1
+\inst2|counter[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[12]~48_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(12));
+
+-- Location: LCCOMB_X51_Y13_N2
+\inst2|counter[13]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
+-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(13),
+	datad => VCC,
+	cin => \inst2|counter[12]~49\,
+	combout => \inst2|counter[13]~50_combout\,
+	cout => \inst2|counter[13]~51\);
+
+-- Location: FF_X51_Y13_N3
+\inst2|counter[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[13]~50_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(13));
+
+-- Location: LCCOMB_X51_Y13_N4
+\inst2|counter[14]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
+-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(14),
+	datad => VCC,
+	cin => \inst2|counter[13]~51\,
+	combout => \inst2|counter[14]~52_combout\,
+	cout => \inst2|counter[14]~53\);
+
+-- Location: FF_X51_Y13_N5
+\inst2|counter[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[14]~52_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(14));
+
+-- Location: LCCOMB_X51_Y13_N6
+\inst2|counter[15]~54\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
+-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datad => VCC,
+	cin => \inst2|counter[14]~53\,
+	combout => \inst2|counter[15]~54_combout\,
+	cout => \inst2|counter[15]~55\);
+
+-- Location: FF_X51_Y13_N7
+\inst2|counter[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[15]~54_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(15));
+
+-- Location: LCCOMB_X51_Y13_N8
+\inst2|counter[16]~56\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
+-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(16),
+	datad => VCC,
+	cin => \inst2|counter[15]~55\,
+	combout => \inst2|counter[16]~56_combout\,
+	cout => \inst2|counter[16]~57\);
+
+-- Location: FF_X51_Y13_N9
+\inst2|counter[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[16]~56_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(16));
+
+-- Location: LCCOMB_X51_Y13_N10
+\inst2|counter[17]~58\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
+-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(17),
+	datad => VCC,
+	cin => \inst2|counter[16]~57\,
+	combout => \inst2|counter[17]~58_combout\,
+	cout => \inst2|counter[17]~59\);
+
+-- Location: FF_X51_Y13_N11
+\inst2|counter[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[17]~58_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(17));
+
+-- Location: LCCOMB_X50_Y13_N20
+\inst2|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|counter\(16),
+	datac => \inst2|counter\(17),
+	datad => \inst2|counter\(14),
+	combout => \inst2|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X51_Y13_N12
+\inst2|counter[18]~60\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
+-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datad => VCC,
+	cin => \inst2|counter[17]~59\,
+	combout => \inst2|counter[18]~60_combout\,
+	cout => \inst2|counter[18]~61\);
+
+-- Location: FF_X51_Y13_N13
+\inst2|counter[18]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[18]~60_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(18));
+
+-- Location: LCCOMB_X51_Y13_N14
+\inst2|counter[19]~62\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
+-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(19),
+	datad => VCC,
+	cin => \inst2|counter[18]~61\,
+	combout => \inst2|counter[19]~62_combout\,
+	cout => \inst2|counter[19]~63\);
+
+-- Location: FF_X51_Y13_N15
+\inst2|counter[19]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[19]~62_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(19));
+
+-- Location: LCCOMB_X51_Y13_N16
+\inst2|counter[20]~64\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
+-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(20),
+	datad => VCC,
+	cin => \inst2|counter[19]~63\,
+	combout => \inst2|counter[20]~64_combout\,
+	cout => \inst2|counter[20]~65\);
+
+-- Location: FF_X51_Y13_N17
+\inst2|counter[20]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[20]~64_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(20));
+
+-- Location: LCCOMB_X51_Y13_N18
+\inst2|counter[21]~66\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
+-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(21),
+	datad => VCC,
+	cin => \inst2|counter[20]~65\,
+	combout => \inst2|counter[21]~66_combout\,
+	cout => \inst2|counter[21]~67\);
+
+-- Location: FF_X51_Y13_N19
+\inst2|counter[21]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[21]~66_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(21));
+
+-- Location: LCCOMB_X51_Y13_N20
+\inst2|counter[22]~68\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
+-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datad => VCC,
+	cin => \inst2|counter[21]~67\,
+	combout => \inst2|counter[22]~68_combout\,
+	cout => \inst2|counter[22]~69\);
+
+-- Location: FF_X51_Y13_N21
+\inst2|counter[22]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[22]~68_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(22));
+
+-- Location: LCCOMB_X51_Y13_N22
+\inst2|counter[23]~70\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(23),
+	cin => \inst2|counter[22]~69\,
+	combout => \inst2|counter[23]~70_combout\);
+
+-- Location: FF_X51_Y13_N23
+\inst2|counter[23]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[23]~70_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(23));
+
+-- Location: LCCOMB_X51_Y13_N24
+\inst2|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datab => \inst2|counter\(20),
+	datac => \inst2|counter\(19),
+	datad => \inst2|counter\(21),
+	combout => \inst2|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X51_Y13_N30
+\inst2|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datac => \inst2|counter\(23),
+	datad => \inst2|LessThan0~1_combout\,
+	combout => \inst2|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X51_Y14_N4
+\inst2|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datab => \inst2|counter\(8),
+	datac => \inst2|counter\(7),
+	datad => \inst2|counter\(10),
+	combout => \inst2|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X51_Y14_N0
+\inst2|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(2),
+	datab => \inst2|counter\(4),
+	datac => \inst2|counter\(0),
+	datad => \inst2|counter\(1),
+	combout => \inst2|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X51_Y14_N6
+\inst2|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100110111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datab => \inst2|counter\(5),
+	datac => \inst2|counter\(3),
+	datad => \inst2|LessThan0~3_combout\,
+	combout => \inst2|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X51_Y14_N2
+\inst2|LessThan0~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datab => \inst2|counter\(6),
+	datac => \inst2|LessThan0~5_combout\,
+	datad => \inst2|LessThan0~4_combout\,
+	combout => \inst2|LessThan0~6_combout\);
+
+-- Location: LCCOMB_X51_Y13_N28
+\inst2|LessThan0~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(16),
+	datab => \inst2|counter\(12),
+	datac => \inst2|counter\(13),
+	datad => \inst2|LessThan0~6_combout\,
+	combout => \inst2|LessThan0~7_combout\);
+
+-- Location: LCCOMB_X51_Y13_N26
+\inst2|LessThan0~8\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|LessThan0~0_combout\,
+	datac => \inst2|LessThan0~2_combout\,
+	datad => \inst2|LessThan0~7_combout\,
+	combout => \inst2|LessThan0~8_combout\);
+
+-- Location: LCCOMB_X52_Y13_N0
+\inst2|ledBuf~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst2|ledBuf~q\,
+	datad => \inst2|LessThan0~8_combout\,
+	combout => \inst2|ledBuf~0_combout\);
+
+-- Location: FF_X52_Y13_N1
+\inst2|ledBuf\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|ledBuf~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|ledBuf~q\);
+
+-- Location: IOIBUF_X38_Y34_N1
+\Address[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(7),
+	o => \Address[7]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N8
+\Address[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(6),
+	o => \Address[6]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N15
+\Address[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(5),
+	o => \Address[5]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N22
+\Address[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(4),
+	o => \Address[4]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N1
+\Address[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(3),
+	o => \Address[3]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N8
+\Address[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(2),
+	o => \Address[2]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N15
+\Address[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(1),
+	o => \Address[1]~input_o\);
+
+-- Location: IOIBUF_X38_Y34_N15
+\Address[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(0),
+	o => \Address[0]~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N1
+\nOE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nOE,
+	o => \nOE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N8
+\nWE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nWE,
+	o => \nWE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N15
+\nCE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nCE,
+	o => \nCE~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N1
+\Data[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(7),
+	o => \Data[7]~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N22
+\Data[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(6),
+	o => \Data[6]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N1
+\Data[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(5),
+	o => \Data[5]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N15
+\Data[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(4),
+	o => \Data[4]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N8
+\Data[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(3),
+	o => \Data[3]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N15
+\Data[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(2),
+	o => \Data[2]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N22
+\Data[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(1),
+	o => \Data[1]~input_o\);
+
+-- Location: IOIBUF_X40_Y34_N8
+\Data[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(0),
+	o => \Data[0]~input_o\);
+
+ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\;
+
+Data(7) <= \Data[7]~output_o\;
+
+Data(6) <= \Data[6]~output_o\;
+
+Data(5) <= \Data[5]~output_o\;
+
+Data(4) <= \Data[4]~output_o\;
+
+Data(3) <= \Data[3]~output_o\;
+
+Data(2) <= \Data[2]~output_o\;
+
+Data(1) <= \Data[1]~output_o\;
+
+Data(0) <= \Data[0]~output_o\;
+END structure;
+
+
diff --git a/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo b/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..7a8f05c
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_8_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,949 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C25Q240C8 Package PQFP240
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
+// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "MainController")
+  (DATE "03/12/2024 16:24:29")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\FPGA_LED_1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1403:1403:1403) (1502:1502:1502))
+        (IOPATH i o (2195:2195:2195) (2297:2297:2297))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\FPGA_CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (899:899:899) (1014:1014:1014))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\FPGA_CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (190:190:190) (179:179:179))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[0\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (567:567:567) (600:600:600))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[1\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (576:576:576) (592:592:592))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[2\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (566:566:566) (594:594:594))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[3\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[4\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (615:615:615))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[5\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[6\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[7\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (561:561:561) (592:592:592))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[8\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[9\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[10\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (421:421:421))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[11\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[12\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[13\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (357:357:357) (434:434:434))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[14\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[15\]\~54\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (460:460:460))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[16\]\~56\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[17\]\~58\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (866:866:866))
+        (PORT datab (635:635:635) (645:645:645))
+        (PORT datac (534:534:534) (562:562:562))
+        (PORT datad (572:572:572) (584:584:584))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[18\]\~60\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[18\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[19\]\~62\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[19\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[20\]\~64\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[20\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[21\]\~66\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (424:424:424))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[21\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[22\]\~68\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[22\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[23\]\~70\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (821:821:821) (810:810:810))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[23\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (302:302:302) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (427:427:427))
+        (PORT datac (776:776:776) (761:761:761))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (434:434:434))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datac (319:319:319) (396:396:396))
+        (PORT datad (304:304:304) (379:379:379))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (445:445:445))
+        (PORT datab (359:359:359) (437:437:437))
+        (PORT datac (318:318:318) (396:396:396))
+        (PORT datad (319:319:319) (389:389:389))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (613:613:613))
+        (PORT datab (342:342:342) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (438:438:438))
+        (PORT datab (344:344:344) (427:427:427))
+        (PORT datac (235:235:235) (262:262:262))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (617:617:617))
+        (PORT datab (345:345:345) (429:429:429))
+        (PORT datac (541:541:541) (559:559:559))
+        (PORT datad (816:816:816) (741:741:741))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~8\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (464:464:464))
+        (PORT datab (531:531:531) (492:492:492))
+        (PORT datac (235:235:235) (262:262:262))
+        (PORT datad (236:236:236) (255:255:255))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|ledBuf\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (747:747:747) (674:674:674))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|ledBuf\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2411:2411:2411) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+)
diff --git a/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho b/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..d2c6f05
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_min_1200mv_0c_fast.vho
@@ -0,0 +1,1526 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
+
+-- DATE "03/12/2024 16:24:29"
+
+-- 
+-- Device: Altera EP3C25Q240C8 Package PQFP240
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	MainController IS
+    PORT (
+	FPGA_LED_1 : OUT std_logic;
+	FPGA_CLK : IN std_logic;
+	Data : INOUT std_logic_vector(7 DOWNTO 0);
+	Address : IN std_logic_vector(7 DOWNTO 0);
+	nOE : IN std_logic;
+	nWE : IN std_logic;
+	nCE : IN std_logic
+	);
+END MainController;
+
+-- Design Ports Information
+-- FPGA_LED_1	=>  Location: PIN_166,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Address[7]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[6]	=>  Location: PIN_230,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[5]	=>  Location: PIN_235,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[4]	=>  Location: PIN_232,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[3]	=>  Location: PIN_233,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[2]	=>  Location: PIN_234,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[1]	=>  Location: PIN_231,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Address[0]	=>  Location: PIN_196,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nOE	=>  Location: PIN_217,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nWE	=>  Location: PIN_218,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- nCE	=>  Location: PIN_219,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- Data[7]	=>  Location: PIN_221,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[6]	=>  Location: PIN_223,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[5]	=>  Location: PIN_224,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[4]	=>  Location: PIN_226,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[3]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[2]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[1]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- Data[0]	=>  Location: PIN_194,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+-- FPGA_CLK	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF MainController IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_FPGA_LED_1 : std_logic;
+SIGNAL ww_FPGA_CLK : std_logic;
+SIGNAL ww_Address : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_nOE : std_logic;
+SIGNAL ww_nWE : std_logic;
+SIGNAL ww_nCE : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Address[7]~input_o\ : std_logic;
+SIGNAL \Address[6]~input_o\ : std_logic;
+SIGNAL \Address[5]~input_o\ : std_logic;
+SIGNAL \Address[4]~input_o\ : std_logic;
+SIGNAL \Address[3]~input_o\ : std_logic;
+SIGNAL \Address[2]~input_o\ : std_logic;
+SIGNAL \Address[1]~input_o\ : std_logic;
+SIGNAL \Address[0]~input_o\ : std_logic;
+SIGNAL \nOE~input_o\ : std_logic;
+SIGNAL \nWE~input_o\ : std_logic;
+SIGNAL \nCE~input_o\ : std_logic;
+SIGNAL \Data[7]~input_o\ : std_logic;
+SIGNAL \Data[6]~input_o\ : std_logic;
+SIGNAL \Data[5]~input_o\ : std_logic;
+SIGNAL \Data[4]~input_o\ : std_logic;
+SIGNAL \Data[3]~input_o\ : std_logic;
+SIGNAL \Data[2]~input_o\ : std_logic;
+SIGNAL \Data[1]~input_o\ : std_logic;
+SIGNAL \Data[0]~input_o\ : std_logic;
+SIGNAL \Data[7]~output_o\ : std_logic;
+SIGNAL \Data[6]~output_o\ : std_logic;
+SIGNAL \Data[5]~output_o\ : std_logic;
+SIGNAL \Data[4]~output_o\ : std_logic;
+SIGNAL \Data[3]~output_o\ : std_logic;
+SIGNAL \Data[2]~output_o\ : std_logic;
+SIGNAL \Data[1]~output_o\ : std_logic;
+SIGNAL \Data[0]~output_o\ : std_logic;
+SIGNAL \FPGA_LED_1~output_o\ : std_logic;
+SIGNAL \FPGA_CLK~input_o\ : std_logic;
+SIGNAL \FPGA_CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst2|counter[0]~24_combout\ : std_logic;
+SIGNAL \inst2|counter[0]~25\ : std_logic;
+SIGNAL \inst2|counter[1]~26_combout\ : std_logic;
+SIGNAL \inst2|counter[1]~27\ : std_logic;
+SIGNAL \inst2|counter[2]~28_combout\ : std_logic;
+SIGNAL \inst2|counter[2]~29\ : std_logic;
+SIGNAL \inst2|counter[3]~30_combout\ : std_logic;
+SIGNAL \inst2|counter[3]~31\ : std_logic;
+SIGNAL \inst2|counter[4]~32_combout\ : std_logic;
+SIGNAL \inst2|counter[4]~33\ : std_logic;
+SIGNAL \inst2|counter[5]~34_combout\ : std_logic;
+SIGNAL \inst2|counter[5]~35\ : std_logic;
+SIGNAL \inst2|counter[6]~36_combout\ : std_logic;
+SIGNAL \inst2|counter[6]~37\ : std_logic;
+SIGNAL \inst2|counter[7]~38_combout\ : std_logic;
+SIGNAL \inst2|counter[7]~39\ : std_logic;
+SIGNAL \inst2|counter[8]~40_combout\ : std_logic;
+SIGNAL \inst2|counter[8]~41\ : std_logic;
+SIGNAL \inst2|counter[9]~42_combout\ : std_logic;
+SIGNAL \inst2|counter[9]~43\ : std_logic;
+SIGNAL \inst2|counter[10]~44_combout\ : std_logic;
+SIGNAL \inst2|counter[10]~45\ : std_logic;
+SIGNAL \inst2|counter[11]~46_combout\ : std_logic;
+SIGNAL \inst2|counter[11]~47\ : std_logic;
+SIGNAL \inst2|counter[12]~48_combout\ : std_logic;
+SIGNAL \inst2|counter[12]~49\ : std_logic;
+SIGNAL \inst2|counter[13]~50_combout\ : std_logic;
+SIGNAL \inst2|counter[13]~51\ : std_logic;
+SIGNAL \inst2|counter[14]~52_combout\ : std_logic;
+SIGNAL \inst2|counter[14]~53\ : std_logic;
+SIGNAL \inst2|counter[15]~54_combout\ : std_logic;
+SIGNAL \inst2|counter[15]~55\ : std_logic;
+SIGNAL \inst2|counter[16]~56_combout\ : std_logic;
+SIGNAL \inst2|counter[16]~57\ : std_logic;
+SIGNAL \inst2|counter[17]~58_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~0_combout\ : std_logic;
+SIGNAL \inst2|counter[17]~59\ : std_logic;
+SIGNAL \inst2|counter[18]~60_combout\ : std_logic;
+SIGNAL \inst2|counter[18]~61\ : std_logic;
+SIGNAL \inst2|counter[19]~62_combout\ : std_logic;
+SIGNAL \inst2|counter[19]~63\ : std_logic;
+SIGNAL \inst2|counter[20]~64_combout\ : std_logic;
+SIGNAL \inst2|counter[20]~65\ : std_logic;
+SIGNAL \inst2|counter[21]~66_combout\ : std_logic;
+SIGNAL \inst2|counter[21]~67\ : std_logic;
+SIGNAL \inst2|counter[22]~68_combout\ : std_logic;
+SIGNAL \inst2|counter[22]~69\ : std_logic;
+SIGNAL \inst2|counter[23]~70_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~1_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~2_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~5_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~3_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~4_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~6_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~7_combout\ : std_logic;
+SIGNAL \inst2|LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~0_combout\ : std_logic;
+SIGNAL \inst2|ledBuf~q\ : std_logic;
+SIGNAL \inst2|counter\ : std_logic_vector(23 DOWNTO 0);
+SIGNAL \inst2|ALT_INV_LessThan0~8_combout\ : std_logic;
+SIGNAL \inst2|ALT_INV_ledBuf~q\ : std_logic;
+
+BEGIN
+
+FPGA_LED_1 <= ww_FPGA_LED_1;
+ww_FPGA_CLK <= FPGA_CLK;
+ww_Address <= Address;
+ww_nOE <= nOE;
+ww_nWE <= nWE;
+ww_nCE <= nCE;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\FPGA_CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \FPGA_CLK~input_o\);
+\inst2|ALT_INV_LessThan0~8_combout\ <= NOT \inst2|LessThan0~8_combout\;
+\inst2|ALT_INV_ledBuf~q\ <= NOT \inst2|ledBuf~q\;
+
+-- Location: IOOBUF_X18_Y34_N2
+\Data[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[7]~output_o\);
+
+-- Location: IOOBUF_X18_Y34_N23
+\Data[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[6]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N2
+\Data[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[5]~output_o\);
+
+-- Location: IOOBUF_X16_Y34_N16
+\Data[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[4]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N9
+\Data[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[3]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N16
+\Data[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[2]~output_o\);
+
+-- Location: IOOBUF_X45_Y34_N23
+\Data[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[1]~output_o\);
+
+-- Location: IOOBUF_X40_Y34_N9
+\Data[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "true")
+-- pragma translate_on
+PORT MAP (
+	i => VCC,
+	devoe => ww_devoe,
+	o => \Data[0]~output_o\);
+
+-- Location: IOOBUF_X53_Y22_N2
+\FPGA_LED_1~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|ALT_INV_ledBuf~q\,
+	devoe => ww_devoe,
+	o => \FPGA_LED_1~output_o\);
+
+-- Location: IOIBUF_X0_Y16_N1
+\FPGA_CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_FPGA_CLK,
+	o => \FPGA_CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\FPGA_CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \FPGA_CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \FPGA_CLK~inputclkctrl_outclk\);
+
+-- Location: LCCOMB_X51_Y14_N8
+\inst2|counter[0]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[0]~24_combout\ = \inst2|counter\(0) $ (VCC)
+-- \inst2|counter[0]~25\ = CARRY(\inst2|counter\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101010110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(0),
+	datad => VCC,
+	combout => \inst2|counter[0]~24_combout\,
+	cout => \inst2|counter[0]~25\);
+
+-- Location: FF_X51_Y14_N9
+\inst2|counter[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[0]~24_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(0));
+
+-- Location: LCCOMB_X51_Y14_N10
+\inst2|counter[1]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[1]~26_combout\ = (\inst2|counter\(1) & (!\inst2|counter[0]~25\)) # (!\inst2|counter\(1) & ((\inst2|counter[0]~25\) # (GND)))
+-- \inst2|counter[1]~27\ = CARRY((!\inst2|counter[0]~25\) # (!\inst2|counter\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(1),
+	datad => VCC,
+	cin => \inst2|counter[0]~25\,
+	combout => \inst2|counter[1]~26_combout\,
+	cout => \inst2|counter[1]~27\);
+
+-- Location: FF_X51_Y14_N11
+\inst2|counter[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[1]~26_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(1));
+
+-- Location: LCCOMB_X51_Y14_N12
+\inst2|counter[2]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[2]~28_combout\ = (\inst2|counter\(2) & (\inst2|counter[1]~27\ $ (GND))) # (!\inst2|counter\(2) & (!\inst2|counter[1]~27\ & VCC))
+-- \inst2|counter[2]~29\ = CARRY((\inst2|counter\(2) & !\inst2|counter[1]~27\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(2),
+	datad => VCC,
+	cin => \inst2|counter[1]~27\,
+	combout => \inst2|counter[2]~28_combout\,
+	cout => \inst2|counter[2]~29\);
+
+-- Location: FF_X51_Y14_N13
+\inst2|counter[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[2]~28_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(2));
+
+-- Location: LCCOMB_X51_Y14_N14
+\inst2|counter[3]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[3]~30_combout\ = (\inst2|counter\(3) & (!\inst2|counter[2]~29\)) # (!\inst2|counter\(3) & ((\inst2|counter[2]~29\) # (GND)))
+-- \inst2|counter[3]~31\ = CARRY((!\inst2|counter[2]~29\) # (!\inst2|counter\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(3),
+	datad => VCC,
+	cin => \inst2|counter[2]~29\,
+	combout => \inst2|counter[3]~30_combout\,
+	cout => \inst2|counter[3]~31\);
+
+-- Location: FF_X51_Y14_N15
+\inst2|counter[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[3]~30_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(3));
+
+-- Location: LCCOMB_X51_Y14_N16
+\inst2|counter[4]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[4]~32_combout\ = (\inst2|counter\(4) & (\inst2|counter[3]~31\ $ (GND))) # (!\inst2|counter\(4) & (!\inst2|counter[3]~31\ & VCC))
+-- \inst2|counter[4]~33\ = CARRY((\inst2|counter\(4) & !\inst2|counter[3]~31\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datad => VCC,
+	cin => \inst2|counter[3]~31\,
+	combout => \inst2|counter[4]~32_combout\,
+	cout => \inst2|counter[4]~33\);
+
+-- Location: FF_X51_Y14_N17
+\inst2|counter[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[4]~32_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(4));
+
+-- Location: LCCOMB_X51_Y14_N18
+\inst2|counter[5]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[5]~34_combout\ = (\inst2|counter\(5) & (!\inst2|counter[4]~33\)) # (!\inst2|counter\(5) & ((\inst2|counter[4]~33\) # (GND)))
+-- \inst2|counter[5]~35\ = CARRY((!\inst2|counter[4]~33\) # (!\inst2|counter\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(5),
+	datad => VCC,
+	cin => \inst2|counter[4]~33\,
+	combout => \inst2|counter[5]~34_combout\,
+	cout => \inst2|counter[5]~35\);
+
+-- Location: FF_X51_Y14_N19
+\inst2|counter[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[5]~34_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(5));
+
+-- Location: LCCOMB_X51_Y14_N20
+\inst2|counter[6]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[6]~36_combout\ = (\inst2|counter\(6) & (\inst2|counter[5]~35\ $ (GND))) # (!\inst2|counter\(6) & (!\inst2|counter[5]~35\ & VCC))
+-- \inst2|counter[6]~37\ = CARRY((\inst2|counter\(6) & !\inst2|counter[5]~35\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(6),
+	datad => VCC,
+	cin => \inst2|counter[5]~35\,
+	combout => \inst2|counter[6]~36_combout\,
+	cout => \inst2|counter[6]~37\);
+
+-- Location: FF_X51_Y14_N21
+\inst2|counter[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[6]~36_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(6));
+
+-- Location: LCCOMB_X51_Y14_N22
+\inst2|counter[7]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[7]~38_combout\ = (\inst2|counter\(7) & (!\inst2|counter[6]~37\)) # (!\inst2|counter\(7) & ((\inst2|counter[6]~37\) # (GND)))
+-- \inst2|counter[7]~39\ = CARRY((!\inst2|counter[6]~37\) # (!\inst2|counter\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(7),
+	datad => VCC,
+	cin => \inst2|counter[6]~37\,
+	combout => \inst2|counter[7]~38_combout\,
+	cout => \inst2|counter[7]~39\);
+
+-- Location: FF_X51_Y14_N23
+\inst2|counter[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[7]~38_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(7));
+
+-- Location: LCCOMB_X51_Y14_N24
+\inst2|counter[8]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[8]~40_combout\ = (\inst2|counter\(8) & (\inst2|counter[7]~39\ $ (GND))) # (!\inst2|counter\(8) & (!\inst2|counter[7]~39\ & VCC))
+-- \inst2|counter[8]~41\ = CARRY((\inst2|counter\(8) & !\inst2|counter[7]~39\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(8),
+	datad => VCC,
+	cin => \inst2|counter[7]~39\,
+	combout => \inst2|counter[8]~40_combout\,
+	cout => \inst2|counter[8]~41\);
+
+-- Location: FF_X51_Y14_N25
+\inst2|counter[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[8]~40_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(8));
+
+-- Location: LCCOMB_X51_Y14_N26
+\inst2|counter[9]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[9]~42_combout\ = (\inst2|counter\(9) & (!\inst2|counter[8]~41\)) # (!\inst2|counter\(9) & ((\inst2|counter[8]~41\) # (GND)))
+-- \inst2|counter[9]~43\ = CARRY((!\inst2|counter[8]~41\) # (!\inst2|counter\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datad => VCC,
+	cin => \inst2|counter[8]~41\,
+	combout => \inst2|counter[9]~42_combout\,
+	cout => \inst2|counter[9]~43\);
+
+-- Location: FF_X51_Y14_N27
+\inst2|counter[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[9]~42_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(9));
+
+-- Location: LCCOMB_X51_Y14_N28
+\inst2|counter[10]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[10]~44_combout\ = (\inst2|counter\(10) & (\inst2|counter[9]~43\ $ (GND))) # (!\inst2|counter\(10) & (!\inst2|counter[9]~43\ & VCC))
+-- \inst2|counter[10]~45\ = CARRY((\inst2|counter\(10) & !\inst2|counter[9]~43\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(10),
+	datad => VCC,
+	cin => \inst2|counter[9]~43\,
+	combout => \inst2|counter[10]~44_combout\,
+	cout => \inst2|counter[10]~45\);
+
+-- Location: FF_X51_Y14_N29
+\inst2|counter[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[10]~44_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(10));
+
+-- Location: LCCOMB_X51_Y14_N30
+\inst2|counter[11]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[11]~46_combout\ = (\inst2|counter\(11) & (!\inst2|counter[10]~45\)) # (!\inst2|counter\(11) & ((\inst2|counter[10]~45\) # (GND)))
+-- \inst2|counter[11]~47\ = CARRY((!\inst2|counter[10]~45\) # (!\inst2|counter\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datad => VCC,
+	cin => \inst2|counter[10]~45\,
+	combout => \inst2|counter[11]~46_combout\,
+	cout => \inst2|counter[11]~47\);
+
+-- Location: FF_X51_Y14_N31
+\inst2|counter[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[11]~46_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(11));
+
+-- Location: LCCOMB_X51_Y13_N0
+\inst2|counter[12]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[12]~48_combout\ = (\inst2|counter\(12) & (\inst2|counter[11]~47\ $ (GND))) # (!\inst2|counter\(12) & (!\inst2|counter[11]~47\ & VCC))
+-- \inst2|counter[12]~49\ = CARRY((\inst2|counter\(12) & !\inst2|counter[11]~47\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(12),
+	datad => VCC,
+	cin => \inst2|counter[11]~47\,
+	combout => \inst2|counter[12]~48_combout\,
+	cout => \inst2|counter[12]~49\);
+
+-- Location: FF_X51_Y13_N1
+\inst2|counter[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[12]~48_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(12));
+
+-- Location: LCCOMB_X51_Y13_N2
+\inst2|counter[13]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[13]~50_combout\ = (\inst2|counter\(13) & (!\inst2|counter[12]~49\)) # (!\inst2|counter\(13) & ((\inst2|counter[12]~49\) # (GND)))
+-- \inst2|counter[13]~51\ = CARRY((!\inst2|counter[12]~49\) # (!\inst2|counter\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(13),
+	datad => VCC,
+	cin => \inst2|counter[12]~49\,
+	combout => \inst2|counter[13]~50_combout\,
+	cout => \inst2|counter[13]~51\);
+
+-- Location: FF_X51_Y13_N3
+\inst2|counter[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[13]~50_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(13));
+
+-- Location: LCCOMB_X51_Y13_N4
+\inst2|counter[14]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[14]~52_combout\ = (\inst2|counter\(14) & (\inst2|counter[13]~51\ $ (GND))) # (!\inst2|counter\(14) & (!\inst2|counter[13]~51\ & VCC))
+-- \inst2|counter[14]~53\ = CARRY((\inst2|counter\(14) & !\inst2|counter[13]~51\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(14),
+	datad => VCC,
+	cin => \inst2|counter[13]~51\,
+	combout => \inst2|counter[14]~52_combout\,
+	cout => \inst2|counter[14]~53\);
+
+-- Location: FF_X51_Y13_N5
+\inst2|counter[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[14]~52_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(14));
+
+-- Location: LCCOMB_X51_Y13_N6
+\inst2|counter[15]~54\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[15]~54_combout\ = (\inst2|counter\(15) & (!\inst2|counter[14]~53\)) # (!\inst2|counter\(15) & ((\inst2|counter[14]~53\) # (GND)))
+-- \inst2|counter[15]~55\ = CARRY((!\inst2|counter[14]~53\) # (!\inst2|counter\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datad => VCC,
+	cin => \inst2|counter[14]~53\,
+	combout => \inst2|counter[15]~54_combout\,
+	cout => \inst2|counter[15]~55\);
+
+-- Location: FF_X51_Y13_N7
+\inst2|counter[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[15]~54_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(15));
+
+-- Location: LCCOMB_X51_Y13_N8
+\inst2|counter[16]~56\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[16]~56_combout\ = (\inst2|counter\(16) & (\inst2|counter[15]~55\ $ (GND))) # (!\inst2|counter\(16) & (!\inst2|counter[15]~55\ & VCC))
+-- \inst2|counter[16]~57\ = CARRY((\inst2|counter\(16) & !\inst2|counter[15]~55\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(16),
+	datad => VCC,
+	cin => \inst2|counter[15]~55\,
+	combout => \inst2|counter[16]~56_combout\,
+	cout => \inst2|counter[16]~57\);
+
+-- Location: FF_X51_Y13_N9
+\inst2|counter[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[16]~56_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(16));
+
+-- Location: LCCOMB_X51_Y13_N10
+\inst2|counter[17]~58\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[17]~58_combout\ = (\inst2|counter\(17) & (!\inst2|counter[16]~57\)) # (!\inst2|counter\(17) & ((\inst2|counter[16]~57\) # (GND)))
+-- \inst2|counter[17]~59\ = CARRY((!\inst2|counter[16]~57\) # (!\inst2|counter\(17)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(17),
+	datad => VCC,
+	cin => \inst2|counter[16]~57\,
+	combout => \inst2|counter[17]~58_combout\,
+	cout => \inst2|counter[17]~59\);
+
+-- Location: FF_X51_Y13_N11
+\inst2|counter[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[17]~58_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(17));
+
+-- Location: LCCOMB_X50_Y13_N20
+\inst2|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~0_combout\ = ((!\inst2|counter\(15) & (!\inst2|counter\(16) & !\inst2|counter\(14)))) # (!\inst2|counter\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|counter\(16),
+	datac => \inst2|counter\(17),
+	datad => \inst2|counter\(14),
+	combout => \inst2|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X51_Y13_N12
+\inst2|counter[18]~60\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[18]~60_combout\ = (\inst2|counter\(18) & (\inst2|counter[17]~59\ $ (GND))) # (!\inst2|counter\(18) & (!\inst2|counter[17]~59\ & VCC))
+-- \inst2|counter[18]~61\ = CARRY((\inst2|counter\(18) & !\inst2|counter[17]~59\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datad => VCC,
+	cin => \inst2|counter[17]~59\,
+	combout => \inst2|counter[18]~60_combout\,
+	cout => \inst2|counter[18]~61\);
+
+-- Location: FF_X51_Y13_N13
+\inst2|counter[18]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[18]~60_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(18));
+
+-- Location: LCCOMB_X51_Y13_N14
+\inst2|counter[19]~62\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[19]~62_combout\ = (\inst2|counter\(19) & (!\inst2|counter[18]~61\)) # (!\inst2|counter\(19) & ((\inst2|counter[18]~61\) # (GND)))
+-- \inst2|counter[19]~63\ = CARRY((!\inst2|counter[18]~61\) # (!\inst2|counter\(19)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(19),
+	datad => VCC,
+	cin => \inst2|counter[18]~61\,
+	combout => \inst2|counter[19]~62_combout\,
+	cout => \inst2|counter[19]~63\);
+
+-- Location: FF_X51_Y13_N15
+\inst2|counter[19]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[19]~62_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(19));
+
+-- Location: LCCOMB_X51_Y13_N16
+\inst2|counter[20]~64\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[20]~64_combout\ = (\inst2|counter\(20) & (\inst2|counter[19]~63\ $ (GND))) # (!\inst2|counter\(20) & (!\inst2|counter[19]~63\ & VCC))
+-- \inst2|counter[20]~65\ = CARRY((\inst2|counter\(20) & !\inst2|counter[19]~63\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(20),
+	datad => VCC,
+	cin => \inst2|counter[19]~63\,
+	combout => \inst2|counter[20]~64_combout\,
+	cout => \inst2|counter[20]~65\);
+
+-- Location: FF_X51_Y13_N17
+\inst2|counter[20]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[20]~64_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(20));
+
+-- Location: LCCOMB_X51_Y13_N18
+\inst2|counter[21]~66\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[21]~66_combout\ = (\inst2|counter\(21) & (!\inst2|counter[20]~65\)) # (!\inst2|counter\(21) & ((\inst2|counter[20]~65\) # (GND)))
+-- \inst2|counter[21]~67\ = CARRY((!\inst2|counter[20]~65\) # (!\inst2|counter\(21)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(21),
+	datad => VCC,
+	cin => \inst2|counter[20]~65\,
+	combout => \inst2|counter[21]~66_combout\,
+	cout => \inst2|counter[21]~67\);
+
+-- Location: FF_X51_Y13_N19
+\inst2|counter[21]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[21]~66_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(21));
+
+-- Location: LCCOMB_X51_Y13_N20
+\inst2|counter[22]~68\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[22]~68_combout\ = (\inst2|counter\(22) & (\inst2|counter[21]~67\ $ (GND))) # (!\inst2|counter\(22) & (!\inst2|counter[21]~67\ & VCC))
+-- \inst2|counter[22]~69\ = CARRY((\inst2|counter\(22) & !\inst2|counter[21]~67\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datad => VCC,
+	cin => \inst2|counter[21]~67\,
+	combout => \inst2|counter[22]~68_combout\,
+	cout => \inst2|counter[22]~69\);
+
+-- Location: FF_X51_Y13_N21
+\inst2|counter[22]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[22]~68_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(22));
+
+-- Location: LCCOMB_X51_Y13_N22
+\inst2|counter[23]~70\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|counter[23]~70_combout\ = \inst2|counter\(23) $ (\inst2|counter[22]~69\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(23),
+	cin => \inst2|counter[22]~69\,
+	combout => \inst2|counter[23]~70_combout\);
+
+-- Location: FF_X51_Y13_N23
+\inst2|counter[23]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|counter[23]~70_combout\,
+	sclr => \inst2|ALT_INV_LessThan0~8_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|counter\(23));
+
+-- Location: LCCOMB_X51_Y13_N24
+\inst2|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~1_combout\ = (((!\inst2|counter\(21)) # (!\inst2|counter\(19))) # (!\inst2|counter\(20))) # (!\inst2|counter\(18))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(18),
+	datab => \inst2|counter\(20),
+	datac => \inst2|counter\(19),
+	datad => \inst2|counter\(21),
+	combout => \inst2|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X51_Y13_N30
+\inst2|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~2_combout\ = ((\inst2|LessThan0~1_combout\) # (!\inst2|counter\(23))) # (!\inst2|counter\(22))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst2|counter\(22),
+	datac => \inst2|counter\(23),
+	datad => \inst2|LessThan0~1_combout\,
+	combout => \inst2|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X51_Y14_N4
+\inst2|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~5_combout\ = (!\inst2|counter\(9) & (!\inst2|counter\(8) & (!\inst2|counter\(7) & !\inst2|counter\(10))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(9),
+	datab => \inst2|counter\(8),
+	datac => \inst2|counter\(7),
+	datad => \inst2|counter\(10),
+	combout => \inst2|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X51_Y14_N0
+\inst2|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~3_combout\ = (!\inst2|counter\(2) & (!\inst2|counter\(4) & ((!\inst2|counter\(1)) # (!\inst2|counter\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(2),
+	datab => \inst2|counter\(4),
+	datac => \inst2|counter\(0),
+	datad => \inst2|counter\(1),
+	combout => \inst2|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X51_Y14_N6
+\inst2|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~4_combout\ = ((\inst2|LessThan0~3_combout\) # ((!\inst2|counter\(4) & !\inst2|counter\(3)))) # (!\inst2|counter\(5))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100110111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(4),
+	datab => \inst2|counter\(5),
+	datac => \inst2|counter\(3),
+	datad => \inst2|LessThan0~3_combout\,
+	combout => \inst2|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X51_Y14_N2
+\inst2|LessThan0~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~6_combout\ = (!\inst2|counter\(11) & (!\inst2|counter\(6) & (\inst2|LessThan0~5_combout\ & \inst2|LessThan0~4_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(11),
+	datab => \inst2|counter\(6),
+	datac => \inst2|LessThan0~5_combout\,
+	datad => \inst2|LessThan0~4_combout\,
+	combout => \inst2|LessThan0~6_combout\);
+
+-- Location: LCCOMB_X51_Y13_N28
+\inst2|LessThan0~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~7_combout\ = (\inst2|counter\(16)) # ((\inst2|counter\(13)) # ((\inst2|counter\(12) & !\inst2|LessThan0~6_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(16),
+	datab => \inst2|counter\(12),
+	datac => \inst2|counter\(13),
+	datad => \inst2|LessThan0~6_combout\,
+	combout => \inst2|LessThan0~7_combout\);
+
+-- Location: LCCOMB_X51_Y13_N26
+\inst2|LessThan0~8\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|LessThan0~8_combout\ = (\inst2|LessThan0~0_combout\) # ((\inst2|LessThan0~2_combout\) # ((!\inst2|counter\(15) & !\inst2|LessThan0~7_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|counter\(15),
+	datab => \inst2|LessThan0~0_combout\,
+	datac => \inst2|LessThan0~2_combout\,
+	datad => \inst2|LessThan0~7_combout\,
+	combout => \inst2|LessThan0~8_combout\);
+
+-- Location: LCCOMB_X52_Y13_N0
+\inst2|ledBuf~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|ledBuf~0_combout\ = \inst2|ledBuf~q\ $ (!\inst2|LessThan0~8_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst2|ledBuf~q\,
+	datad => \inst2|LessThan0~8_combout\,
+	combout => \inst2|ledBuf~0_combout\);
+
+-- Location: FF_X52_Y13_N1
+\inst2|ledBuf\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \FPGA_CLK~inputclkctrl_outclk\,
+	d => \inst2|ledBuf~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2|ledBuf~q\);
+
+-- Location: IOIBUF_X38_Y34_N1
+\Address[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(7),
+	o => \Address[7]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N8
+\Address[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(6),
+	o => \Address[6]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N15
+\Address[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(5),
+	o => \Address[5]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N22
+\Address[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(4),
+	o => \Address[4]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N1
+\Address[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(3),
+	o => \Address[3]~input_o\);
+
+-- Location: IOIBUF_X7_Y34_N8
+\Address[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(2),
+	o => \Address[2]~input_o\);
+
+-- Location: IOIBUF_X14_Y34_N15
+\Address[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(1),
+	o => \Address[1]~input_o\);
+
+-- Location: IOIBUF_X38_Y34_N15
+\Address[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Address(0),
+	o => \Address[0]~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N1
+\nOE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nOE,
+	o => \nOE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N8
+\nWE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nWE,
+	o => \nWE~input_o\);
+
+-- Location: IOIBUF_X20_Y34_N15
+\nCE~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_nCE,
+	o => \nCE~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N1
+\Data[7]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(7),
+	o => \Data[7]~input_o\);
+
+-- Location: IOIBUF_X18_Y34_N22
+\Data[6]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(6),
+	o => \Data[6]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N1
+\Data[5]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(5),
+	o => \Data[5]~input_o\);
+
+-- Location: IOIBUF_X16_Y34_N15
+\Data[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(4),
+	o => \Data[4]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N8
+\Data[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(3),
+	o => \Data[3]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N15
+\Data[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(2),
+	o => \Data[2]~input_o\);
+
+-- Location: IOIBUF_X45_Y34_N22
+\Data[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(1),
+	o => \Data[1]~input_o\);
+
+-- Location: IOIBUF_X40_Y34_N8
+\Data[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => Data(0),
+	o => \Data[0]~input_o\);
+
+ww_FPGA_LED_1 <= \FPGA_LED_1~output_o\;
+
+Data(7) <= \Data[7]~output_o\;
+
+Data(6) <= \Data[6]~output_o\;
+
+Data(5) <= \Data[5]~output_o\;
+
+Data(4) <= \Data[4]~output_o\;
+
+Data(3) <= \Data[3]~output_o\;
+
+Data(2) <= \Data[2]~output_o\;
+
+Data(1) <= \Data[1]~output_o\;
+
+Data(0) <= \Data[0]~output_o\;
+END structure;
+
+
diff --git a/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo b/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..ac15010
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,949 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C25Q240C8 Package PQFP240
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C25Q240C8,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "MainController")
+  (DATE "03/12/2024 16:24:29")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\FPGA_LED_1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (677:677:677) (604:604:604))
+        (IOPATH i o (1309:1309:1309) (1354:1354:1354))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\FPGA_CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (320:320:320) (873:873:873))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\FPGA_CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (91:91:91) (78:78:78))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[0\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (266:266:266))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[1\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (212:212:212) (265:265:265))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[2\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (209:209:209) (265:265:265))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[3\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1150:1150:1150))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[4\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (217:217:217) (273:273:273))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[5\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[6\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1150:1150:1150))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[7\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (211:211:211) (265:265:265))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[8\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (183:183:183))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[9\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (918:918:918) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[10\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (182:182:182))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1150:1150:1150))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[11\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (134:134:134) (187:187:187))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1150:1150:1150))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (612:612:612) (611:611:611))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[12\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (183:183:183))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[13\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[14\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[15\]\~54\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (199:199:199))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (917:917:917) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[16\]\~56\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (189:189:189))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (917:917:917) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[17\]\~58\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (917:917:917) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (331:331:331) (397:397:397))
+        (PORT datab (233:233:233) (291:291:291))
+        (PORT datac (200:200:200) (249:249:249))
+        (PORT datad (212:212:212) (260:260:260))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[18\]\~60\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (190:190:190))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[18\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (917:917:917) (925:925:925))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[19\]\~62\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[19\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[20\]\~64\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[20\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[21\]\~66\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[21\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[22\]\~68\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (186:186:186))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[22\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[23\]\~70\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (368:368:368))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[23\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1151:1151:1151))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (372:372:372))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (190:190:190))
+        (PORT datab (135:135:135) (184:184:184))
+        (PORT datac (122:122:122) (164:164:164))
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (PORT datac (289:289:289) (344:344:344))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (190:190:190))
+        (PORT datab (137:137:137) (186:186:186))
+        (PORT datac (130:130:130) (170:170:170))
+        (PORT datad (124:124:124) (162:162:162))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (PORT datab (143:143:143) (192:192:192))
+        (PORT datac (128:128:128) (168:168:168))
+        (PORT datad (129:129:129) (165:165:165))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (274:274:274))
+        (PORT datab (135:135:135) (185:185:185))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (PORT datab (137:137:137) (188:188:188))
+        (PORT datac (89:89:89) (109:109:109))
+        (PORT datad (90:90:90) (106:106:106))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (278:278:278))
+        (PORT datab (138:138:138) (189:189:189))
+        (PORT datac (203:203:203) (249:249:249))
+        (PORT datad (301:301:301) (355:355:355))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~8\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (151:151:151) (205:205:205))
+        (PORT datab (185:185:185) (222:222:222))
+        (PORT datac (88:88:88) (110:110:110))
+        (PORT datad (89:89:89) (106:106:106))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|ledBuf\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (274:274:274) (308:308:308))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|ledBuf\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1115:1115:1115) (1152:1152:1152))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/MainController/simulation/modelsim/MainController_modelsim.xrf b/MainController/simulation/modelsim/MainController_modelsim.xrf
new file mode 100644
index 0000000..bb35dbd
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_modelsim.xrf
@@ -0,0 +1,108 @@
+vendor_name = ModelSim
+source_file = 1, D:/GITEA/altera/MainController/MainController.bdf
+source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.qip
+source_file = 1, D:/GITEA/altera/MainController/AlteraPLL.vhd
+source_file = 1, D:/GITEA/altera/MainController/RAM.vhd
+source_file = 1, D:/GITEA/altera/MainController/LedBlink.vhd
+source_file = 1, D:/GITEA/altera/MainController/db/MainController.cbx.xml
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_b.vhd
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/vhdl/ieee/timing_p.vhd
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/aglobal131.inc
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, d:/intelfpga/13.1/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, D:/GITEA/altera/MainController/db/alterapll_altpll.v
+design_name = MainController
+instance = comp, \Data[7]~output\, Data[7]~output, MainController, 1
+instance = comp, \Data[6]~output\, Data[6]~output, MainController, 1
+instance = comp, \Data[5]~output\, Data[5]~output, MainController, 1
+instance = comp, \Data[4]~output\, Data[4]~output, MainController, 1
+instance = comp, \Data[3]~output\, Data[3]~output, MainController, 1
+instance = comp, \Data[2]~output\, Data[2]~output, MainController, 1
+instance = comp, \Data[1]~output\, Data[1]~output, MainController, 1
+instance = comp, \Data[0]~output\, Data[0]~output, MainController, 1
+instance = comp, \FPGA_LED_1~output\, FPGA_LED_1~output, MainController, 1
+instance = comp, \FPGA_CLK~input\, FPGA_CLK~input, MainController, 1
+instance = comp, \FPGA_CLK~inputclkctrl\, FPGA_CLK~inputclkctrl, MainController, 1
+instance = comp, \inst2|counter[0]~24\, inst2|counter[0]~24, MainController, 1
+instance = comp, \inst2|counter[0]\, inst2|counter[0], MainController, 1
+instance = comp, \inst2|counter[1]~26\, inst2|counter[1]~26, MainController, 1
+instance = comp, \inst2|counter[1]\, inst2|counter[1], MainController, 1
+instance = comp, \inst2|counter[2]~28\, inst2|counter[2]~28, MainController, 1
+instance = comp, \inst2|counter[2]\, inst2|counter[2], MainController, 1
+instance = comp, \inst2|counter[3]~30\, inst2|counter[3]~30, MainController, 1
+instance = comp, \inst2|counter[3]\, inst2|counter[3], MainController, 1
+instance = comp, \inst2|counter[4]~32\, inst2|counter[4]~32, MainController, 1
+instance = comp, \inst2|counter[4]\, inst2|counter[4], MainController, 1
+instance = comp, \inst2|counter[5]~34\, inst2|counter[5]~34, MainController, 1
+instance = comp, \inst2|counter[5]\, inst2|counter[5], MainController, 1
+instance = comp, \inst2|counter[6]~36\, inst2|counter[6]~36, MainController, 1
+instance = comp, \inst2|counter[6]\, inst2|counter[6], MainController, 1
+instance = comp, \inst2|counter[7]~38\, inst2|counter[7]~38, MainController, 1
+instance = comp, \inst2|counter[7]\, inst2|counter[7], MainController, 1
+instance = comp, \inst2|counter[8]~40\, inst2|counter[8]~40, MainController, 1
+instance = comp, \inst2|counter[8]\, inst2|counter[8], MainController, 1
+instance = comp, \inst2|counter[9]~42\, inst2|counter[9]~42, MainController, 1
+instance = comp, \inst2|counter[9]\, inst2|counter[9], MainController, 1
+instance = comp, \inst2|counter[10]~44\, inst2|counter[10]~44, MainController, 1
+instance = comp, \inst2|counter[10]\, inst2|counter[10], MainController, 1
+instance = comp, \inst2|counter[11]~46\, inst2|counter[11]~46, MainController, 1
+instance = comp, \inst2|counter[11]\, inst2|counter[11], MainController, 1
+instance = comp, \inst2|counter[12]~48\, inst2|counter[12]~48, MainController, 1
+instance = comp, \inst2|counter[12]\, inst2|counter[12], MainController, 1
+instance = comp, \inst2|counter[13]~50\, inst2|counter[13]~50, MainController, 1
+instance = comp, \inst2|counter[13]\, inst2|counter[13], MainController, 1
+instance = comp, \inst2|counter[14]~52\, inst2|counter[14]~52, MainController, 1
+instance = comp, \inst2|counter[14]\, inst2|counter[14], MainController, 1
+instance = comp, \inst2|counter[15]~54\, inst2|counter[15]~54, MainController, 1
+instance = comp, \inst2|counter[15]\, inst2|counter[15], MainController, 1
+instance = comp, \inst2|counter[16]~56\, inst2|counter[16]~56, MainController, 1
+instance = comp, \inst2|counter[16]\, inst2|counter[16], MainController, 1
+instance = comp, \inst2|counter[17]~58\, inst2|counter[17]~58, MainController, 1
+instance = comp, \inst2|counter[17]\, inst2|counter[17], MainController, 1
+instance = comp, \inst2|LessThan0~0\, inst2|LessThan0~0, MainController, 1
+instance = comp, \inst2|counter[18]~60\, inst2|counter[18]~60, MainController, 1
+instance = comp, \inst2|counter[18]\, inst2|counter[18], MainController, 1
+instance = comp, \inst2|counter[19]~62\, inst2|counter[19]~62, MainController, 1
+instance = comp, \inst2|counter[19]\, inst2|counter[19], MainController, 1
+instance = comp, \inst2|counter[20]~64\, inst2|counter[20]~64, MainController, 1
+instance = comp, \inst2|counter[20]\, inst2|counter[20], MainController, 1
+instance = comp, \inst2|counter[21]~66\, inst2|counter[21]~66, MainController, 1
+instance = comp, \inst2|counter[21]\, inst2|counter[21], MainController, 1
+instance = comp, \inst2|counter[22]~68\, inst2|counter[22]~68, MainController, 1
+instance = comp, \inst2|counter[22]\, inst2|counter[22], MainController, 1
+instance = comp, \inst2|counter[23]~70\, inst2|counter[23]~70, MainController, 1
+instance = comp, \inst2|counter[23]\, inst2|counter[23], MainController, 1
+instance = comp, \inst2|LessThan0~1\, inst2|LessThan0~1, MainController, 1
+instance = comp, \inst2|LessThan0~2\, inst2|LessThan0~2, MainController, 1
+instance = comp, \inst2|LessThan0~5\, inst2|LessThan0~5, MainController, 1
+instance = comp, \inst2|LessThan0~3\, inst2|LessThan0~3, MainController, 1
+instance = comp, \inst2|LessThan0~4\, inst2|LessThan0~4, MainController, 1
+instance = comp, \inst2|LessThan0~6\, inst2|LessThan0~6, MainController, 1
+instance = comp, \inst2|LessThan0~7\, inst2|LessThan0~7, MainController, 1
+instance = comp, \inst2|LessThan0~8\, inst2|LessThan0~8, MainController, 1
+instance = comp, \inst2|ledBuf~0\, inst2|ledBuf~0, MainController, 1
+instance = comp, \inst2|ledBuf\, inst2|ledBuf, MainController, 1
+instance = comp, \Address[7]~input\, Address[7]~input, MainController, 1
+instance = comp, \Address[6]~input\, Address[6]~input, MainController, 1
+instance = comp, \Address[5]~input\, Address[5]~input, MainController, 1
+instance = comp, \Address[4]~input\, Address[4]~input, MainController, 1
+instance = comp, \Address[3]~input\, Address[3]~input, MainController, 1
+instance = comp, \Address[2]~input\, Address[2]~input, MainController, 1
+instance = comp, \Address[1]~input\, Address[1]~input, MainController, 1
+instance = comp, \Address[0]~input\, Address[0]~input, MainController, 1
+instance = comp, \nOE~input\, nOE~input, MainController, 1
+instance = comp, \nWE~input\, nWE~input, MainController, 1
+instance = comp, \nCE~input\, nCE~input, MainController, 1
+instance = comp, \Data[7]~input\, Data[7]~input, MainController, 1
+instance = comp, \Data[6]~input\, Data[6]~input, MainController, 1
+instance = comp, \Data[5]~input\, Data[5]~input, MainController, 1
+instance = comp, \Data[4]~input\, Data[4]~input, MainController, 1
+instance = comp, \Data[3]~input\, Data[3]~input, MainController, 1
+instance = comp, \Data[2]~input\, Data[2]~input, MainController, 1
+instance = comp, \Data[1]~input\, Data[1]~input, MainController, 1
+instance = comp, \Data[0]~input\, Data[0]~input, MainController, 1
diff --git a/MainController/simulation/modelsim/MainController_vhd.sdo b/MainController/simulation/modelsim/MainController_vhd.sdo
new file mode 100644
index 0000000..7a8f05c
--- /dev/null
+++ b/MainController/simulation/modelsim/MainController_vhd.sdo
@@ -0,0 +1,949 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C25Q240C8 Package PQFP240
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C25Q240C8,
+// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "MainController")
+  (DATE "03/12/2024 16:24:29")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\FPGA_LED_1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1403:1403:1403) (1502:1502:1502))
+        (IOPATH i o (2195:2195:2195) (2297:2297:2297))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\FPGA_CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (899:899:899) (1014:1014:1014))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\FPGA_CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (190:190:190) (179:179:179))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[0\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (567:567:567) (600:600:600))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[1\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (576:576:576) (592:592:592))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[2\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (566:566:566) (594:594:594))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[3\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (423:423:423))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[4\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (615:615:615))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[5\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (342:342:342) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[6\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (425:425:425))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[7\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (561:561:561) (592:592:592))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[8\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (423:423:423))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[9\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1920:1920:1920) (1930:1930:1930))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[10\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (341:341:341) (421:421:421))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[11\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (434:434:434))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2413:2413:2413))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (1472:1472:1472) (1612:1612:1612))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[12\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (340:340:340) (422:422:422))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[13\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (357:357:357) (434:434:434))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[14\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (358:358:358) (435:435:435))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[15\]\~54\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (460:460:460))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[16\]\~56\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (359:359:359) (436:436:436))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[17\]\~58\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (362:362:362) (447:447:447))
+        (IOPATH dataa combout (461:461:461) (481:481:481))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (866:866:866))
+        (PORT datab (635:635:635) (645:645:645))
+        (PORT datac (534:534:534) (562:562:562))
+        (PORT datad (572:572:572) (584:584:584))
+        (IOPATH dataa combout (438:438:438) (448:448:448))
+        (IOPATH datab combout (440:440:440) (462:462:462))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[18\]\~60\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (436:436:436))
+        (IOPATH dataa combout (471:471:471) (472:472:472))
+        (IOPATH dataa cout (552:552:552) (416:416:416))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[18\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1919:1919:1919) (1929:1929:1929))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[19\]\~62\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (425:425:425))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[19\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[20\]\~64\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (426:426:426))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[20\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[21\]\~66\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (424:424:424))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[21\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[22\]\~68\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (428:428:428))
+        (IOPATH datab combout (472:472:472) (473:473:473))
+        (IOPATH datab cout (565:565:565) (421:421:421))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+        (IOPATH cin cout (73:73:73) (73:73:73))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[22\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|counter\[23\]\~70\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (821:821:821) (810:810:810))
+        (IOPATH dataa combout (471:471:471) (481:481:481))
+        (IOPATH cin combout (607:607:607) (577:577:577))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|counter\[23\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2410:2410:2410) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (PORT sclr (951:951:951) (989:989:989))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+      (HOLD sclr (posedge clk) (212:212:212))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (435:435:435))
+        (PORT datab (342:342:342) (425:425:425))
+        (PORT datac (302:302:302) (385:385:385))
+        (PORT datad (302:302:302) (378:378:378))
+        (IOPATH dataa combout (420:420:420) (428:428:428))
+        (IOPATH datab combout (432:432:432) (433:433:433))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (427:427:427))
+        (PORT datac (776:776:776) (761:761:761))
+        (PORT datad (237:237:237) (256:256:256))
+        (IOPATH datab combout (473:473:473) (487:487:487))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (434:434:434))
+        (PORT datab (343:343:343) (424:424:424))
+        (PORT datac (319:319:319) (396:396:396))
+        (PORT datad (304:304:304) (379:379:379))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (361:361:361) (445:445:445))
+        (PORT datab (359:359:359) (437:437:437))
+        (PORT datac (318:318:318) (396:396:396))
+        (PORT datad (319:319:319) (389:389:389))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (457:457:457) (489:489:489))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (613:613:613))
+        (PORT datab (342:342:342) (424:424:424))
+        (PORT datac (301:301:301) (385:385:385))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (481:481:481) (491:491:491))
+        (IOPATH datab combout (494:494:494) (496:496:496))
+        (IOPATH datac combout (324:324:324) (315:315:315))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (438:438:438))
+        (PORT datab (344:344:344) (427:427:427))
+        (PORT datac (235:235:235) (262:262:262))
+        (PORT datad (237:237:237) (255:255:255))
+        (IOPATH dataa combout (393:393:393) (398:398:398))
+        (IOPATH datab combout (393:393:393) (408:408:408))
+        (IOPATH datac combout (324:324:324) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (617:617:617))
+        (PORT datab (345:345:345) (429:429:429))
+        (PORT datac (541:541:541) (559:559:559))
+        (PORT datad (816:816:816) (741:741:741))
+        (IOPATH dataa combout (471:471:471) (453:453:453))
+        (IOPATH datab combout (472:472:472) (452:452:452))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|LessThan0\~8\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (464:464:464))
+        (PORT datab (531:531:531) (492:492:492))
+        (PORT datac (235:235:235) (262:262:262))
+        (PORT datad (236:236:236) (255:255:255))
+        (IOPATH dataa combout (456:456:456) (486:486:486))
+        (IOPATH datab combout (454:454:454) (473:473:473))
+        (IOPATH datac combout (327:327:327) (316:316:316))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|ledBuf\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (747:747:747) (674:674:674))
+        (IOPATH datac combout (462:462:462) (482:482:482))
+        (IOPATH datad combout (177:177:177) (155:155:155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\inst2\|ledBuf\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2411:2411:2411) (2414:2414:2414))
+        (PORT d (99:99:99) (115:115:115))
+        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (212:212:212))
+    )
+  )
+)