1559 lines
178 KiB
Plaintext
1559 lines
178 KiB
Plaintext
|
TimeQuest Timing Analyzer report for MainController
|
||
|
|
Tue Mar 12 16:24:27 2024
|
||
|
|
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||
|
|
|
||
|
|
|
||
|
|
---------------------
|
||
|
|
; Table of Contents ;
|
||
|
|
---------------------
|
||
|
|
1. Legal Notice
|
||
|
|
2. TimeQuest Timing Analyzer Summary
|
||
|
|
3. Parallel Compilation
|
||
|
|
4. Clocks
|
||
|
|
5. Slow 1200mV 85C Model Fmax Summary
|
||
|
|
6. Timing Closure Recommendations
|
||
|
|
7. Slow 1200mV 85C Model Setup Summary
|
||
|
|
8. Slow 1200mV 85C Model Hold Summary
|
||
|
|
9. Slow 1200mV 85C Model Recovery Summary
|
||
|
|
10. Slow 1200mV 85C Model Removal Summary
|
||
|
|
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
|
||
|
|
12. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
|
||
|
|
13. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
|
||
|
|
14. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
|
||
|
|
15. Clock to Output Times
|
||
|
|
16. Minimum Clock to Output Times
|
||
|
|
17. Slow 1200mV 85C Model Metastability Report
|
||
|
|
18. Slow 1200mV 0C Model Fmax Summary
|
||
|
|
19. Slow 1200mV 0C Model Setup Summary
|
||
|
|
20. Slow 1200mV 0C Model Hold Summary
|
||
|
|
21. Slow 1200mV 0C Model Recovery Summary
|
||
|
|
22. Slow 1200mV 0C Model Removal Summary
|
||
|
|
23. Slow 1200mV 0C Model Minimum Pulse Width Summary
|
||
|
|
24. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
|
||
|
|
25. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
|
||
|
|
26. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
|
||
|
|
27. Clock to Output Times
|
||
|
|
28. Minimum Clock to Output Times
|
||
|
|
29. Slow 1200mV 0C Model Metastability Report
|
||
|
|
30. Fast 1200mV 0C Model Setup Summary
|
||
|
|
31. Fast 1200mV 0C Model Hold Summary
|
||
|
|
32. Fast 1200mV 0C Model Recovery Summary
|
||
|
|
33. Fast 1200mV 0C Model Removal Summary
|
||
|
|
34. Fast 1200mV 0C Model Minimum Pulse Width Summary
|
||
|
|
35. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
|
||
|
|
36. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
|
||
|
|
37. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
|
||
|
|
38. Clock to Output Times
|
||
|
|
39. Minimum Clock to Output Times
|
||
|
|
40. Fast 1200mV 0C Model Metastability Report
|
||
|
|
41. Multicorner Timing Analysis Summary
|
||
|
|
42. Clock to Output Times
|
||
|
|
43. Minimum Clock to Output Times
|
||
|
|
44. Board Trace Model Assignments
|
||
|
|
45. Input Transition Times
|
||
|
|
46. Slow Corner Signal Integrity Metrics
|
||
|
|
47. Fast Corner Signal Integrity Metrics
|
||
|
|
48. Setup Transfers
|
||
|
|
49. Hold Transfers
|
||
|
|
50. Report TCCS
|
||
|
|
51. Report RSKM
|
||
|
|
52. Unconstrained Paths
|
||
|
|
53. TimeQuest Timing Analyzer Messages
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
----------------
|
||
|
|
; Legal Notice ;
|
||
|
|
----------------
|
||
|
|
Copyright (C) 1991-2013 Altera Corporation
|
||
|
|
Your use of Altera Corporation's design tools, logic functions
|
||
|
|
and other software and tools, and its AMPP partner logic
|
||
|
|
functions, and any output files from any of the foregoing
|
||
|
|
(including device programming or simulation files), and any
|
||
|
|
associated documentation or information are expressly subject
|
||
|
|
to the terms and conditions of the Altera Program License
|
||
|
|
Subscription Agreement, Altera MegaCore Function License
|
||
|
|
Agreement, or other applicable license agreement, including,
|
||
|
|
without limitation, that your use is for the sole purpose of
|
||
|
|
programming logic devices manufactured by Altera and sold by
|
||
|
|
Altera or its authorized distributors. Please refer to the
|
||
|
|
applicable agreement for further details.
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------+
|
||
|
|
; TimeQuest Timing Analyzer Summary ;
|
||
|
|
+--------------------+-----------------------------------------------------+
|
||
|
|
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
|
||
|
|
; Revision Name ; MainController ;
|
||
|
|
; Device Family ; Cyclone III ;
|
||
|
|
; Device Name ; EP3C25Q240C8 ;
|
||
|
|
; Timing Models ; Final ;
|
||
|
|
; Delay Model ; Combined ;
|
||
|
|
; Rise/Fall Delays ; Enabled ;
|
||
|
|
+--------------------+-----------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------+
|
||
|
|
; Parallel Compilation ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
; Processors ; Number ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
; Number detected on machine ; 8 ;
|
||
|
|
; Maximum allowed ; 4 ;
|
||
|
|
; ; ;
|
||
|
|
; Average used ; 1.00 ;
|
||
|
|
; Maximum used ; 4 ;
|
||
|
|
; ; ;
|
||
|
|
; Usage by Processor ; % Time Used ;
|
||
|
|
; Processor 1 ; 100.0% ;
|
||
|
|
; Processors 2-4 ; < 0.1% ;
|
||
|
|
; Processors 5-8 ; 0.0% ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Clocks ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
|
||
|
|
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
|
||
|
|
; FPGA_CLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK } ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Fmax Summary ;
|
||
|
|
+------------+-----------------+------------+------+
|
||
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||
|
|
+------------+-----------------+------------+------+
|
||
|
|
; 201.86 MHz ; 201.86 MHz ; FPGA_CLK ; ;
|
||
|
|
+------------+-----------------+------------+------+
|
||
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------
|
||
|
|
; Timing Closure Recommendations ;
|
||
|
|
----------------------------------
|
||
|
|
HTML report is unavailable in plain text report export.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Setup Summary ;
|
||
|
|
+----------+--------+-----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+-----------------+
|
||
|
|
; FPGA_CLK ; -3.954 ; -84.790 ;
|
||
|
|
+----------+--------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Hold Summary ;
|
||
|
|
+----------+-------+-----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+-------+-----------------+
|
||
|
|
; FPGA_CLK ; 0.435 ; 0.000 ;
|
||
|
|
+----------+-------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
------------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Recovery Summary ;
|
||
|
|
------------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Removal Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
|
||
|
|
+----------+--------+-------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+-------------------------------+
|
||
|
|
; FPGA_CLK ; -3.000 ; -40.175 ;
|
||
|
|
+----------+--------+-------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Setup: 'FPGA_CLK' ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.954 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.876 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.947 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.869 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.821 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.253 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.809 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 4.241 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.743 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.665 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.674 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.596 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.665 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.587 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.610 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.532 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.557 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.479 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.546 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.978 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.535 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.569 ; 3.967 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.876 ;
|
||
|
|
; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ;
|
||
|
|
; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ;
|
||
|
|
; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ;
|
||
|
|
; -3.477 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.391 ; 4.869 ;
|
||
|
|
; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ;
|
||
|
|
; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ;
|
||
|
|
; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ;
|
||
|
|
; -3.475 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.079 ; 4.397 ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Hold: 'FPGA_CLK' ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.435 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 0.746 ;
|
||
|
|
; 0.611 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.392 ;
|
||
|
|
; 0.612 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.393 ;
|
||
|
|
; 0.620 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.402 ;
|
||
|
|
; 0.629 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.411 ;
|
||
|
|
; 0.629 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.410 ;
|
||
|
|
; 0.726 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.037 ;
|
||
|
|
; 0.729 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.040 ;
|
||
|
|
; 0.729 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.039 ;
|
||
|
|
; 0.730 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.041 ;
|
||
|
|
; 0.730 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.041 ;
|
||
|
|
; 0.731 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.041 ;
|
||
|
|
; 0.731 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.041 ;
|
||
|
|
; 0.732 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.042 ;
|
||
|
|
; 0.733 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.043 ;
|
||
|
|
; 0.742 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.523 ;
|
||
|
|
; 0.744 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.054 ;
|
||
|
|
; 0.746 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.037 ;
|
||
|
|
; 0.746 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.056 ;
|
||
|
|
; 0.748 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.039 ;
|
||
|
|
; 0.749 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.040 ;
|
||
|
|
; 0.750 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.041 ;
|
||
|
|
; 0.751 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.532 ;
|
||
|
|
; 0.758 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.540 ;
|
||
|
|
; 0.760 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.541 ;
|
||
|
|
; 0.760 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.542 ;
|
||
|
|
; 0.763 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.054 ;
|
||
|
|
; 0.766 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.057 ;
|
||
|
|
; 0.767 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.549 ;
|
||
|
|
; 0.769 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.551 ;
|
||
|
|
; 0.769 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.550 ;
|
||
|
|
; 0.771 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.062 ;
|
||
|
|
; 0.776 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.558 ;
|
||
|
|
; 0.785 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.567 ;
|
||
|
|
; 0.809 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.590 ;
|
||
|
|
; 0.858 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.639 ;
|
||
|
|
; 0.882 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.663 ;
|
||
|
|
; 0.891 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.672 ;
|
||
|
|
; 0.892 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.673 ;
|
||
|
|
; 0.898 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.680 ;
|
||
|
|
; 0.900 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.682 ;
|
||
|
|
; 0.900 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.681 ;
|
||
|
|
; 0.906 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.688 ;
|
||
|
|
; 0.907 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.689 ;
|
||
|
|
; 0.909 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.690 ;
|
||
|
|
; 0.915 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.697 ;
|
||
|
|
; 0.916 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.697 ;
|
||
|
|
; 0.916 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.698 ;
|
||
|
|
; 0.925 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.707 ;
|
||
|
|
; 0.959 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.250 ;
|
||
|
|
; 0.960 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.741 ;
|
||
|
|
; 0.963 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.744 ;
|
||
|
|
; 0.966 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.257 ;
|
||
|
|
; 0.973 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.264 ;
|
||
|
|
; 0.978 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.269 ;
|
||
|
|
; 0.979 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.270 ;
|
||
|
|
; 0.986 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.767 ;
|
||
|
|
; 1.023 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.804 ;
|
||
|
|
; 1.032 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.813 ;
|
||
|
|
; 1.038 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.820 ;
|
||
|
|
; 1.046 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.828 ;
|
||
|
|
; 1.055 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.837 ;
|
||
|
|
; 1.056 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.838 ;
|
||
|
|
; 1.057 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.838 ;
|
||
|
|
; 1.081 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.392 ;
|
||
|
|
; 1.085 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.395 ;
|
||
|
|
; 1.085 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.395 ;
|
||
|
|
; 1.090 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.400 ;
|
||
|
|
; 1.091 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.402 ;
|
||
|
|
; 1.093 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.403 ;
|
||
|
|
; 1.094 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.404 ;
|
||
|
|
; 1.098 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.408 ;
|
||
|
|
; 1.099 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.409 ;
|
||
|
|
; 1.100 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.411 ;
|
||
|
|
; 1.103 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.413 ;
|
||
|
|
; 1.103 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.884 ;
|
||
|
|
; 1.110 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.401 ;
|
||
|
|
; 1.117 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.898 ;
|
||
|
|
; 1.118 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.409 ;
|
||
|
|
; 1.122 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.903 ;
|
||
|
|
; 1.126 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.417 ;
|
||
|
|
; 1.127 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.418 ;
|
||
|
|
; 1.136 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.079 ; 1.427 ;
|
||
|
|
; 1.138 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.919 ;
|
||
|
|
; 1.163 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.944 ;
|
||
|
|
; 1.165 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.571 ; 1.948 ;
|
||
|
|
; 1.167 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.477 ;
|
||
|
|
; 1.172 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.953 ;
|
||
|
|
; 1.186 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.968 ;
|
||
|
|
; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ;
|
||
|
|
; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ;
|
||
|
|
; 1.195 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.570 ; 1.977 ;
|
||
|
|
; 1.197 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.569 ; 1.978 ;
|
||
|
|
; 1.212 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.523 ;
|
||
|
|
; 1.216 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.526 ;
|
||
|
|
; 1.216 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.526 ;
|
||
|
|
; 1.221 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.532 ;
|
||
|
|
; 1.223 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.534 ;
|
||
|
|
; 1.225 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.098 ; 1.535 ;
|
||
|
|
; 1.231 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.099 ; 1.542 ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK' ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; 0.258 ; 0.446 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; 0.265 ; 0.453 ; 0.188 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; 0.325 ; 0.545 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; 0.326 ; 0.546 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; 0.332 ; 0.552 ; 0.220 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ;
|
||
|
|
; 0.395 ; 0.395 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ;
|
||
|
|
; 0.395 ; 0.395 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ;
|
||
|
|
; 0.398 ; 0.398 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ;
|
||
|
|
; 0.405 ; 0.405 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 7.359 ; 7.560 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Minimum Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 7.176 ; 7.373 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Metastability Report ;
|
||
|
|
----------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Fmax Summary ;
|
||
|
|
+-----------+-----------------+------------+------+
|
||
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||
|
|
+-----------+-----------------+------------+------+
|
||
|
|
; 214.5 MHz ; 214.5 MHz ; FPGA_CLK ; ;
|
||
|
|
+-----------+-----------------+------------+------+
|
||
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Setup Summary ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
; FPGA_CLK ; -3.662 ; -77.889 ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Hold Summary ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
; FPGA_CLK ; 0.384 ; 0.000 ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Recovery Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Removal Summary ;
|
||
|
|
----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
; FPGA_CLK ; -3.000 ; -40.175 ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Setup: 'FPGA_CLK' ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.662 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.593 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.657 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.588 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.562 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.023 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.553 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 4.014 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.484 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.415 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.394 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.325 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.386 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.317 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.361 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.292 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.289 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.750 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.285 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.216 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.279 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.541 ; 3.740 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.227 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.071 ; 4.158 ;
|
||
|
|
; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ;
|
||
|
|
; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ;
|
||
|
|
; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ;
|
||
|
|
; -3.210 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.381 ; 4.593 ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Hold: 'FPGA_CLK' ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.384 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.669 ;
|
||
|
|
; 0.545 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.283 ;
|
||
|
|
; 0.546 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.282 ;
|
||
|
|
; 0.551 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.287 ;
|
||
|
|
; 0.560 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.298 ;
|
||
|
|
; 0.563 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.299 ;
|
||
|
|
; 0.643 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.379 ;
|
||
|
|
; 0.651 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.389 ;
|
||
|
|
; 0.667 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.404 ;
|
||
|
|
; 0.667 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.405 ;
|
||
|
|
; 0.670 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.406 ;
|
||
|
|
; 0.676 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.960 ;
|
||
|
|
; 0.678 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.963 ;
|
||
|
|
; 0.679 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.963 ;
|
||
|
|
; 0.679 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.964 ;
|
||
|
|
; 0.679 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.964 ;
|
||
|
|
; 0.680 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.964 ;
|
||
|
|
; 0.680 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.418 ;
|
||
|
|
; 0.680 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.418 ;
|
||
|
|
; 0.682 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.420 ;
|
||
|
|
; 0.682 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 0.966 ;
|
||
|
|
; 0.682 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.967 ;
|
||
|
|
; 0.683 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.968 ;
|
||
|
|
; 0.684 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.421 ;
|
||
|
|
; 0.689 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.974 ;
|
||
|
|
; 0.693 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 0.978 ;
|
||
|
|
; 0.694 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.960 ;
|
||
|
|
; 0.694 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.430 ;
|
||
|
|
; 0.697 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.963 ;
|
||
|
|
; 0.697 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.435 ;
|
||
|
|
; 0.698 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.964 ;
|
||
|
|
; 0.699 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.965 ;
|
||
|
|
; 0.708 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.974 ;
|
||
|
|
; 0.713 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.979 ;
|
||
|
|
; 0.716 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 0.982 ;
|
||
|
|
; 0.764 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.501 ;
|
||
|
|
; 0.773 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.511 ;
|
||
|
|
; 0.785 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.523 ;
|
||
|
|
; 0.789 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.527 ;
|
||
|
|
; 0.789 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.526 ;
|
||
|
|
; 0.789 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.525 ;
|
||
|
|
; 0.791 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.527 ;
|
||
|
|
; 0.791 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.528 ;
|
||
|
|
; 0.795 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.531 ;
|
||
|
|
; 0.802 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.540 ;
|
||
|
|
; 0.802 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.540 ;
|
||
|
|
; 0.806 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.543 ;
|
||
|
|
; 0.810 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.548 ;
|
||
|
|
; 0.819 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.557 ;
|
||
|
|
; 0.826 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.562 ;
|
||
|
|
; 0.868 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.134 ;
|
||
|
|
; 0.872 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.138 ;
|
||
|
|
; 0.872 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.138 ;
|
||
|
|
; 0.884 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.150 ;
|
||
|
|
; 0.886 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.622 ;
|
||
|
|
; 0.892 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.158 ;
|
||
|
|
; 0.892 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.628 ;
|
||
|
|
; 0.895 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.633 ;
|
||
|
|
; 0.899 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.635 ;
|
||
|
|
; 0.907 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.645 ;
|
||
|
|
; 0.911 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.647 ;
|
||
|
|
; 0.916 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.653 ;
|
||
|
|
; 0.924 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.662 ;
|
||
|
|
; 0.932 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.670 ;
|
||
|
|
; 0.997 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.282 ;
|
||
|
|
; 0.998 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.283 ;
|
||
|
|
; 0.999 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.089 ; 1.283 ;
|
||
|
|
; 1.001 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.286 ;
|
||
|
|
; 1.002 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.287 ;
|
||
|
|
; 1.002 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.287 ;
|
||
|
|
; 1.003 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.288 ;
|
||
|
|
; 1.007 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.744 ;
|
||
|
|
; 1.013 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ;
|
||
|
|
; 1.013 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ;
|
||
|
|
; 1.013 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.298 ;
|
||
|
|
; 1.013 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.750 ;
|
||
|
|
; 1.016 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.301 ;
|
||
|
|
; 1.018 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.284 ;
|
||
|
|
; 1.018 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.754 ;
|
||
|
|
; 1.020 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.756 ;
|
||
|
|
; 1.029 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.767 ;
|
||
|
|
; 1.030 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.296 ;
|
||
|
|
; 1.030 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.296 ;
|
||
|
|
; 1.031 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.316 ;
|
||
|
|
; 1.032 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.769 ;
|
||
|
|
; 1.035 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.771 ;
|
||
|
|
; 1.038 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.304 ;
|
||
|
|
; 1.038 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.542 ; 1.775 ;
|
||
|
|
; 1.039 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.777 ;
|
||
|
|
; 1.047 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.313 ;
|
||
|
|
; 1.084 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.541 ; 1.820 ;
|
||
|
|
; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ;
|
||
|
|
; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ;
|
||
|
|
; 1.085 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.543 ; 1.823 ;
|
||
|
|
; 1.094 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.379 ;
|
||
|
|
; 1.100 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.385 ;
|
||
|
|
; 1.100 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.385 ;
|
||
|
|
; 1.118 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.071 ; 1.384 ;
|
||
|
|
; 1.119 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.404 ;
|
||
|
|
; 1.120 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.090 ; 1.405 ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; 0.253 ; 0.437 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; 0.293 ; 0.509 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; 0.301 ; 0.485 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; 0.343 ; 0.559 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ;
|
||
|
|
; 0.386 ; 0.386 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ;
|
||
|
|
; 0.388 ; 0.388 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ;
|
||
|
|
; 0.388 ; 0.388 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ;
|
||
|
|
; 0.434 ; 0.434 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 6.960 ; 7.231 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Minimum Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 6.795 ; 7.059 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
---------------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Metastability Report ;
|
||
|
|
---------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Setup Summary ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
; FPGA_CLK ; -1.072 ; -20.939 ;
|
||
|
|
+----------+--------+----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Hold Summary ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
; FPGA_CLK ; 0.179 ; 0.000 ;
|
||
|
|
+----------+-------+----------------+
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Recovery Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Removal Summary ;
|
||
|
|
----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
; FPGA_CLK ; -3.000 ; -35.949 ;
|
||
|
|
+----------+--------+------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Setup: 'FPGA_CLK' ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.072 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.022 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.071 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 2.021 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.022 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.775 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -1.004 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.757 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.985 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.935 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.969 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.919 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.927 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.877 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.906 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.856 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.894 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.647 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.892 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.234 ; 1.645 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.889 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; -0.037 ; 1.839 ;
|
||
|
|
; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ;
|
||
|
|
; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ;
|
||
|
|
; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ;
|
||
|
|
; -0.883 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 1.000 ; 0.152 ; 2.022 ;
|
||
|
|
+--------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Hold: 'FPGA_CLK' ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.179 ; LedBlink:inst2|ledBuf ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.044 ; 0.307 ;
|
||
|
|
; 0.248 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.566 ;
|
||
|
|
; 0.250 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.568 ;
|
||
|
|
; 0.259 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.577 ;
|
||
|
|
; 0.262 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.580 ;
|
||
|
|
; 0.263 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.581 ;
|
||
|
|
; 0.288 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.417 ;
|
||
|
|
; 0.289 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.418 ;
|
||
|
|
; 0.289 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.418 ;
|
||
|
|
; 0.290 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.419 ;
|
||
|
|
; 0.290 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.419 ;
|
||
|
|
; 0.291 ; LedBlink:inst2|counter[6] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.420 ;
|
||
|
|
; 0.291 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.420 ;
|
||
|
|
; 0.292 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.421 ;
|
||
|
|
; 0.292 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.421 ;
|
||
|
|
; 0.296 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.417 ;
|
||
|
|
; 0.296 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.425 ;
|
||
|
|
; 0.298 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[5] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.419 ;
|
||
|
|
; 0.298 ; LedBlink:inst2|counter[14] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.427 ;
|
||
|
|
; 0.299 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.420 ;
|
||
|
|
; 0.299 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.419 ;
|
||
|
|
; 0.305 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.425 ;
|
||
|
|
; 0.308 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.428 ;
|
||
|
|
; 0.309 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[15] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.429 ;
|
||
|
|
; 0.311 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.629 ;
|
||
|
|
; 0.314 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.632 ;
|
||
|
|
; 0.319 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.637 ;
|
||
|
|
; 0.322 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.640 ;
|
||
|
|
; 0.325 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.643 ;
|
||
|
|
; 0.326 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.644 ;
|
||
|
|
; 0.328 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.646 ;
|
||
|
|
; 0.329 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.647 ;
|
||
|
|
; 0.332 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.650 ;
|
||
|
|
; 0.334 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.652 ;
|
||
|
|
; 0.337 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.655 ;
|
||
|
|
; 0.340 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.658 ;
|
||
|
|
; 0.371 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[2] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.492 ;
|
||
|
|
; 0.371 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.492 ;
|
||
|
|
; 0.373 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[1] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.494 ;
|
||
|
|
; 0.376 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[4] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.497 ;
|
||
|
|
; 0.377 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.695 ;
|
||
|
|
; 0.380 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[0] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.501 ;
|
||
|
|
; 0.380 ; LedBlink:inst2|counter[9] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.698 ;
|
||
|
|
; 0.382 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.700 ;
|
||
|
|
; 0.385 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.703 ;
|
||
|
|
; 0.388 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.706 ;
|
||
|
|
; 0.388 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.706 ;
|
||
|
|
; 0.389 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[19] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.707 ;
|
||
|
|
; 0.389 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.707 ;
|
||
|
|
; 0.391 ; LedBlink:inst2|counter[18] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.709 ;
|
||
|
|
; 0.392 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.710 ;
|
||
|
|
; 0.392 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.710 ;
|
||
|
|
; 0.395 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.713 ;
|
||
|
|
; 0.398 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[3] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.716 ;
|
||
|
|
; 0.400 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.718 ;
|
||
|
|
; 0.401 ; LedBlink:inst2|counter[2] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.719 ;
|
||
|
|
; 0.403 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.721 ;
|
||
|
|
; 0.437 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.566 ;
|
||
|
|
; 0.439 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.568 ;
|
||
|
|
; 0.440 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[20] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.569 ;
|
||
|
|
; 0.445 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.763 ;
|
||
|
|
; 0.445 ; LedBlink:inst2|counter[13] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.574 ;
|
||
|
|
; 0.447 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.576 ;
|
||
|
|
; 0.447 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.576 ;
|
||
|
|
; 0.448 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.766 ;
|
||
|
|
; 0.450 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ;
|
||
|
|
; 0.450 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ;
|
||
|
|
; 0.450 ; LedBlink:inst2|counter[12] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ;
|
||
|
|
; 0.450 ; LedBlink:inst2|counter[23] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ;
|
||
|
|
; 0.450 ; LedBlink:inst2|counter[22] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.579 ;
|
||
|
|
; 0.451 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.769 ;
|
||
|
|
; 0.452 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[11] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.770 ;
|
||
|
|
; 0.453 ; LedBlink:inst2|counter[20] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.582 ;
|
||
|
|
; 0.454 ; LedBlink:inst2|counter[17] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.574 ;
|
||
|
|
; 0.455 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.773 ;
|
||
|
|
; 0.455 ; LedBlink:inst2|counter[7] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.773 ;
|
||
|
|
; 0.457 ; LedBlink:inst2|counter[8] ; LedBlink:inst2|counter[9] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.578 ;
|
||
|
|
; 0.457 ; LedBlink:inst2|counter[1] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.775 ;
|
||
|
|
; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[16] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.578 ;
|
||
|
|
; 0.458 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.776 ;
|
||
|
|
; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[17] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.586 ;
|
||
|
|
; 0.466 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.784 ;
|
||
|
|
; 0.467 ; LedBlink:inst2|counter[0] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.785 ;
|
||
|
|
; 0.469 ; LedBlink:inst2|counter[16] ; LedBlink:inst2|counter[18] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.036 ; 0.589 ;
|
||
|
|
; 0.472 ; LedBlink:inst2|counter[4] ; LedBlink:inst2|counter[10] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.790 ;
|
||
|
|
; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ;
|
||
|
|
; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[12] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ;
|
||
|
|
; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ;
|
||
|
|
; 0.495 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.813 ;
|
||
|
|
; 0.500 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.629 ;
|
||
|
|
; 0.502 ; LedBlink:inst2|counter[21] ; LedBlink:inst2|counter[23] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.631 ;
|
||
|
|
; 0.503 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[21] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.632 ;
|
||
|
|
; 0.503 ; LedBlink:inst2|counter[11] ; LedBlink:inst2|counter[14] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.632 ;
|
||
|
|
; 0.505 ; LedBlink:inst2|counter[3] ; LedBlink:inst2|counter[6] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.634 ;
|
||
|
|
; 0.506 ; LedBlink:inst2|counter[19] ; LedBlink:inst2|counter[22] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.635 ;
|
||
|
|
; 0.510 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[7] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.631 ;
|
||
|
|
; 0.511 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.829 ;
|
||
|
|
; 0.513 ; LedBlink:inst2|counter[5] ; LedBlink:inst2|counter[8] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.037 ; 0.634 ;
|
||
|
|
; 0.513 ; LedBlink:inst2|counter[10] ; LedBlink:inst2|counter[13] ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.045 ; 0.642 ;
|
||
|
|
; 0.514 ; LedBlink:inst2|counter[15] ; LedBlink:inst2|ledBuf ; FPGA_CLK ; FPGA_CLK ; 0.000 ; 0.234 ; 0.832 ;
|
||
|
|
+-------+----------------------------+----------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK' ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; FPGA_CLK ; Rise ; FPGA_CLK ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; -0.261 ; -0.077 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[14] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[19] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[20] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[21] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[22] ;
|
||
|
|
; -0.260 ; -0.076 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[23] ;
|
||
|
|
; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; -0.259 ; -0.075 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; -0.232 ; -0.048 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; -0.231 ; -0.047 ; 0.184 ; Low Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; -0.081 ; -0.081 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|ledBuf|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[12]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[13]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[14]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[19]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[20]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[21]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[22]|clk ;
|
||
|
|
; -0.080 ; -0.080 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[23]|clk ;
|
||
|
|
; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[10]|clk ;
|
||
|
|
; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[11]|clk ;
|
||
|
|
; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[3]|clk ;
|
||
|
|
; -0.079 ; -0.079 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[6]|clk ;
|
||
|
|
; -0.053 ; -0.053 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|o ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[0]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[15]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[16]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[17]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[18]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[1]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[2]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[4]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[5]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[7]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[8]|clk ;
|
||
|
|
; -0.052 ; -0.052 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; inst2|counter[9]|clk ;
|
||
|
|
; -0.041 ; -0.041 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|inclk[0] ;
|
||
|
|
; -0.041 ; -0.041 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~inputclkctrl|outclk ;
|
||
|
|
; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|i ;
|
||
|
|
; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; FPGA_CLK ; Rise ; FPGA_CLK~input|i ;
|
||
|
|
; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[15] ;
|
||
|
|
; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[16] ;
|
||
|
|
; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[17] ;
|
||
|
|
; 0.829 ; 1.045 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[18] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[0] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[1] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[2] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[4] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[5] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[7] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[8] ;
|
||
|
|
; 0.830 ; 1.046 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[9] ;
|
||
|
|
; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[10] ;
|
||
|
|
; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[11] ;
|
||
|
|
; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[3] ;
|
||
|
|
; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[6] ;
|
||
|
|
; 0.857 ; 1.073 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|ledBuf ;
|
||
|
|
; 0.858 ; 1.074 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[12] ;
|
||
|
|
; 0.858 ; 1.074 ; 0.216 ; High Pulse Width ; FPGA_CLK ; Rise ; LedBlink:inst2|counter[13] ;
|
||
|
|
+--------+--------------+----------------+------------------+----------+------------+--------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 3.617 ; 3.589 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Minimum Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 3.532 ; 3.507 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
---------------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Metastability Report ;
|
||
|
|
---------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------+
|
||
|
|
; Multicorner Timing Analysis Summary ;
|
||
|
|
+------------------+---------+-------+----------+---------+---------------------+
|
||
|
|
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
||
|
|
+------------------+---------+-------+----------+---------+---------------------+
|
||
|
|
; Worst-case Slack ; -3.954 ; 0.179 ; N/A ; N/A ; -3.000 ;
|
||
|
|
; FPGA_CLK ; -3.954 ; 0.179 ; N/A ; N/A ; -3.000 ;
|
||
|
|
; Design-wide TNS ; -84.79 ; 0.0 ; 0.0 ; 0.0 ; -40.175 ;
|
||
|
|
; FPGA_CLK ; -84.790 ; 0.000 ; N/A ; N/A ; -40.175 ;
|
||
|
|
+------------------+---------+-------+----------+---------+---------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 7.359 ; 7.560 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------+
|
||
|
|
; Minimum Clock to Output Times ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
; FPGA_LED_1 ; FPGA_CLK ; 3.532 ; 3.507 ; Rise ; FPGA_CLK ;
|
||
|
|
+------------+------------+-------+-------+------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Board Trace Model Assignments ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
; FPGA_LED_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; Data[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------+
|
||
|
|
; Input Transition Times ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
; Address[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Address[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; nOE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; nWE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; nCE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; Data[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; FPGA_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow Corner Signal Integrity Metrics ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; FPGA_LED_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0671 V ; 0.235 V ; 0.176 V ; 6.85e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0671 V ; 0.235 V ; 0.176 V ; 6.85e-10 s ; 6.31e-10 s ; Yes ; No ;
|
||
|
|
; Data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.08 V ; -0.00526 V ; 0.185 V ; 0.249 V ; 5.8e-09 s ; 4.45e-09 s ; Yes ; Yes ; 3.08 V ; 7.47e-07 V ; 3.08 V ; -0.00526 V ; 0.185 V ; 0.249 V ; 5.8e-09 s ; 4.45e-09 s ; Yes ; Yes ;
|
||
|
|
; Data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; Data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ; 3.08 V ; 7.47e-07 V ; 3.11 V ; -0.0527 V ; 0.256 V ; 0.175 V ; 7.07e-10 s ; 6.42e-10 s ; Yes ; No ;
|
||
|
|
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.58e-07 V ; 3.13 V ; -0.0964 V ; 0.164 V ; 0.127 V ; 3.14e-10 s ; 3.99e-10 s ; Yes ; Yes ; 3.08 V ; 2.58e-07 V ; 3.13 V ; -0.0964 V ; 0.164 V ; 0.127 V ; 3.14e-10 s ; 3.99e-10 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ; 3.08 V ; 5.01e-07 V ; 3.11 V ; -0.0488 V ; 0.191 V ; 0.217 V ; 1.08e-09 s ; 8.59e-10 s ; No ; No ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast Corner Signal Integrity Metrics ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; FPGA_LED_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.24e-07 V ; 3.6 V ; -0.129 V ; 0.303 V ; 0.209 V ; 4.54e-10 s ; 4.11e-10 s ; No ; No ; 3.46 V ; 1.24e-07 V ; 3.6 V ; -0.129 V ; 0.303 V ; 0.209 V ; 4.54e-10 s ; 4.11e-10 s ; No ; No ;
|
||
|
|
; Data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.48 V ; -0.0176 V ; 0.357 V ; 0.323 V ; 3.9e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.48 V ; -0.0176 V ; 0.357 V ; 0.323 V ; 3.9e-09 s ; 3.06e-09 s ; No ; No ;
|
||
|
|
; Data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; Data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.83e-07 V ; 3.58 V ; -0.143 V ; 0.305 V ; 0.24 V ; 4.6e-10 s ; 4.2e-10 s ; No ; No ;
|
||
|
|
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.53e-08 V ; 3.65 V ; -0.246 V ; 0.406 V ; 0.305 V ; 1.57e-10 s ; 2.13e-10 s ; No ; Yes ; 3.46 V ; 6.53e-08 V ; 3.65 V ; -0.246 V ; 0.406 V ; 0.305 V ; 1.57e-10 s ; 2.13e-10 s ; No ; Yes ;
|
||
|
|
; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.24e-07 V ; 3.57 V ; -0.0876 V ; 0.318 V ; 0.176 V ; 6.78e-10 s ; 6.15e-10 s ; No ; No ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Setup Transfers ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; FPGA_CLK ; FPGA_CLK ; 976 ; 0 ; 0 ; 0 ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Hold Transfers ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; FPGA_CLK ; FPGA_CLK ; 976 ; 0 ; 0 ; 0 ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report TCCS ;
|
||
|
|
---------------
|
||
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report RSKM ;
|
||
|
|
---------------
|
||
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------+
|
||
|
|
; Unconstrained Paths ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Property ; Setup ; Hold ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Illegal Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Input Ports ; 0 ; 0 ;
|
||
|
|
; Unconstrained Input Port Paths ; 0 ; 0 ;
|
||
|
|
; Unconstrained Output Ports ; 1 ; 1 ;
|
||
|
|
; Unconstrained Output Port Paths ; 1 ; 1 ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; TimeQuest Timing Analyzer Messages ;
|
||
|
|
+------------------------------------+
|
||
|
|
Info: *******************************************************************
|
||
|
|
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
|
||
|
|
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
|
||
|
|
Info: Processing started: Tue Mar 12 16:24:25 2024
|
||
|
|
Info: Command: quartus_sta MainController -c MainController
|
||
|
|
Info: qsta_default_script.tcl version: #1
|
||
|
|
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
|
||
|
|
Info (21077): Core supply voltage is 1.2V
|
||
|
|
Info (21077): Low junction temperature is 0 degrees C
|
||
|
|
Info (21077): High junction temperature is 85 degrees C
|
||
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'MainController.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332105): Deriving Clocks
|
||
|
|
Info (332105): create_clock -period 1.000 -name FPGA_CLK FPGA_CLK
|
||
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||
|
|
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||
|
|
Info: Analyzing Slow 1200mV 85C Model
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||
|
|
Info (332146): Worst-case setup slack is -3.954
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.954 -84.790 FPGA_CLK
|
||
|
|
Info (332146): Worst-case hold slack is 0.435
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.435 0.000 FPGA_CLK
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -40.175 FPGA_CLK
|
||
|
|
Info: Analyzing Slow 1200mV 0C Model
|
||
|
|
Info (334003): Started post-fitting delay annotation
|
||
|
|
Info (334004): Delay annotation completed successfully
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||
|
|
Info (332146): Worst-case setup slack is -3.662
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.662 -77.889 FPGA_CLK
|
||
|
|
Info (332146): Worst-case hold slack is 0.384
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.384 0.000 FPGA_CLK
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -40.175 FPGA_CLK
|
||
|
|
Info: Analyzing Fast 1200mV 0C Model
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
|
||
|
|
Info (332146): Worst-case setup slack is -1.072
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -1.072 -20.939 FPGA_CLK
|
||
|
|
Info (332146): Worst-case hold slack is 0.179
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.179 0.000 FPGA_CLK
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -35.949 FPGA_CLK
|
||
|
|
Info (332102): Design is not fully constrained for setup requirements
|
||
|
|
Info (332102): Design is not fully constrained for hold requirements
|
||
|
|
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||
|
|
Info: Peak virtual memory: 4700 megabytes
|
||
|
|
Info: Processing ended: Tue Mar 12 16:24:27 2024
|
||
|
|
Info: Elapsed time: 00:00:02
|
||
|
|
Info: Total CPU time (on all processors): 00:00:01
|
||
|
|
|
||
|
|
|