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Alexey
2024-10-16 16:03:37 +03:00
parent 6a08b0462d
commit 8939ab257f
750 changed files with 10725 additions and 350180 deletions
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108
MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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@@ -1,37 +1,20 @@
/************************************************************************
/**
**************************************************************************
* @file stm32f4xx_matlab.h
* @brief Заголовочный файл для работы с STM32F4xx в MATLAB.
**************************************************************************
@details
Данный файл является копией stm32f407xx.h с некоторыми изменениями:
- добавлен кейловский stdint.h (через "", вместо <>) (~170)
- добавлен cmsis_armcc_matlab.h с дефайнами из оригинального cmsis_armcc.h (~170)
- добавлен core_cm4.h с дефайнами из оригинального core_cm4.h (~170)
- добавлена структура имитирующая память МК (для работы дефайнов адресов регистров) (~950)
(надо допилить)
Необходимо допилить поддержку всех дефайнов, которые объявляются в
arm_acle.h, arm_compat.h, cmsis_armclang.h, cmsis_compiler.h, cmsis_version.h,
core_cm4.h, mpu_armv7.h, stddef
**************************************************************************/
/**
******************************************************************************
* @file stm32f407xx.h
* @author MCD Application Team
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
@@ -912,84 +895,9 @@ typedef struct
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */
#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */
#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */
#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */
#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
#define SRAM2_SIZE 0x4000UL /* (16 KB) */
#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
typedef struct _memory
{
//uint8_t RESERVED[FLASH_BASE_SHIFT];
uint8_t FLASH_BASE[FLASH_SIZE];
uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE];
uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE];
uint8_t SRAM1_BASE[SRAM1_SIZE];
uint8_t SRAM2_BASE[SRAM2_SIZE];
uint8_t SRAM1_BB_BASE[SRAM1_SIZE];
uint8_t SRAM2_BB_BASE[SRAM2_SIZE];
uint8_t PERIPH_BASE[PERIPH_SIZE];
uint8_t BKPSRAM_BASE[BKPSRAM_SIZE];
uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE];
uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE];
uint8_t FSMC_R_BASE[FSMC_R_SIZE];
}MCU_MemoryTypeDef;
extern MCU_MemoryTypeDef MCU_MEM;
DBGMCU_TypeDef DEBUG_MCU;
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */
#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */
#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */
#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1097,8 +1005,6 @@ DBGMCU_TypeDef DEBUG_MCU;
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
/*!< Debug MCU registers base address */
#define DBGMCU_BASE (&DEBUG_MCU)
/*!< USB registers base address */
#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
#define USB_OTG_FS_PERIPH_BASE 0x50000000UL